Article

Free access

New efficient algorithms for computing effective capacitance

Authors:

Andrew B. Kahng,

Sudhakar MudduAuthors Info & Claims

ISPD '98: Proceedings of the 1998 international symposium on Physical design

Pages 147 - 151

https://doi.org/10.1145/274535.274557

Published: 01 April 1998 Publication History

PDF eReader

Abstract

We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than previous methods for computing effective capacitance, with little or no loss of accuracy. Thus, the approach is suitable within the analysis loop for performance-driven iterative layout optimization. After reviewing previous gate load models and effective capacitance approximations, we separately derive our method for the cases of step and ramp waveform at the gate output, and note on-going extensions for the case of complex gates (e.g., channel-connected components). Experimental results using the new effective capacitance approach show that our resulting delay estimates are quite accurate — within 15% of IISPICE-computed delays on data corresponding to an 0.25µm microprocessor design.

References

[1]

W. C. Elmore, '~l'he Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers", Journal of Applied Physics 19, Jan. 1948, pp. 55-63.

Crossref

Google Scholar

[2]

A. B. Kalmg and S. Muddu, "Efficient Gate Delay Modeling for Large Interconnect Loads", Proc. IEEE Multi-Chip Module Conf., Feb. 1995 (Submitted to IEEE Trans. on CAD).

Google Scholar

[3]

A.B. Katmg and S. Muddu,' "Accurate Analytical Delay Models for VLSI Interconnects", IEEE Intl. Symposium on Circuits and Systems, Atlanta, May 1995.

Google Scholar

[4]

A. B. Kahng, K. Masuko and S. Muddu, "Analytical Delay Models for VLSI Interconnects Under Ramp Input", IEEE ICCAD, Nov. 1996.

Digital Library

Google Scholar

[5]

A.B. Kahng and S. Muddu, "A Glossary on Analysis and Modeling ofVLSI Interconnections", Manusc@t, February 1996.

Digital Library

Google Scholar

[6]

S. P. McCormick, "Modeling and Simulation of VLSI Interconnections with Moments", PhD Thes/s, MIT, June 1989.

Google Scholar

[7]

J. K. Ousterhout, "A Switch-level Timing Verifier for Digital MOS VLSI", IEEE Trans. on CAD, July 1985, pp. 336-349.

Digital Library

Google Scholar

[8]

P. R. O'Brien and T. L. Savarino, ''Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation", Proc. IEEE ICCAD, 1989, pp. 512-515.

Crossref

Google Scholar

[9]

P.R. O'Brien and T. L. Savarino, "Efficient On-Chip Delay Estimation for Leak3, Models of Multiple-Source Nets", Proc. IEEE Custom Integrated Circuits Conf., 1990, pp. 9.6.1-9.6.4.

Crossref

Google Scholar

[10]

L.T. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis", IEEE Trans. on CAD 9, Apr. 1990, pp.352- 366.

Digital Library

Google Scholar

[11]

J. Qian, S. PuIlela and L. Pillage, "Modeling the '`Effective Capacitance" for the RC Interconnect of CMOS gates", IEEE Trans. on CAD, December 1994, pp. 1526-1535.

Digital Library

Google Scholar

[12]

J. Rub~r~tein, P. Penfield and M. A. Horowitz, "Signal Delay in RC Tree Networks", IEEE Trans. on CAD, July 1983, pp. 202- 211.

Google Scholar

[13]

C. Ratzlaff, S. PuHela and L. Pillage, '`Modeling the RC Interconnect effects in a Hierarchical Timing Analyzer", Proc. 1EEE Custom Integrated Circuits Conference, May 1992, pp. 15.6.1-15.6.4.

Crossref

Google Scholar

[14]

Synopsys, "Design Compiler Family Reference Manual", version 3.3a, March 1995.

Google Scholar

Cited By

View all

JIANG MHUANG ZKUROKAWA ALI QLIN BINOUE Y(2011)A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load EffectIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E94.A.1201E94-A:5(1201-1209)Online publication date: 2011
https://doi.org/10.1587/transfun.E94.A.1201
Jiang MLi QHuang ZInoue Y(2010)A non-iterative effective capacitance model for CMOS gate delay computing2010 International Conference on Communications, Circuits and Systems (ICCCAS)10.1109/ICCCAS.2010.5581849(896-900)Online publication date: Jul-2010
https://doi.org/10.1109/ICCCAS.2010.5581849
JIANG MHUANG ZKUROKAWA AFANG SINOUE Y(2009)Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin ModelIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.2531E92-A:10(2531-2539)Online publication date: 2009
https://doi.org/10.1587/transfun.E92.A.2531
Show More Cited By

Index Terms

New efficient algorithms for computing effective capacitance
1. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation
  2. Integrated circuits

Recommendations

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads

In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance C_eff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new ...
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance C_eff concept is usually used to calculate the gate delay of interconnect loads. Many C_eff ...
Optimizing effective interconnect capacitance for FPGA power reduction
FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays

We propose a technique to reduce the effective parasitic capacitance of interconnect routing conductors in a bid to simultaneously reduce power consumption and improve delay. The parasitic capacitance reduction is achieved by ensuring routing conductors ...

Comments

Information & Contributors

Information

Published In

ISPD '98: Proceedings of the 1998 international symposium on Physical design

April 1998

220 pages

ISBN:158113021X

DOI:10.1145/274535

Chairman:
M. Sarrafzadeh
Northwestern Univ., Evanston, IL

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1998

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ISPD98

Sponsor:

SIGDA
IEEE-CAS
IEEE-CS

ISPD98: International Symposium on Physical Design

April 6 - 8, 1998

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

26
Total Citations
View Citations
392
Total Downloads

Downloads (Last 12 months)53
Downloads (Last 6 weeks)7

Reflects downloads up to 06 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

JIANG MHUANG ZKUROKAWA ALI QLIN BINOUE Y(2011)A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load EffectIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E94.A.1201E94-A:5(1201-1209)Online publication date: 2011
https://doi.org/10.1587/transfun.E94.A.1201
Jiang MLi QHuang ZInoue Y(2010)A non-iterative effective capacitance model for CMOS gate delay computing2010 International Conference on Communications, Circuits and Systems (ICCCAS)10.1109/ICCCAS.2010.5581849(896-900)Online publication date: Jul-2010
https://doi.org/10.1109/ICCCAS.2010.5581849
JIANG MHUANG ZKUROKAWA AFANG SINOUE Y(2009)Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin ModelIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.2531E92-A:10(2531-2539)Online publication date: 2009
https://doi.org/10.1587/transfun.E92.A.2531
Jiang MHuang ZKurokawa AInoue Y(2008)An advanced model for calculating the effective capacitance considering input waveform effect2008 International Conference on Communications, Circuits and Systems10.1109/ICCCAS.2008.4657957(1088-1092)Online publication date: May-2008
https://doi.org/10.1109/ICCCAS.2008.4657957
Wang JLi JYanamanamanda SVakati LMuchherla K(2006)Modeling the Driver Load in the Presence of Process VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.86273925:10(2264-2275)Online publication date: 1-Oct-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.862739
Liou JKrstic AJiang YCheng K(2006)Modeling, testing, and analysis for delay defects and noise effects in deep submicron devicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2003.81144222:6(756-769)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2003.811442
El-Moursy MFriedman E(2005)Shielding effect of on-chip interconnect inductanceIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.84231513:3(396-400)Online publication date: 1-Mar-2005
https://dl.acm.org/doi/10.1109/TVLSI.2004.842315
Nassif SLi Z(2005)A More Effective C_{EFF}Proceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.10(648-653)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.10
Gupta PKahng AMuddu S(2005)Quantifying Error in Dynamic Power Estimation of CMOS CircuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-005-6759-442:3(253-264)Online publication date: 1-Mar-2005
https://dl.acm.org/doi/10.1007/s10470-005-6759-4
Kaul HSylvester DBlaauw D(2004)Performance Optimization of Critical Nets Through Active ShieldingIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2004.83824751:12(2417-2435)Online publication date: Dec-2004
https://doi.org/10.1109/TCSI.2004.838247
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew

Optimizing effective interconnect capacitance for FPGA power reduction

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

Abstract

References

Cited By

Index Terms

Recommendations

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew

Optimizing effective interconnect capacitance for FPGA power reduction

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Get Access

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations