research-article

Shielding effect of on-chip interconnect inductance

Authors:

Magdy A. El-Moursy,

Eby G. FriedmanAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 13, Issue 3

Pages 396 - 400

https://doi.org/10.1109/TVLSI.2004.842315

Published: 01 March 2005 Publication History

Abstract

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.

References

[1]

W. C. Elmore, "The transient response of damped linear networks," J. Appl. Phys., vol. 19, pp. 55-63, Jan. 1948.

[2]

A. B. Kahng and S. Muddu, "Analysis of RC interconnections under ramp input," in Proc. ACM/IEEE Design Autom. Conf., Jun. 1996, pp. 533-538.

[3]

L. Chen, S. K. Gupta, and M. A. Breuer, "A new gate delay model for simultaneous switching and its applications," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2001, pp. 289-294.

[4]

V. Adler and E. G. Friedman, "Repeater design to reduce delay and power in resistive interconnect," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, pp. 607-616, May 1998.

[5]

P. R. O'Brien and T. L. Savarino, "Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1989, pp. 512-515.

[6]

J. Qian, S. Pullela, and L. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 13, pp. 1526-1535, Dec. 1994.

Digital Library

[7]

A. B. Kahng and S. Muddu, "New efficient algorithms for computing effective capacitance," in Proc. ACM Int. Symp. Physical Design, Apr. 1998, pp. 147-151.

[8]

C. V. Kashyap, C. J. Alpert, and A. Devgan, "An effective capacitance based delay metric for RC interconnect," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 2000, pp. 229-234.

[9]

A. Devgan and P. R. O'Brien, "Realizable reduction for RC interconnect circuits," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1999, pp. 204-207.

[10]

Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Figures of meritt o characterize the importance of on-chip inductance," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 7, pp. 442-449, Dec. 1999.

[11]

B. Krautr, S. Mehrotra, and V. Chandramoouli, "Including inductive effects in interconnect timing analysis," in Proc. IEEE Custom Integr. Circuits Conf., May 1999, pp. 445-452.

[12]

Y. I. Ismail and E. G. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 8, pp. 195-206, Apr. 2000.

Digital Library

[13]

R. Venkatesan, J. A. Davis, and J. D. Meindl, "Compact distributed RLC interconnect models--Part IV: Unified models for time delay, crosstalk, and repeater insertion," IEEE Trans. Electron Devices, vol. 50, pp. 1094-1101, Apr. 2003.

[14]

K. Banerjee and A. Mehrotra, "Analysis of on-chip inductance effects for distributed RLC interconnects," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 21, pp. 904-915, Aug. 2002.

Digital Library

[15]

K. T. Tang and E. G. Friedman, "Delay and power expressions characterizing a CMOS inverter driving an RLC load," in Proc. IEEE Int. Symp. Circuits Syst., vol. 3, May 2000, pp. 283-286.

[16]

X. Yang, C.-K. Chang, W. H. Ku, and R. J. Carragher, "Hurwitz stable reduced order modeling for RLC interconnect trees," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 2000, pp. 222-228.

[17]

A. B. Kahng and S. Muddu, "Efficientg ate delay modeling for large interconnect loads," in Proc. IEEE Multi-Chip Module Conf., Feb. 1996, pp. 202-207.

[18]

L. Yin and L. He, "An efficient analyt ical model of coupled on-chip RLC interconnects," in Proc. ACM/IEEE Design Autom. Conf., Jan. 2001, pp. 385-390.

[19]

M. A. El-Moursy and E. G. Friedman, "Shielding effectof on-chip interconnectinduct ance," in Proc. IEEE Great Lakes Symp. VLSI, Apr. 2003, pp. 165-170.

[20]

B. S. Cherkauer and E. G. Friedman, "A unified design methodology for CMOS tapered buffers," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 3, pp. 99-111, Mar. 1995.

Digital Library

Cited By

Chen GFriedman E(2006)Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraintsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.86375014:2(161-172)Online publication date: 1-Feb-2006
https://dl.acm.org/doi/10.1109/TVLSI.2005.863750

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Shielding effect of on-chip interconnect inductance
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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 13, Issue 3

March 2005

114 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 2005.

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IEEE Educational Activities Department

United States

Publication History

Published: 01 March 2005

Revised: 15 March 2004

Received: 15 November 2003

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Cited By

Chen GFriedman E(2006)Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraintsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.86375014:2(161-172)Online publication date: 1-Feb-2006
https://dl.acm.org/doi/10.1109/TVLSI.2005.863750

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