Article

Shielding effect of on-chip interconnect inductance

Authors:

Magdy A. El-Moursy,

Eby G. FriedmanAuthors Info & Claims

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

Pages 165 - 170

https://doi.org/10.1145/764808.764852

Published: 28 April 2003 Publication History

Abstract

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. The effective capacitance of an RLC load driven by a CMOS inverter is analytically modeled. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall signal propagation delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, thereby reducing the dynamic power dissipation. A reduction in power of 17% and area of 29% is achieved for an example circuit.

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Cited By

Abinash Roy Jingye Xu Chowdhury M(2007)Inductance aware performance and reliability analysis of high performance integrated circuits2007 IEEE International Conference on Electro/Information Technology10.1109/EIT.2007.4374478(91-95)Online publication date: May-2007
https://doi.org/10.1109/EIT.2007.4374478
El-Moursy MFriedman E(2007)Wire shaping of RLC interconnectsIntegration, the VLSI Journal10.1016/j.vlsi.2006.06.00240:4(461-472)Online publication date: 1-Jul-2007
https://dl.acm.org/doi/10.1016/j.vlsi.2006.06.002
Venkateswaran NBalaji SSridhar V(2005)Fault tolerant bus architecture for deep submicron based processorsACM SIGARCH Computer Architecture News10.1145/1055626.105564733:1(148-155)Online publication date: 1-Mar-2005
https://dl.acm.org/doi/10.1145/1055626.1055647
Show More Cited By

Index Terms

Shielding effect of on-chip interconnect inductance
1. Hardware
  1. Integrated circuits
  2. Robustness

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Published In

cover image ACM Conferences

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

April 2003

320 pages

ISBN:1581136773

DOI:10.1145/764808

General Chair:
Mircea Stan
University of Virginia
,
Program Chairs:
David Garrett
Bell Labs Research, Lucent Technologies
,
Kazuo Nakajima
University of Maryland

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 28 April 2003

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GLSVLSI03: Great Lakes Symposium on VLSI 2003

April 28 - 29, 2003

D. C., Washington, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Abinash Roy Jingye Xu Chowdhury M(2007)Inductance aware performance and reliability analysis of high performance integrated circuits2007 IEEE International Conference on Electro/Information Technology10.1109/EIT.2007.4374478(91-95)Online publication date: May-2007
https://doi.org/10.1109/EIT.2007.4374478
El-Moursy MFriedman E(2007)Wire shaping of RLC interconnectsIntegration, the VLSI Journal10.1016/j.vlsi.2006.06.00240:4(461-472)Online publication date: 1-Jul-2007
https://dl.acm.org/doi/10.1016/j.vlsi.2006.06.002
Venkateswaran NBalaji SSridhar V(2005)Fault tolerant bus architecture for deep submicron based processorsACM SIGARCH Computer Architecture News10.1145/1055626.105564733:1(148-155)Online publication date: 1-Mar-2005
https://dl.acm.org/doi/10.1145/1055626.1055647
El-Moursy MFriedman E(2005)Shielding effect of on-chip interconnect inductanceIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.84231513:3(396-400)Online publication date: 1-Mar-2005
https://dl.acm.org/doi/10.1109/TVLSI.2004.842315
Dong Gang Yang Yintang Li Yuejin (2005)Gate Delay Estimation Based on Close-Ended Line Model2005 6th International Conference on ASIC10.1109/ICASIC.2005.1611480(934-937)Online publication date: 2005
https://doi.org/10.1109/ICASIC.2005.1611480
El-Moursy MFriedman E(2005)Design Methodologies for on-Chip Inductive InterconnectInterconnect-Centric Design for Advanced SoC and NoC10.1007/1-4020-7836-6_4(85-124)Online publication date: 2005
https://doi.org/10.1007/1-4020-7836-6_4
El-Moursy MFriedman E(2003)Optimum wire shaping of an RLC interconnect2003 46th Midwest Symposium on Circuits and Systems10.1109/MWSCAS.2003.1562571(1459-1464)Online publication date: 2003
https://doi.org/10.1109/MWSCAS.2003.1562571

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