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COSY communication IP's

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W. J. M. SmitsAuthors Info & Claims

DAC '00: Proceedings of the 37th Annual Design Automation Conference

Pages 406 - 409

https://doi.org/10.1145/337292.337515

Published: 01 June 2000 Publication History

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Abstract

The Fsprit/OMI-COSY project defines transaction-levels to set-up the exchange of IP's in separating function from architecture and body-behavior from proprietary interfaces. These transaction-levels are supported by the “COSY COMMUNICATION IPs” that are presented in this paper. They implement onto Systems-On-Chip the extended Kahn Process Network that is defined in COSY for modeling signal processing applications. We present a generic implementation and performance model of these system-level communications and we illustrate specific implementations. They set system communications across software and hardware boundaries, and achieve bus independence through the Virtual Component Interface of the VSI Alliance. Finally, we describe the COSY-VCC flow that supports communication refinement from specification, to performance estimation, to implementation.

References

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J.Y Brunel et al., ~COSY: a methodology for system design based on reusable hardware & software IP's,>> in: J-Y. Roger (ed.), Technologies for the Information Society, IOS Press, 709-716, 1998

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[2]

J.-Y. Brunel et al., ~Communication Refinement in Video Systems on Chip,>> CODES'99, Rome, 1999, pp. 142-146

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D. Fairbank et al., ~The VSI Alliance: journey from vision to production,>> Electronic Design, vol. 46, no. 1, pp. 86-92, Jan 12 1998.

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G. Martin et al., ~Methodology and technology for design of communications and multimedia products via system-level IP integration,>> DAC, 1998

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E.A.de Kock et al., ~YAPI: Application Modeling for Signal Processing Systems,>> Submitted to DAC2000, Los Angeles, 2000

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Peter Clarke, ~Philips extends TriMedia reuse into Nexperia cores>> EE Times, Aug 30,1999

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Masood SKhan SHassan AKhalique F(2022)A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded SystemsElectronics10.3390/electronics1118294511:18(2945)Online publication date: 17-Sep-2022
https://doi.org/10.3390/electronics11182945
Grammatikakis MPapagrigoriou APetrakis PCoppola M(2016)Back-Annotating System-Level ModelsElectronic Design Automation for IC System Design, Verification, and Testing10.1201/b19569-16(275-304)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19569-16
Genius DMunier Kordon AZine El Abidine K(2013)Space optimal solution for data reordering in streaming applications on NoC based MPSoCJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.04.00159:7(455-467)Online publication date: 1-Aug-2013
https://dl.acm.org/doi/10.1016/j.sysarc.2013.04.001
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COSY communication IP's

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DAC '00: Proceedings of the 37th Annual Design Automation Conference

June 2000

819 pages

ISBN:1581131879

DOI:10.1145/337292

Chairman:
Giovanni De Micheli
Stanford Univ., Stanford, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 2000

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June 5 - 9, 2000

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https://doi.org/10.3390/electronics11182945
Grammatikakis MPapagrigoriou APetrakis PCoppola M(2016)Back-Annotating System-Level ModelsElectronic Design Automation for IC System Design, Verification, and Testing10.1201/b19569-16(275-304)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19569-16
Genius DMunier Kordon AZine El Abidine K(2013)Space optimal solution for data reordering in streaming applications on NoC based MPSoCJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.04.00159:7(455-467)Online publication date: 1-Aug-2013
https://dl.acm.org/doi/10.1016/j.sysarc.2013.04.001
Sharma HPatkar S(2013)A design methodology for optimally folded, pipelined architectures in VLSI applications using projective space latticesMicroprocessors & Microsystems10.1016/j.micpro.2013.02.00437:6-7(674-683)Online publication date: 1-Aug-2013
https://dl.acm.org/doi/10.1016/j.micpro.2013.02.004
Genius Del Abidine K(2012)A solution to the data re-ordering problem for multi-pipeline streaming applications on clustered MPSoC7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2012.6322892(1-8)Online publication date: Jul-2012
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Yehia KSafar MYouness HAbdElSalam MSalem A(2011)A design methodology for system level synthesis of multi-core system architectures2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)10.1109/SIECPC.2011.5876883(1-6)Online publication date: Apr-2011
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Genius DPouillon N(2011)Monitoring communication channels on a shared memory multi-processor system on chip6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2011.5981502(1-8)Online publication date: Jun-2011
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Genius DFaure EPouillon N(2011)Mapping a Telecommunication Application on a Multiprocessor System-on-ChipAlgorithm-Architecture Matching for Signal and Image Processing10.1007/978-90-481-9965-5_3(53-77)Online publication date: 2011
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A generic packet router IP for multi-processors network-on-chip

Design and Implementation of DES IP Core Based on LEON3 SOPC Platform

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A generic packet router IP for multi-processors network-on-chip

Design and Implementation of DES IP Core Based on LEON3 SOPC Platform

Communication refinement in video systems on chip

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