Resource allocation in a high clock rate microprocessor
Pages 98 - 109
Abstract
This paper discusses the design of a high clock rate (300MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. Recommendations are then made to increase the effectiveness of each of the models.
References
[1]
K. Diefendorff and M. Allen, "Organization of the Motorola 88110 Superscalar RISC Microprocessor," IEEE MICRO, April, 1992, pp. 40--63.
[2]
K. Diefendorff, R. Oehler, R. Hochspmng, "Evolution of the PowerPC Architecture," IEEE MICRO, April 1994, pp 34-49.
[3]
D. Ditzel and H. McLellan, "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero," 14th Annual Symposium on Computer Architecture, 1987, pp. 2-16.
[4]
D. Dobberpuhl et al., "A 200-MHz 64-b Dual-Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, vol. 27 no. 11, pp. 1555-1567, Nov. 1992
[5]
I. Gee, M. Hill, D. Pnevmatikatos et al., "Cache Performance of the SPEC 92 Benchmark Suite," IEEE MICRO, August 1993 pp 17-27.
[6]
P. Hsu, "Designing the TFP Microprocessor," IEEE MICRO, April 1994, pp 23-33.
[7]
N. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," 17th International Symposium on Computer Architecture, 1990, pp. 364-373.
[8]
N. Jouppi, Cache Write Policies and Performance, WRL Research Report 91/12 DEC Western Research Laboratory
[9]
D. Kroft, "Lockup-free Instruction Fetch/P~femh Cache Organization,'' 8th International Symposium on Computer Architecture, 1981, pp. 81-87.
[10]
N. Kushiyama et al., "A 500-Megabyte/s Data-Rate 4.5M DRAM," IEEE Journal of Solid-State Circuits, vol. 28 no. 4, pp. 490-498, Apr. 1993
[11]
J. Mulder et al., "An area model for on-chip memories and its application," IEEE Journal of Solid-State Circuits, vol. 26, no. 2, 1991, pp. 98-106.
[12]
O.A. Olukotun, T.N. Mudge, and R.B. Brown, "Performance optimization of pipelined primary caches," Proc. of the 19th Ann. Int. Symposium on Computer Architecture, May 1992, pp. 181-190.
[13]
J. Smith and A. Pleszkun, "Implementing precise interrupts in pipelined processors," IEEE Transactions on Computers, (7- 37, no. 5, May, 1988, pp. 562-573.
[14]
T. J. Stanley, M. D. Upton, P. J. Sherhart, T. N. Mudge, R. B. Brown, "A microarchitectural performance evaluation of a 3.2 GB/s microprocessor bus," MICRO-26, The Ann. ACM/IEEE Int. Symposium on Microarchitecture, Austin, TX, Dec. 1993, pp. 31-40.
[15]
J. Thornton, The Design of a Computer, the Control Data 6600, Scott, Foresman and Company, 1970.
[16]
M. Upton, T. Huff, P. Sherhart, P. Barker, R. McVay, T. Stanley, R. Brown, R. Lomax, T. Mudge, and K. Sakallah, "A 160,000 transistor GaAs microprocessor," int. Solid-State Circuits Conf. Digest of Technical Papers, vol. 36, Feb. 1993, pp. 92-93.
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- Resource allocation in a high clock rate microprocessor
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Resource allocation in a high clock rate microprocessor
ASPLOS VI: Proceedings of the sixth international conference on Architectural support for programming languages and operating systemsThis paper discusses the design of a high clock rate (300MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is ...
The MIPS R10000 Superscalar Microprocessor
The Mips R10000 is a dynamic superscalar microprocessor that implements the 64-bit Mips-4 Instruction Set Architecture. It fetches and decodes four instructions per cycle and dynamically issues them to five fully pipelined low-latency execution units. ...
A complexity-effective microprocessor design with decoupled dispatch queues and prefetching
Continuing demands for high degrees of Instruction Level Parallelism (ILP) require large dispatch queues (or centralized reservation stations) in modern superscalar microprocessors. However, such large dispatch queues are inevitably accompanied by high ...
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Publication History
Published: 01 November 1994
Published in SIGOPS Volume 28, Issue 5
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