A Model-Based Approach for Adaptable Middleware Evolution in WSN Platforms
Abstract
:1. Introduction
- We define a model-based porting approach of applications for embedded systems, with focus on WSN applications, required whenever the underlying software layers (e.g., the operating system) are evolved/updated. Through this approach the quality of the resulting application is improved and a low effort is required to get a working version of the application on the new release of the underlying software layer;
- The model-based approach presented in this paper is the generalization of the methodology we initially adopted in our previous work on Agilla [5], which represents a specific use-case for this general method. Indeed, the methodology is now improved and formalized better. Its validity is demonstrated on Agilla as use-case: we define the general model-based approach, and then we cut it into details showing how it led to the results obtained in Reference [5], along with discussions on the intermediate results and on the effects of the model-based porting to the Agilla internals. The result of the porting (Agilla 2) is available to the research community on the Github platform [6].
- We define and measure some relevant metrics (e.g., number of source code lines, storage occupation, code dependency degree) to evaluate the quality of Agilla 2 in comparison with the original version of Agilla. The result of the comparison shows that Agilla 2 has a more flexible software architecture at the cost of a negligible impact on performances.
- In order to provide a further validation, we use the data and the models obtained from the proposed approach to add new energy-aware capabilities to Agilla 2, making it suitable for energy-sensitive applications. We demonstrate that, using the proposed approach, the integration of such relevant new features is possible with a reduced time and complexity.
2. Background & Motivations
- Reliability. WSNs are vulnerable to node failures, hence a robust MW should be able to overcome such failures without interrupting the WSN services. This requires WSN to implement proper recovery strategies.
- Re-configurability. MW shall manage effectively the continuous variations of the number of network nodes and its topology and/or architecture, and the WSN services’ continuity shall be guaranteed during the mote reconfiguration.
- Heterogeneity. An MW shall provide an interface of abstraction towards any kind of nodes participate in the WSN, since different hardware nodes from different technologies could be present in the network.
- Battery life. Energy management is a critical issue for MW for WSNs. Long life of the battery is guaranteed if the MW provides an effective use of the energy-aware communication protocols, Smart HW handling (i.e., by powering off the HW components currently non utilized) and the support for Data Aggregation, to reduce the number of transmissions to the sink node as much as possible.
- QoS. An MW should help QoS management by monitoring performance, network capabilities, throughput, power-consumption, and transmission delays.
- Real-Time requirements. When WSN applications need real-time data, an MW should provide real-time services, despite limited node computational power and HW resources.
- Context-Awareness. An MW should be able to adapt itself to surrounding environment, composed by HW/SW resources, physical characteristics, and constraints.
- Security. WSNs are often deployed into vulnerable environments; hence, in some cases, security is more important than data. An MW shall provide security-centric mechanisms to grant data integrity, authentication, and secure data transfer. Conventional techniques may not be suitable in those cases where performance issues and/or unacceptable power consumption may occur. Often (e.g., Reference [21]), these mechanisms provide acceptable performance if customized to the specific application.
- Virtual Machine-based MWs. A virtual machine approach is used to provide a flexible environment and an interpreter. Examples can be found in Reference [24].
- Application-driven MWs. Here, the final application requirements define how the network, and consequently the MW, should operate, as, e.g., in Milan [25].
3. Model-Based Porting
- Reverse Engineering of the available source code of the target application. An architectural model is obtained that describes its software architecture by using the standard UML description language. This step is not completely automated since there could not be any toolkit available for retrieving full-featured UML diagrams that work directly on the source programming language (e.g., for low-level code or platform-specific languages). Even if the language in which the application is written is not an object-based language, we adopted UML as it is considered a suitable modeling language to describe software architectures; hence, it is adequate for our aim.
- Subsystems identification. The models obtained in (1) are classified by grouping the components based on their high level functionality. We refer to these groups as the subsystems. This step is very important in big applications, since it helps developers reduce the analysis surface and focus on functionality-oriented porting process. The output of this step is a subsystem-level graph.
- Dependency identification. The subsystem-level graph is filtered out to identify the dependency of the target application on the lower-level software layers. This step leads to the identification of those subsystems which are porting-critical. In other words, these are the subsystems that contain components that are tightly coupled with low-level software layers and may have the major impact on the porting procedures. To complete this step, it is necessary to explore the available documentation of the application, of the low-level software layers and of the hardware platform of interests (if any).
- Evolutionary Development Process. This process takes as input the application source code, its architectural model and the list of porting-critical subsystems to produce the architectural model and the source code of the new version of the target application. It consists of multiple iterations of the following four steps, which are interleaved rather than separated, with rapid feedback across activities:
- 4a.
- Model Refinement;
- 4b.
- Subsystem Code Modification;
- 4c.
- Subsystem Stand-alone Testing; and
- 4d.
- Subsystem Integration/Validation.
The process is repeated for every subsystem and ends when the source-code and the architectural models of all considered subsystems are validated and integrated. - General Validation & Evaluation. A general application-wise validation step is conducted. This step ensures that the ported application can be used with all its features in place of the old version. If the validation is successful, the application is evaluated in terms of performance gain/loss, memory occupation, or other relevant metrics. If not, the Evolutionary Development Process is started again to refine the models and update the source code. We define a set of metrics to evaluate the porting results, the improvements, and the software quality, which have been measured and compared.
4. Agilla as the Porting Use Case
4.1. STEP (1): Agilla Reverse-Engineering
4.1.1. UML Notation
4.1.2. Agilla Component Graph
4.1.3. MagicDraw and Agilla UML Modeling
4.2. STEP (2): Agilla’s Subsystem Identification
4.3. STEP (3): Agilla’s Dependency Identification
4.3.1. Agilla vs. TinyOS Dependency Analysis
4.3.2. Porting-Critical Subsystem Analysis
4.3.3. Selected Agilla Critical-Subsystems
- The Hardware-interface subsystem;
- The Agent-management subsystem;
- The Networking subsystem.
4.4. STEP (4): Agilla Evolutionary Development Process
- Model refinement— Focusing on the subsystem components, the information quality and quantity on the UML Component Diagram and Component Graph models are refined and enhanced, by adding information about, e.g., where the components are located, which algorithms and data structure use to achieve their functionalities, etc. The refined subsystem models contain useful information for the developers to progress in the subsequent step of source code modification. Moreover, as said previously, in this step, developers can decide to improve some aspects of the architecture of the subsystems.
- Subsystem code modifications—Using the original model and the refined model as supports, the original source code is analyzed and reworked. At this stage, it is needed to re-analyze carefully the TEPs to find the changes introduced in TinyOS 2.x. The TEPs can be found in every TinyOS distribution in various formats (e.g., txt, pdf, html). With this information from the TEPs, it is possible to rework most of the code of the porting-critical subsystems with few process iterations (in the range from one to four).
- Subsystem stand-alone testing— This step is intended to create a stand-alone testing environment (testbeds) of the correct operation of the subsystems, with no need of compiling the whole application. This step helps developers to quickly check and fix problems from the previous step, potentially reducing the number of issues that may appear after the integration of the reworked subsystem in the application. In addition, by testing only the target subsystem in its testbed, developers can focus on the subsystem functionalities, reducing the quantity of code to review/test and the time required to perform such operations. The creation of the testbeds for Agilla consisted in creating new, small, TinyOS 2.x applications which include only the target subsystem and some basic boot code.
- Subsystem integration & validation—The final step of each iteration in the process consists of the integration of the subsystem into the application. Since the interfaces used and provided by the target subsystem may have been modified, in this phase, developers have to discover and list inter-subsystem problems which can be handled in a subsequent iteration of the process of the same subsystem. An optional activity can be performed during the subsystem integration step: testbeds (created in the previous step) of different subsystems can be enhanced and combined together to create an ”incremental” testbed which includes, piece by piece, the reworked subsystems. This way, it is possible to both create progressively an application-wise testbed and incrementally validate the subsystems.
4.5. STEP (5): General Validation & Evaluation
5. Agilla 2: Quality and Performance Analysis
- a larger compatibility with new WSN mote hardware platforms (e.g., IRIS motes);
- an increased stability, thanks to the reworks of problematic hierarchies, e.g., the removal of the single-point-of-failure of the NetworkInterface component;
- increased mantainability, thanks to the new available models, which can be used both to maintain Agilla 2 code and as support tool to navigate and correct problems in the code.
5.1. Metrics
- Source code lines (nesCLoC) are retrieved by summing the lines of each Agilla component NesC source file (excluding TinyOS components). Such a sum has been obtained using the standard UNIX command wc-l.
- The resulting C source code lines can be retrieved by counting the lines of the app.c file, which is generated by the NesC trans-compiler upon compilation. Although a raw measure of the source code lines has no strong meaning, it is useful to consider the ratio between the two metrics (i.e., Line of Codes Ratio):The resulting value is higher when few lines of NesC code generate a high number of C source code lines. This is a good indication of the expressivity of the NesC source code.
- The storage occupation (both for RAM and ROM storage) is computed directly upon a successful compilation of Agilla/Agilla 2. As in any embedded system, the desired value for those two metrics is as little as possible. In the RAM case, the storage occupation takes into account only data allocated on start. Dynamically allocated data is not included, although it can be neglected since Agilla and, in general, software applications for embedded systems, do not include a dinamic memory allocator and use only pre-allocated data.
- The components fan-in/fan-out metric is the number of relations between provided and used interfaces in the components. The method we applied to evaluate this metric is to use the UML Component Diagram to find the critical components and counting the total number of provided interfaces and the total number of (unique) used interfaces. This metric gives an indication on how many relations have to be broken in order to refactor the critical components of Agilla.
- A similar metric is the dependency of Agilla and its underlying TinyOS version. We define this metric as the number of relations between the Agilla components and the TinyOS components. We retrieve such number by using the Component Graph. A loose dependency is obviously preferable.
- Finally, we take into account the quality of the documentation in the Agilla/Agilla 2 source code.We use two metrics: the comment-ratio and the artifact ratio, definitions of which can be found in Reference [4]. Apart from the source code, we also consider (for Agilla 2) the documentation created during the porting operations.
5.2. Results
6. Agilla Improvements
6.1. Energy Consumption and WSN Node Lifetime Considerations
6.2. New Instruction: battery
7. Conclusions
Author Contributions
Funding
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
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CPU/MCU Architecture | Clock Freq. | Instructions Per Second | Flash/ROM | RAM |
---|---|---|---|---|
Harvard, 8- or 16-bit | 16–25 MHz | 8–16 MIPS | 32–128 KiB | 8–10 KiB |
Agilla | actorNet | MAPS | AFME | WSageNt | |
---|---|---|---|---|---|
Migration | Y | Y | Y | Y | Y |
Multitasking | Y | Y | Y | Y | N |
Communication Model | tuple space | messages | messages | messages | messages |
Programming Language | proprietary ISA | Scheme-like | Java | Java | ALLL |
Agent Model | Assembler-like | Functional | Finite State | BDI | Assembler-like |
Machine | |||||
Intentional Agents | N | N | N | Y | N |
Sensor Platforms | Mica2, MICAz, TelosB | Mica2 | Sun SPOT | Sun SPOT | MICAz, IRIS |
Model-based porting | ||
---|---|---|
Step | Artifact | Description |
1 | Component Graph | The GraphViz-like diagram obtained by performing a quick (e.g., automated) analysis of the target application components. |
First UML Component Diagram | The standard UML Component Diagram obtained by refining the Component Diagram with the application architectural information retrieved by the source code. | |
2 | Subsystem-level Diagram | A higher-level model that highlights the subsystems of the target application. |
3 | Target-only UML Component Diagram | A refined UML Component Diagram, which includes information on the dependency of the target application on the low-level software layers (e.g., operating system). |
Target-only Component Graph | A refined Component Graph divided in two sections: target-only components and low-level software components. | |
List of porting-critical subsystems | The list of the application subsystems which are highly coupled with the operating system and require a rework. | |
4 | Ported application source code | The ported version of the target application, working as intended. |
Ported-MW models | The ported-MW models resulting from the refinement of the original MW models (UML Component Diagram and Component Graph). |
Metrics List | |
---|---|
Metric Name | Meaning |
Agilla ROM footprint (ROM) | The space occupation (in bytes) of the binary image of Agilla when programmed into the node |
Agilla RAM footprint (RAM) | The estimated runtime space occupation (in bytes) of the data allocated by Agilla when programmed into the node |
nesC Lines of Code (nesCLoC) | The total number of lines of NesC code in Agilla components, (without the TinyOS components) |
Resulting C Lines of Code (CLoC) | The total number of lines of C code generated by the NesC trans-compiler from Agilla (including TinyOS components) |
Critical Components Fan-in/Fan-out (CritFanInOut) | The number of connections from and to the components inside the considered critical-subsystems |
TinyOS dependency degree (Dependency) | The number of connections between pure Agilla components and the underlying TinyOS components |
Quality of Documentation (Doc) | The quality and the quantity of documentation available both internal and external to the source code |
Metric Name | TinyOS 1.x + Agilla | TinyOS 2.x + Agilla 2 |
---|---|---|
ROM (bytes) | 54,736 | 55,944 (~+2.2%) |
RAM (bytes) | 3191 | 3640 (~+14%) |
nesCLoC (number) | 19,776 | 21563 (~+9%) |
CLoC (number) | 40,285 | 61,402 (~+52%) |
LoCRatio (ratio) | 2.037 | 2.84 (~+39%) |
CritFanInOut (relations) | 596 | 521 (~−13%) |
Dependency (relations) | 225 | 182 (~−20%) |
Doc (types) | Source-code comments | Comments, TEP, Graphs & Diagrams |
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Tiberti, W.; Cassioli, D.; Di Marco, A.; Pomante, L.; Santic, M. A Model-Based Approach for Adaptable Middleware Evolution in WSN Platforms. J. Sens. Actuator Netw. 2021, 10, 20. https://doi.org/10.3390/jsan10010020
Tiberti W, Cassioli D, Di Marco A, Pomante L, Santic M. A Model-Based Approach for Adaptable Middleware Evolution in WSN Platforms. Journal of Sensor and Actuator Networks. 2021; 10(1):20. https://doi.org/10.3390/jsan10010020
Chicago/Turabian StyleTiberti, Walter, Dajana Cassioli, Antinisca Di Marco, Luigi Pomante, and Marco Santic. 2021. "A Model-Based Approach for Adaptable Middleware Evolution in WSN Platforms" Journal of Sensor and Actuator Networks 10, no. 1: 20. https://doi.org/10.3390/jsan10010020