Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking
Abstract
:1. Introduction
2. Literature Review/Related Works
2.1. DLDO Voltage Regulators
2.2. Countermeasures against Side-Channel Attacks
2.3. Hardware Masking
3. Theoretical Modelling
4. Methodology
5. Verification and Validation of Inputs
6. Experimental Results
6.1. Effect of the PDN Parasitic Impedance with an Ideal Voltage Regulator
6.2. Effect of the PDN Parasitic Impedance with a DLDO Voltage Regulator
6.2.1. DLDO with 64 PMOS (Strong DLDO)
6.2.2. DLDO with 32 PMOS (Normal DLDO)
6.2.3. DLDO with 16 PMOS (Weak DLDO)
6.3. Effect of PDN Parasitic Impedance with Two DLDOs
6.4. Effect of PDN Parasitic Impedance with a Shared Two-Phase DLDO
6.5. Effect of the DLDO Voltage Regulator Placement in the Grid Network
7. Conclusions and Future Recommendations
Author Contributions
Funding
Conflicts of Interest
References
- Mayhew, M.; Muresan, R. On-chip nanoscale capacitor decoupling architectures for hardware security. IEEE Trans. Emerg. Top. Comput. 2014, 2, 4–15. [Google Scholar] [CrossRef]
- Yu, W.; Köse, S. Time-delayed converter-reshuffling: An efficient and secure power delivery architecture. IEEE Embed. Syst. Lett. 2015, 7, 73–76. [Google Scholar] [CrossRef]
- Nawaz, K.; Kamel, D.; Standaert, F.X.; Flandre, D. Scaling trends for dual-rail logic styles against side-channel attacks: A case-study. In International Workshop on Constructive Side-Channel Analysis and Secure Design; Springer: Berlin/Heidelberg, Germany, 2017; pp. 19–33. [Google Scholar]
- Duc, A.; Faust, S.; Standaert, F.X. Making masking security proofs concrete (or how to evaluate the security of any leaking device), extended version. J. Cryptol. 2019, 32, 1263–1297. [Google Scholar] [CrossRef]
- De Cnudde, T.; Ender, M.; Moradi, A. Hardware masking, revisited. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018, 123–148. [Google Scholar] [CrossRef]
- Balasch, J.; Gierlichs, B.; Grosso, V.; Reparaz, O.; Standaert, F.X. On the cost of lazy engineering for masked software implementations. In Proceedings of the International Conference on Smart Card Research and Advanced Applications, Paris, France, 5–7 November 2014; pp. 64–81. [Google Scholar]
- Šijačić, D.; Balasch, J.; Verbauwhede, I. Sweeping for leakage in masked circuit layouts. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Grenoble, France, 9–13 March 2020; pp. 915–920. [Google Scholar]
- Dai, H.; Köse, S. On the vulnerability of hardware masking in practical implementations. In Proceedings of the 2021 on Great Lakes Symposium on VLSI, Virtual Event, 22–25 June 2021; pp. 77–82. [Google Scholar]
- Dyrkolbotn, G.O.; Wold, K.; Snekkenes, E. Security implications of crosstalk in switching cmos gates. In Proceedings of the International Conference on Information Security, Shanghai, China, 20–24 October 2010; pp. 269–275. [Google Scholar]
- Giechaskiel, I.; Eguro, K. Information leakage between FPGA long wires. arXiv 2016, arXiv:1611. [Google Scholar]
- Zussa, L.; Exurville, I.; Dutertre, J.M.; Rigaud, J.B.; Robisson, B.; Tria, A.; Clediere, J. Evidence of an information leakage between logically independent blocks. In Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, Amsterdam, The Netherlands, 19–21 January 2015; pp. 25–30. [Google Scholar]
- Schellenberg, F.; Gnad, D.R.; Moradi, A.; Tahoori, M.B. An inside job: Remote power analysis attacks on FPGAs. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Dresden, Germany, 19–23 March 2018; pp. 1111–1116. [Google Scholar]
- De Cnudde, T.; Bilgin, B.; Gierlichs, B.; Nikov, V.; Nikova, S.; Rijmen, V. Does coupling affect the security of masked implementations? In Proceedings of the International Workshop on Constructive Side-Channel Analysis and Secure Design, Lugano, Switzerland, 25–27 October 2017; pp. 1–18. [Google Scholar]
- Sijacic, D.; Balasch, J.; Yang, B.; Ghosh, S.; Verbauwhede, I. Towards efficient and automated side channel evaluations at design time. Kalpa Publ. Comput. 2018, 7, 16–31. [Google Scholar]
- Monta, K.; Sonoda, H.; Okidono, T.; Araga, Y.; Watanabe, N.; Shimamoto, H.; Kikuchi, K.; Miura, N.; Miki, T.; Nagata, M. 3D CMOS chip stacking for security ICs featuring backside buried metal power delivery networks with distributed capacitance. IEEE Trans. Electron Devices 2021, 68, 2077–2082. [Google Scholar] [CrossRef]
- Dey, S.; Park, J.; Pundir, N.; Saha, D.; Shuvo, A.M.; Mehta, D.; Asadi, N.; Rahman, F.; Farahmandi, F.; Tehranipoor, M. Secure Physical Design. Cryptology ePrint Archive, Paper 2022/891, 202. Available online: https://eprint.iacr.org/2022/891 (accessed on 16 August 2022).
- Vaisband, I.P.; Jakushokas, R.; Popovich, M.; Mezhiba, A.V.; Köse, S.; Friedman, E.G. On-Chip Power Delivery and Management; Springer: Berlin/Heidelberg, Germany, 2016. [Google Scholar]
- Addisu, M.; Salau, A.O.; Takele, H. Fuzzy logic based optimal placement of voltage regulators and capacitors for distribution systems efficiency improvement. Heliyon 2021, 7, e07848. [Google Scholar] [CrossRef]
- Salau, A.; Nweke, J.; Ogbuefi, U. Effective implementation of mitigation measures against voltage collapse in distribution power systems. Prz. Elektrotech. 2021, 65–68. [Google Scholar] [CrossRef]
- Kar, M.; Singh, A.; Mathew, S.; Rajan, A.; De, V.; Mukhopadhyay, S. Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines. In Proceedings of the 2016 International Symposium on Low Power Electronics and Design, San Francisco, CA, USA, 8–10 August 2016; pp. 130–135. [Google Scholar]
- Yu, W.; Köse, S. Exploiting voltage regulators to enhance various power attack countermeasures. IEEE Trans. Emerg. Top. Comput. 2016, 6, 244–257. [Google Scholar] [CrossRef]
- Yu, W.; Uzun, O.A.; Köse, S. Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks. In Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, 8–12 June 2015; pp. 1–6. [Google Scholar]
- Uzun, O.A.; Köse, S. Converter-gating: A power efficient and secure on-chip power delivery system. IEEE J. Emerg. Sel. Top. Circuits Syst. 2014, 4, 169–179. [Google Scholar] [CrossRef]
- Wang, L.; Khatamifard, S.K.; Karpuzcu, U.R.; Köse, S. Exploiting algorithmic noise tolerance for scalable on-chip voltage regulation. IEEE Trans. Very Large Scale Integr. Syst. 2018, 27, 229–242. [Google Scholar] [CrossRef]
- Seçkiner, S.; Wang, L.; Köse, S. An NBTI-aware digital low-dropout regulator with adaptive gain scaling control. In Proceedings of the IFIP/IEEE 27th International Conference on Very Large Scale Integration, Cuzco, Peru, 6–9 October 2019; pp. 191–196. [Google Scholar]
- Wang, L.; Khatamifard, S.K.; Karpuzcu, U.R.; Köse, S. Mitigation of NBTI induced performance degradation in on-chip digital LDOs. In Proceedings of the Design, Automation and Test in Europe, San Jose, CA, USA, 19–23 March 2018; pp. 803–808. [Google Scholar]
- Okuma, Y.; Ishida, K.; Ryu, Y.; Zhang, X.; Chen, P.H.; Watanabe, K.; Takamiya, M.; Sakurai, T. 0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS. In Proceedings of the IEEE Custom Integrated Circuits Conference 2010, San Jose, CA, USA, 19–22 September 2010; pp. 1–4. [Google Scholar]
- Shamir, A. Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies; Springer: Berlin/Heidelberg, Germany, 2000; pp. 71–77. [Google Scholar]
- Kim, S.K. Smart Cards Having Protection Circuits Therein that Inhibit Power Analysis Attacks and Methods of Operating Same. U.S. Patent 7,620,823, 17 November 2009. [Google Scholar]
- Hubert, G.T. Current Source for Cryptographic Processor. U.S. Patent 7,571,492, 4 August 2009. [Google Scholar]
- Tokunaga, C.; Blaauw, D. Securing encryption systems with a switched capacitor current equalizer. IEEE J. Solid State Circuits 2009, 45, 23–31. [Google Scholar] [CrossRef]
- Ratanpal, G.B.; Williams, R.D.; Blalock, T.N. An on-chip signal suppression countermeasure to power analysis attacks. IEEE Trans. Dependable Secur. Comput. 2004, 1, 179–189. [Google Scholar] [CrossRef]
- Muresan, R.; Gregori, S. Protection circuit against differential power analysis attacks for smart cards. IEEE Trans. Comput. 2008, 57, 1540–1549. [Google Scholar] [CrossRef]
- Tiri, K.; Akmal, M.; Verbauwhede, I. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. In Proceedings of the IEEE 28th European Solid-State Circuits Conference, Florence, Italy, 24–26 September 2002; pp. 403–406. [Google Scholar]
- Hwang, D.D.; Tiri, K.; Hodjat, A.; Lai, B.C.; Yang, S.; Schaumont, P.; Verbauwhede, I. AES-Based Security Coprocessor IC in 0.18-muhboxm CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. IEEE J. Solid State Circuits 2006, 41, 781–792. [Google Scholar] [CrossRef]
- Sokolov, D.; Murphy, J.; Bystrov, A.; Yakovlev, A. Design and analysis of dual-rail circuits for security applications. IEEE Trans. Comput. 2005, 54, 449–460. [Google Scholar] [CrossRef]
- Toprak, Z.; Leblebici, Y. Low-power current mode logic for improved DPA-resistance in embedded systems. In Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, 23–26 May 2005; pp. 1059–1062. [Google Scholar]
- Sana, P.K.; Satyam, M. An energy efficient secure logic to provide resistance against differential power analysis attacks. In Proceedings of the IEEE International Symposium on Electronic System Design, Bhubaneswar, India, 20–22 December 2010; pp. 61–65. [Google Scholar]
- Ambrose, J.A.; Ragel, R.G.; Parameswaran, S.; Ignjatovic, A. Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks. IET Comput. Digit. Tech. 2011, 5, 1–15. [Google Scholar] [CrossRef]
- Seyyedi, S.A.; Kamal, M.; Noori, H.; Safari, S. Securing embedded processors against power analysis based side channel attacks using reconfigurable architecture. In Proceedings of the IEEE 9th International Conference on Embedded and Ubiquitous Computing, Melbourne, Australia, 24–26 October 2011; pp. 255–260. [Google Scholar]
- Shu, D.B.; Chow, L.W.; Clark, W., Jr. Cryptographic Architecture with Instruction Masking and other Techniques for Thwarting Differential Power Analysis. U.S. Patent 8,095,993, 10 January 2012. [Google Scholar]
- Shamir, A. How to share a secret. Commun. ACM 1979, 22, 612–613. [Google Scholar] [CrossRef]
- Chari, S.; Jutla, C.S.; Rao, J.R.; Rohatgi, P. Towards sound approaches to counteract power-analysis attacks. In Proceedings of the Annual International Cryptology Conference, Santa Barbara, CA, USA, 15–19 August 1999; pp. 398–412. [Google Scholar]
- Corbett, J.D. The Xilinx Isolation Design Flow for Fault-Tolerant Systems; Xilinx White Paper WP412. 2013. Available online: https://docs.xilinx.com/v/u/en-US/wp412_IDF_for_Fault_Tolerant_Sys (accessed on 16 August 2022).
- Gu, J.; Harjani, R.; Kim, C. Distributed active decoupling capacitors for on-chip supply noise cancellation in digital VLSI circuits. In 2006 Symposium on VLSI Circuits; Digest of Technical Papers; IEEE: Piscataway, NJ, USA, 2006; pp. 216–217. [Google Scholar]
- Dufort, B.; Roberts, G.W. On-chip analog signal generation for mixed-signal built-in self-test. IEEE J. Solid State Circuits 1999, 34, 318–330. [Google Scholar] [CrossRef]
- Sakurai, T.; Newton, A. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J. Solid State Circuits 1990, 25, 584–594. [Google Scholar] [CrossRef]
- Zhao, W.; Cao, Y. Predictive technology model for nano-CMOS design exploration. ACM J. Emerg. Technol. Comput. Syst. (JETC) 2007, 3, 1-es. [Google Scholar] [CrossRef]
- Kose, S.; Salman, E.; Friedman, E.G. Shielding methodologies in the presence of power/ground noise. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2010, 19, 1458–1468. [Google Scholar] [CrossRef]
- Gilbert Goodwill, B.J.; Jaffe, J.; Rohatgi, P. A testing methodology for side-channel resistance validation. In Proceedings of the NIST Non-Invasive Attack Testing Workshop, Nara, Japan, 25–27 September 2011; Volume 7, pp. 115–136. [Google Scholar]
- O’Flynn, C.; Chen, Z.D. ChipWhisperer: An Open-Source Platform for Hardware Embedded Security Research. In Constructive Side-Channel Analysis and Secure Design; Prouff, E., Ed.; Springer International Publishing: Cham, Switzerland, 2014; pp. 243–260. [Google Scholar]
- Kocher, P.; Jaffe, J.; Jun, B. Differential power analysis. In Annual International Cryptology Conference; Springer: Berlin/Heidelberg, Germany, 1999; pp. 388–397. [Google Scholar]
- Standaert, F.X. How (not) to use welch’s t-test in side-channel security evaluations. In Proceedings of the International Conference on Smart Card Research and Advanced Applications, Monpellier, France, 12–14 November 2018; pp. 65–79. [Google Scholar]
Setup | t-Test | ||
---|---|---|---|
Ideal voltage regulator | 8 k | 2 k | 1.74 |
Strong DLDO voltage regulator | 8 k | 2 k | 1.11 |
Two DLDO sharing same VDD | 500, 1 k, 2 k, 4 k, 8 k | 2 k | 0.36 |
Two-phase DLDO with 180 degree phase | 500, 1 k, 2 k, 4 k, 8 k | 2 k | 0.43 |
ASIC/FPGA | Implementation | Minimum Number of Traces for the Leakage (Higher Is Better) | |
---|---|---|---|
[7] | ASIC | PDN | 1k |
[15] | ASIC | PDN | 18k |
[16] | ASIC | X | X |
This work | ASIC | PDN | 80k |
DLDO Voltage Regulator Position in Grid | Correlation between Two Shares | |
---|---|---|
| 5.68 | 0.71 |
| 4.25 | 0.53 |
| 3.94 | 0.49 |
| 4.09 | 0.51 |
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |
© 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
Share and Cite
Seçkiner, S.; Köse, S. Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking. Sensors 2022, 22, 7028. https://doi.org/10.3390/s22187028
Seçkiner S, Köse S. Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking. Sensors. 2022; 22(18):7028. https://doi.org/10.3390/s22187028
Chicago/Turabian StyleSeçkiner, Soner, and Selçuk Köse. 2022. "Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking" Sensors 22, no. 18: 7028. https://doi.org/10.3390/s22187028