Bounded Model Checking for Metric Temporal Logic Properties of Timed Automata with Digital Clocks †
Abstract
:1. Introduction
- Defining the translation of the existential model-checking problem for MTL to the existential model-checking problem for linear temporal logic with additional propositional variables (this logic is denoted by );
- Clarification of the steps of the new method;
- Proving the correctness of the above translation;
- Defining bounded semantics for ;
- Defining the BMC algorithm;
- Implementing the new method;
- A detailed experimental evaluation of the old and the new methods on two earlier presented benchmarks: a timed generic pipeline paradigm (TGPP) and a timed train controller system (TTCS),
- Modeling a dining philosophers problem with time as the timed dining philosophers problem (TDPP);
- A detailed experimental evaluation of the old and the new methods on TDPP.
Related Work
- The time difference translation for strict semantics, where new propositional variables encode time differences between states (the time difference translation is similar to the method presented in [1]).
- The gap translation for the strict semantics uses a new propositional variable, called gap, to encode the jumps between states. The gap is intended to be true in LTL states corresponding to unmapped time points in MTL models. The main idea for their translation is to map each timed state sequence into a state sequence. Both LTL translations are exponential in the size of the MTL input formula due to the binary encoding of the numbers in the intervals.
2. Discrete Timed Automata and MTL
2.1. Discrete Timed Automata
- is a finite set of actions,
- is a finite set of locations,
- is the initial location,
- is a finite set of clocks,
- is a transition relation,
- is a state invariant function,
- is a set of atomic propositions, and
- is a valuation function assigning to each location a set of atomic propositions true in this location.
2.2. Product of a Network of Discrete Timed Automata
- ,
- ,
- ,
- ,
- ,
- ,
2.3. Concrete Model
- is the set of the concrete states.
- is the initial state.
- A valuation function is defined as for each state is a transition relation on Q defined by action and time transitions as follows.
- For and :
- 1.
- Action transition: if there is a transition such that and and ,
- 2.
- Time transition: iff and .
2.4. MTL Logic
2.4.1. Syntax
2.4.2. Semantics
- ,
- ,
- ,
- ,
- ,
- ,
- ,
3. Bounded Model Checking
3.1. The Translation
3.1.1. Abstract Model
- is the set of abstract states;
- is the initial state;
- is a valuation function such that for all , if and only if ;
- , where is a transition relation defined by the time and action transitions.
- −
- The time transition is defined as if and only if , and .
- −
- The action transition is defined as follows: for any , if and only if there exists a transition such that , and .
3.1.2. MTL Semantics in the Abstract Model
- ,
- ,
- iff ,
- iff ,
- and ,
- or ,
- ,
- iff implies .
3.1.3. Logic
- ,
- ,
- iff ,
- iff ,
- iff ,
- iff ,
- iff and ,
- iff or ,
- iff and ,
- iff .
3.1.4. The Translation from MTL to
- ,
- ,
- ,
- ,
- ,
- ,
- , and
- = .
4. Proof of the Theorem 2
- . Because , it is obvious that . Therefore, .
- , where . Thus, . Therefore, .
- . From the definition of the satisfiability relation (Definition 7) it follows that and . By inductive hypothesis, we obtain and . Therefore, , and hence .
- . From the definition of the satisfiability relation (Definition 7) it follows that or . By inductive hypothesis, we obtain that or . Therefore, , and hence .
- . Assume that . From the definition of the satisfiability relation (Definition 7), it follows that and and , for some . By inductive hypothesis, we obtain and , for some and , for all . Therefore, , for some , and , for all . Therefore, we conclude that .
- . Assume that . From the definition of the satisfiability relation (Definition 7), it follows that implies , which means that , for all . By inductive hypothesis, we obtain , for all . Hence, , for all . From the semantics of , it follows that . So, we can conclude that .
- . Since , it follows that . Therefore, .
- , where . Then . Therefore, .
- . Thus, . From the definition of the satisfiability relation (Definiton 8) it follows that and . By inductive hypothesis, we obtain and . Hence, and thus .
- . Then . From the definition of the satisfiability relation (Definition 8) it follows that or . By inductive hypothesis, we obtain or . Hence, , and thus .
- . Assume that . From the definition of the translation, it follows that . From the definition of the satisfiability relation 8, it follows that and , for some . Therefore, and , for some . From the inductive hypothesis, we obtain and , thus and . Thus, we conclude that .
- . Assume that . From the definition of the translation, it follows that . From the definition of the satisfiability relation or , which means or , for all . By inductive hypothesis, we obtain or , which is equivalent to . Therefore, .
4.1. Bounded Semantics
4.2. Translation to SAT
5. Experimental Results
5.1. Timed Dining Philosophers
- . At least one philosopher will eventually eat and put down both forks.
- . Eventually, every second philosopher (starting with the first one) eats.
- . Every second philosopher (starting with the first one) always eats in the end.
5.2. Timed Generic Pipeline Paradigm
- . It states that always either the producer has sent the data or the consumer has received the data.
- . It states that eventually in time less then , it is always the case that the producer is ready to send the data or the consumer has received the data.
- . It states that the Consumer infinitely often eventually receives the data in time less than units.
5.3. Timed Train Controller System
- . It expresses that the system violates the mutual exclusion property.
- . It expresses that the first train can infinitely often and from any state enter the tunnel in time less than .
- . It expresses that the first train is infinitely often in the tunnel and outside the tunnel in time less than .
6. Statistics
7. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
Abbreviations
MTL | Metric Temporal Logic |
HLTL | Hard Reset LTL |
LTL | Linear Temporal Logic |
TA | Timed Automata |
DTA | Discrete Timed Automaton |
BMC | Bounded Model Checking |
Linear Temporal Logic with Additional Propositional Variables | |
TGPP | Timed Generic Pipeline Paradigm |
TTCS | Timed Train Controller System |
TDPP | Timed Dining Philosophers Problem |
Appendix A. Improvements and Extensions Compared to the Workshop Paper
- We improved it and proved the main theorem. The workshop paper presented only the idea of the method;
- We improved definitions;
- We changed the semantics: the weakly monotonic semantics seems to be more natural in the case of discrete time. In [1], we used strongly monotonic semantics;
- We redefined the concrete model. The process of creating the concrete model presented in [26] was unnecessarily complicated;
- We redefined the semantics of MTL;
- We showed the translation to SAT for the formula on the path starting at point m at the depth d;
- We extended the experimental section by adding the timed dining philosophers problem (to the best of our knowledge, we modeled TDP for the first time as a network of discrete timed automata—we could find only the modeling using timed Petri nets in the literature).
Appendix B. Code Reproducibility
Appendix B.1. Preliminary
Appendix B.2. Running Experiments
Appendix B.3. Example-TTCS
References
- Zbrzezny, A.M.; Zbrzezny, A. Simple Bounded MTL Model Checking for Discrete Timed Automata (Extended abstract). In Proceedings of the 23th International Workshop on Concurrency, Specification and Programming (CS&P 2016), Rostock, Germany, 28–30 September 2016; Volume 1698, pp. 37–48. [Google Scholar]
- Bourke, T.; Sowmya, A. Analyzing an Embedded Sensor with Timed Automata in Uppaal. ACM Trans. Embed. Comput. Syst. (TECS) 2013, 13, 44-1–44-26. [Google Scholar] [CrossRef] [Green Version]
- Chen, G.; Jiang, T.; Wang, M.; Tang, X.; Ji, W. Design and model checking of timed automata oriented architecture for Internet of thing. Int. J. Distrib. Sens. Netw. 2020, 16, 1550147720911008. [Google Scholar] [CrossRef]
- Iversen, T.K.; Kristoffersen, K.J.; Larsen, K.G.; Laursen, M.; Madsen, R.G.; Mortensen, S.K.; Pettersson, P.; Thomasen, C.B. Model-checking real-time control programs: Verifying Lego(R) MindstormsTM systems using UPPAAL. In Proceedings of the 12th Euromicro Conference on Real-Time Systems (ECRTS 2000), Stockholm, Sweden, 19–21 June 2000; IEEE Computer Society: Washington, DC, USA, 2000; pp. 147–155. [Google Scholar] [CrossRef]
- Lahtinen, J. Model Checking Timed Safety Instrumented Systems; Research Report TKK-ICS-R3; Helsinki University of Technology, Department of Information and Computer Science: Espoo, Finland, 2008. [Google Scholar]
- Hammal, Y.; Monnet, Q.; Mokdad, L.; Ben-Othman, J.; Abdelli, A. Timed automata based modeling and verification of denial of service attacks in wireless sensor networks. Stud. Inform. Universalis 2014, 12, 1–46. [Google Scholar]
- Mouradian, A.; Augé-Blum, I. Modeling Local Broadcast Behavior of Wireless Sensor Networks with Timed Automata for Model Checking of WCTT. In Proceedings of the WCTT’12, San Juan, Puerto Rico, 4 December 2012; pp. 23–30. [Google Scholar]
- Alur, R.; Dill, D. A Theory of Timed Automata. Theor. Comput. Sci. 1994, 126, 183–235. [Google Scholar] [CrossRef] [Green Version]
- Bozga, M.; Hou, J.; Maler, O.; Yovine, S. Verification of Asynchronous Circuits using Timed Automata. Electr. Notes Theor. Comput. Sci. 2002, 65, 47–59. [Google Scholar] [CrossRef] [Green Version]
- Dierks, H. PLC-automata: A new class of implementable real-time automata. Theor. Comput. Sci. 2001, 253, 61–93. [Google Scholar] [CrossRef] [Green Version]
- Clarke, E.M.; Emerson, E.A. Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic. In Proceedings of the Logics of Programs, Yorktown Heights, NY, USA, 4–6 May 1981; Springer: Berlin/Heidelberg, Germany, 1981; Volume 131, pp. 52–71. [Google Scholar]
- Emerson, E.A.; Mok, A.K.; Sistla, A.P.; Srinivasan, J. Quantitative Temporal Reasoning. Real-Time Syst. 1992, 4, 331–352. [Google Scholar] [CrossRef]
- Pnueli, A. The Temporal Logic of Programs. In Proceedings of the 18th Annual Symposium on Foundations of Computer Science, Providence, RI, USA, 20–23 October 1977; pp. 46–57. [Google Scholar]
- Koymans, R. Specifying Real-Time Properties with Metric Temporal Logic. Real-Time Syst. 1990, 2, 255–299. [Google Scholar] [CrossRef]
- Bouyer, P. Model-checking Timed Temporal Logics. Electr. Notes Theor. Comput. Sci. 2009, 231, 323–341. [Google Scholar] [CrossRef] [Green Version]
- Furia, C.A.; Spoletini, P. Tomorrow and All our Yesterdays: MTL Satisfiability over the Integers. In Proceedings of the ICTAC, Istanbul, Turkey, 1–3 September 2008; Springer: Berlin/Heidelberg, Germany, 2008; Volume 5160, pp. 126–140. [Google Scholar]
- Ho, H.; Ouaknine, J.; Worrell, J. On the Expressiveness and Monitoring of Metric Temporal Logic. Logical Methods in Comp. Sci. 2019, 15. [Google Scholar] [CrossRef]
- Pradella, M.; Morzenti, A.; Pietro, P.S. Bounded satisfiability checking of metric temporal logic specifications. ACM Trans. Softw. Eng. Methodol. 2013, 22, 20:1–20:54. [Google Scholar] [CrossRef]
- Henzinger, T.; Manna, Z.; Pnueli, A. What good are digital clocks? In Proceedings of the ICALP 92: Automata, Languages, and Programming, Wien, Austria, 13–17 July 1992; Kuich, W., Ed.; Springer: Berlin/Heidelberg, Germany, 1992; pp. 545–558. [Google Scholar]
- Biere, A.; Cimatti, A.; Clarke, E.; Zhu, Y. Symbolic Model Checking without BDDs. In Proceedings of the TACAS’99, Amsterdam, The Netherlands, 22–28 March 1999; Springer: Berlin/Heidelberg, Germany, 1999; Volume 1579, pp. 193–207. [Google Scholar]
- Biere, A.; Cimatti, A.; Clarke, E.M.; Strichman, O.; Zhu, Y. Bounded Model Checking. Adv. Comput. 2003, 58, 117–148. [Google Scholar]
- Penczek, W.; Woźna, B.; Zbrzezny, A. Bounded Model Checking for the Universal Fragment of CTL. Fundam. Inform. 2002, 51, 135–156. [Google Scholar]
- Alur, R.; Henzinger, T.A. Real-time Logics: Complexity and Expressiveness. In Proceedings of the LICS ’90, Philadelphia, PA, USA, 4–7 June 1990; pp. 390–401. [Google Scholar]
- Alur, R.; Feder, T.; Henzinger, T.A. The Benefits of Relaxing Punctuality. J. ACM 1996, 43, 116–146. [Google Scholar] [CrossRef] [Green Version]
- Wilke, T. Specifying Timed State Sequences in Powerful Decidable Logics and Timed Automata. In Proceedings of the Formal Techniques in Real-Time and Fault-Tolerant Systems, Lübeck, Germany, 19–23 September 1994; pp. 694–715. [Google Scholar]
- Woźna-Szcześniak, B.; Zbrzezny, A. Checking MTL Properties of Discrete Timed Automata via Bounded Model Checking. Fundam. Inform. 2014, 135, 553–568. [Google Scholar] [CrossRef]
- Alur, R.; Henzinger, T.A. Logics and Models of Real Time: A Survey. In Proceedings of the Real-Time: Theory in Practice, REX Workshop, Mook, The Netherlands, 3–7 June 1991; de Bakker, J.W., Huizing, C., de Roever, W.P., Rozenberg, G., Eds.; Springer: Berlin/Heidelberg, Germany, 1991; Volume 600, pp. 74–106. [Google Scholar] [CrossRef] [Green Version]
- Bozga, M.; Maler, O.; Tripakis, S. Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics. In Proceedings of the Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME ’99, Bad Herrenalb, Germany, 27–29 September 1999; Pierre, L., Kropf, T., Eds.; Springer: Berlin/Heidelberg, Germany, 1999; Volume 1703, pp. 125–141. [Google Scholar] [CrossRef] [Green Version]
- Ruf, J.; Kropf, T. Symbolic Verification and Analysis of Discrete Timed Systems. Form. Methods Syst. Des. 2003, 23, 67–108. [Google Scholar] [CrossRef]
- Cimatti, A.; Griggio, A.; Magnago, E.; Roveri, M.; Tonetta, S. Extending nuXmv with timed transition systems and timed temporal properties. In Proceedings of the International Conference on Computer Aided Verification, New York, NY, USA, 15–18 July 2019; Springer: Cham, Switzerland, 2019; pp. 376–386. [Google Scholar]
- Gao, Y.; Abate, A.; Jiang, F.J.; Giacobbe, M.; Xie, L.; Johansson, K.H. Temporal logic trees for model checking and control synthesis of uncertain discrete-time systems. IEEE Trans. Autom. Control 2021, 67, 5071–5086. [Google Scholar] [CrossRef]
- Laroussinie, F.; Markey, N.; Schnoebelen, P. Efficient timed model checking for discrete-time systems. Theor. Comput. Sci. 2006, 353, 249–271. [Google Scholar] [CrossRef]
- Krystosik, A. Embedded Systems Modeling Language. In Proceedings of the 2006 International Conference on Dependability of Computer Systems (DepCoS-RELCOMEX 2006), Szklarska Poreba, Poland, 24–28 May 2006; IEEE Computer Society: Washington, DC, USA, 2006; pp. 27–34. [Google Scholar] [CrossRef]
- Bruneel, H.; Kim, B.G. Discrete-Time Models for Communication Systems Including ATM; Springer Science & Business Media: New York, NY, USA, 2012; Volume 205. [Google Scholar]
- Belta, C.; Yordanov, B.; Gol, E.A. Formal Methods for Discrete-Time Dynamical Systems; Springer: Cham, Switzerland, 2017; Volume 15. [Google Scholar]
- Allen, L.; Jones, M.; Martin, C. A discrete-time model with vaccination for a measles epidemic. Math. Biosci. 1991, 105, 111–131. [Google Scholar] [CrossRef]
- Li, S.; Lu, Y.; Garrido, J. A review of discrete-time risk models. RACSAM-Rev. De La Real Acad. De Cienc. Exactas Fis. Y Nat. Ser. A Mat. 2009, 103, 321–337. [Google Scholar] [CrossRef]
- Oli, M.K.; Venkataraman, M.; Klein, P.A.; Wendland, L.D.; Brown, M.B. Population dynamics of infectious diseases: A discrete time model. Ecol. Model. 2006, 198, 183–194. [Google Scholar] [CrossRef]
- Quaas, K. MTL-Model Checking of One-Clock Parametric Timed Automata is Undecidable. In Proceedings of the 1st International Workshop on Synthesis of Continuous Parameters, SynCoP 2014, Grenoble, France, 6 April 2014; André, É., Frehse, G., Eds.; Open Publishing Association: Waterloo, Australia, 2014; Volume 145, pp. 5–17. [Google Scholar] [CrossRef] [Green Version]
- Bae, K.; Lee, J. Bounded model checking of signal temporal logic properties using syntactic separation. Proc. ACM Program. Lang. 2019, 3, 1–30. [Google Scholar] [CrossRef] [Green Version]
- Li, J.; Vardi, M.Y.; Rozier, K.Y. Satisfiability checking for mission-time LTL. In Proceedings of the International Conference on Computer Aided Verification, New York, NY, USA, 15–18 July 2019; Springer: Cham, Switzerland, 2019; pp. 3–22. [Google Scholar]
- Jonk, R.; Voeten, J.; Geilen, M.; Basten, T.; Schiffelers, R. SMT-based verification of temporal properties for component-based software systems. IFAC-PapersOnLine 2020, 53, 493–500. [Google Scholar] [CrossRef]
- Smith, R.L.; Bersani, M.M.; Rossi, M.; San Pietro, P. Improved Bounded Model Checking of Timed Automata. In Proceedings of the 9th IEEE/ACM International Conference on Formal Methods in Software Engineering, FormaliSE@ICSE 2021, Madrid, Spain, 17–21 May 2021; Bliudze, S., Gnesi, S., Plat, N., Semini, L., Eds.; IEEE: Piscataway, NJ, USA, 2021; pp. 97–110. [Google Scholar] [CrossRef]
- Hofmann, T.; Schupp, S. Controlling Timed Automata against MTL Specifications with TACoS. Sci. Comput. Program. 2022, 225, 102898. [Google Scholar] [CrossRef]
- Hustadt, U.; Ozaki, A.; Dixon, C. Theorem Proving for Pointwise Metric Temporal Logic Over the Naturals via Translations. J. Autom. Reason. 2020, 64, 1553–1610. [Google Scholar] [CrossRef] [Green Version]
- Ouaknine, J.; Worrell, J. Some Recent Results in Metric Temporal Logic. In Proceedings of the Formal Modeling and Analysis of Timed Systems, 6th International Conference, FORMATS 2008, Saint Malo, France, 15–17 September 2008; Cassez, F., Jard, C., Eds.; Springer: Berlin/Heidelberg, Germany, 2008; Volume 5215, pp. 1–13. [Google Scholar] [CrossRef]
- D’Souza, D.; Prabhakar, P. On the expressiveness of MTL in the pointwise and continuous semantics. Int. J. Softw. Tools Technol. Transf. 2007, 9, 1–4. [Google Scholar] [CrossRef]
- Bouyer, P.; Chevalier, F.; Markey, N. On the expressiveness of TPTL and MTL. Inf. Comput. 2010, 208, 97–116. [Google Scholar] [CrossRef] [Green Version]
- Zbrzezny, A.M.; Zbrzezny, A. Checking MTL Properties of Timed Automata with Dense Time using Satisfiability Modulo Theories (Extended Abstract). In Proceedings of the 28th International Workshop on CS&P, Olsztyn, Poland, 24–26 September 2019; Volume 2571. [Google Scholar]
- Bonakdarpour, B.; Prabhakar, P.; Sánchez, C. Model checking timed hyperproperties in discrete-time systems. In Proceedings of the NASA Formal Methods Symposium, Moffett Field, CA, USA, 11–15 May 2020; Springer: Cham, Switzerland, 2020; pp. 311–328. [Google Scholar]
- Penczek, W.; Półrola, A. Advances in Verification of Time Petri Nets and Timed Automata: A Temporal Logic Approach; Studies in Computational Intelligence; Springer: Berlin/Heidelberg, Germany, 2006; Volume 20. [Google Scholar]
- Tripakis, S.; Yovine, S. Analysis of Timed Systems Using Time-Abstracting Bisimulations. Form. Methods Syst. Des. 2001, 18, 25–68. [Google Scholar] [CrossRef]
- Zbrzezny, A. A new translation from ECTL* to SAT. Fundam. Informaticae 2012, 120, 377–397. [Google Scholar] [CrossRef]
- Biere, A.; Fazekas, K.; Fleury, M.; Heisinger, M. CaDiCaL, Kissat, Paracooba, Plingeling and Treengeling Entering the SAT Competition 2020. In Proceedings of the SAT Competition 2020–Solver and Benchmark Descriptions, virtual event affiliated with the 23rd International Conference on Theory and Applications of Satisfiability Testing, Alghero, Italy, 5–9 July 2020; Balyo, T., Froleyks, N., Heule, M., Iser, M., Järvisalo, M., Suda, M., Eds.; University of Helsinki: Helsinki, Finland, 2020; Volume B-2020-1, pp. 51–53. [Google Scholar]
- Probst, D.K.; Li, H.F. Verifying Timed Behavior Automata with Nonbinary Delay Constraints. In Proceedings of the Computer Aided Verification, Fourth International Workshop, CAV ’92, Montreal, QC, Canada, 29 June–1 July 1992; von Bochmann, G., Probst, D.K., Eds.; Springer: Berlin/Heidelberg, Germany, 1992; Volume 663, pp. 123–136. [Google Scholar] [CrossRef]
- Zbrzezny, A.; Pólrola, A. SAT-Based Reachability Checking for Timed Automata with Discrete Data. Fundam. Informaticae 2007, 79, 579–593. [Google Scholar]
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |
© 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
Share and Cite
Zbrzezny, A.M.; Zbrzezny, A. Bounded Model Checking for Metric Temporal Logic Properties of Timed Automata with Digital Clocks. Sensors 2022, 22, 9552. https://doi.org/10.3390/s22239552
Zbrzezny AM, Zbrzezny A. Bounded Model Checking for Metric Temporal Logic Properties of Timed Automata with Digital Clocks. Sensors. 2022; 22(23):9552. https://doi.org/10.3390/s22239552
Chicago/Turabian StyleZbrzezny, Agnieszka M., and Andrzej Zbrzezny. 2022. "Bounded Model Checking for Metric Temporal Logic Properties of Timed Automata with Digital Clocks" Sensors 22, no. 23: 9552. https://doi.org/10.3390/s22239552
APA StyleZbrzezny, A. M., & Zbrzezny, A. (2022). Bounded Model Checking for Metric Temporal Logic Properties of Timed Automata with Digital Clocks. Sensors, 22(23), 9552. https://doi.org/10.3390/s22239552