HARDWARE MODELS FOR AUTOMATED PARTITIONING AND MAPPING IN MULTI-CORE SYSTEMS USING MATHEMATICAL ALGORITHMS
DOI:
https://doi.org/10.47839/ijc.12.4.614Keywords:
Multi-core, hardware model, embedded systems software development, target mapping, model-driven development, Autosar.Abstract
Multi-core CPUs offer several major benefits in embedded systems. For instance, they usually provide higher energy efficiency and more computing power compared to single-core CPUs. However, these benefits do not come for free: A program has to be divided into tasks, which can be executed in parallel on different cores. Partitioning of software and mapping on cores are nontrivial activities that require detailed knowledge about the underlying hardware platform, e.g., the number of cores, their speed, available memories, etc. Such information is typically stored in handbooks. If this information would be available in a machine readable model, we call it hardware model, the partitioning and mapping activities can be automated. In this paper, we propose a hardware model and illustrate it using an example of a Freescale multi-core CPU. We then discuss a small case study situated in the automotive domain, which illustrates the use of the hardware model in partitioning, mapping, and code generation.References
P. Marwedel. Embedded System Design: Embedded systems foundations of cyber-physical systems, Springer Science+ Business Media, 2011.
A. P. Consortium et al., EAST-ADL domain model specification, 2010. [Online]. Available: http://www.east-adl.info
AUTOSAR, Automotive open system architecture, 2007. [Online]. Available: http://www.autosar.org
D. Cordes, P. Marwedel, and A. Mallik. Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming, in IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010, pp. 267–276.
L. Krawczyk and E. Kamsties. Hardware models for automated partitioning and mapping in multi-core systems, in Proceedings of the 7th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS 2013), Berlin, Germany, 12-14 September 2013, pp. 721-725.
I. T. Foster. Designing and Building Parallel Programs. Reading, Mass.: Addison-Wesley, 1995.
J. Herrington. Code Generation in Action, Manning Publications Co., USA, 2003.
R. Hoettger, B. Igel and E. Kamsties. A novel partitioning and tracing approach for distributed systems based on vector clocks, inProceedings of the 7th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS 2013), Berlin, Germany, 12-14 September 2013, pp. 670-675.
M. Drozdowski. Scheduling for Parallel Processing, Springer London, 2010.
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