Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Wikipedia

AMD Eyefinity

AMD Eyefinity is a brand name for AMD video card products that support multi-monitor setups by integrating multiple (up to six) display controllers on one GPU.[1] AMD Eyefinity was introduced with the Radeon HD 5000 series "Evergreen" in September 2009 and has been available on APUs and professional-grade graphics cards branded AMD FirePro as well.[2]

AMD Eyefinity
Design firmAdvanced Micro Devices
IntroducedSeptember 2009
TypeMulti-monitor or video walls
PortsDisplayPort,
HDMI, DVI, VGA, DMS-59, VHDCI
Playing a racing video game on Single Large Surface (SLS) with a 5x1 portrait display group configuration at ExtravaLANza 2012 in Toronto

AMD Eyefinity supports a maximum of 2 non-DisplayPort displays (e.g., HDMI, DVI, VGA, DMS-59, VHDCI) (which AMD calls "legacy output") and up to 6 DisplayPort displays simultaneously using a single graphics card or APU. To feed more than two displays, the additional panels must have native DisplayPort support.[3] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.[4]

The setup of large video walls by connecting multiple computers over Gigabit Ethernet or Ethernet is also supported.[5]

The version of AMD Eyefinity (aka DCE, display controller engine) introduced with Excavator-based Carrizo APUs features a Video underlay pipe.[6]

Overview

edit

AMD Eyefinity is implemented by multiple on-die display controllers. The HD 5000-series designs host two internal clocks and one external clock. Displays connected over VGA, DVI, or HDMI each require their own internal clock. But all displays connected over DisplayPort can be driven from only one external clock. This external clock is what allows Eyefinity to fuel up to six monitors from a single card.

The entire HD 5000 series of products have Eyefinity capabilities supporting three outputs. The Radeon HD 5870 Eyefinity Edition, however, supports six mini DisplayPort outputs, all of which can be simultaneously active.[7]

The display controller has two RAMDACs that drive the VGA or DVI ports in analog mode. For example, when a DVI-to-VGA converter is attached to a DVI port). It also has a maximum of six digital transmitters that can output either a DisplayPort signal or a TMDS signal for either DVI or HDMI, and two clock signal generators to drive the digital outputs in TMDS mode. Dual-link DVI displays use two of the TMDS/DisplayPort transmitters and one clock signal each. Single-link DVI displays and HDMI displays use one TMDS/DisplayPort transmitter and one clock signal each. DisplayPort displays use one TMDS/DisplayPort transmitter and no clock signal.

An active DisplayPort adapter can convert a DisplayPort signal to another type of signal—like VGA, single-link DVI, or dual-link DVI; or HDMI if more than two non-DisplayPort displays must be connected to a Radeon HD 5000 series graphics card.[7]

DisplayPort 1.2 added the possibility to drive multiple displays on single DisplayPort connector, called Multi-Stream Transport (MST). AMD graphics solutions equipped with DisplayPort 1.2 outputs can run multiple monitors from a single port.

At High-Performance Graphics 2010 Mark Fowler presented the Evergreen and stated that e.g. 5870 (Cypress), 5770 (Juniper) and 5670 (Redwood) support max resolution of the 6 times 2560×1600 pixels, while the 5470 (Cedar) supports 4 times 2560×1600 pixels.[8]

Availability

edit

Feature overview for AMD graphics cards

edit
Main article: List of Radeon graphics cards

All AMD GPUs starting with the Evergreen series support a maximum of 2 non-DisplayPort displays and a maximum of 6 DisplayPort displays per graphics card.[4]

The following table shows features of AMD/ATI's GPUs (see also: List of AMD graphics processing units).

[ VisualEditor ]
Name of GPU series Wonder Mach 3D Rage Rage Pro Rage 128 R100 R200 R300 R400 R500 R600 RV670 R700 Evergreen Northern
Islands 		Southern
Islands 		Sea
Islands 		Volcanic
Islands 		Arctic
Islands/Polaris 		Vega Navi 1x Navi 2x Navi 3x
Released 1986 1991 Apr
1996 		Mar
1997 		Aug
1998 		Apr
2000 		Aug
2001 		Sep
2002 		May
2004 		Oct
2005 		May
2007 		Nov
2007 		Jun
2008 		Sep
2009 		Oct
2010 		Dec
2010 		Jan
2012 		Sep
2013 		Jun
2015 		Jun 2016, Apr 2017, Aug 2019 Jun 2017, Feb 2019 Jul
2019 		Nov
2020 		Dec
2022
Marketing Name Wonder Mach 3D
Rage 		Rage
Pro 		Rage
128 		Radeon
7000 		Radeon
8000 		Radeon
9000 		Radeon
X700/X800 		Radeon
X1000 		Radeon
HD 2000 		Radeon
HD 3000 		Radeon
HD 4000 		Radeon
HD 5000 		Radeon
HD 6000 		Radeon
HD 7000 		Radeon
200 		Radeon
300 		Radeon
400/500/600 		Radeon
RX Vega, Radeon VII 		Radeon
RX 5000 		Radeon
RX 6000 		Radeon
RX 7000
AMD support    
Kind 2D 3D
Instruction set architecture Not publicly known TeraScale instruction set GCN instruction set RDNA instruction set
Microarchitecture TeraScale 1
(VLIW) 		TeraScale 2
(VLIW5) 		TeraScale 2
(VLIW5)
up to 68xx 		TeraScale 3
(VLIW4)
in 69xx [9][10] 		GCN 1st
gen 		GCN 2nd
gen 		GCN 3rd
gen 		GCN 4th
gen 		GCN 5th
gen 		RDNA RDNA 2 RDNA 3
Type Fixed pipeline[a] Programmable pixel & vertex pipelines Unified shader model
Direct3D — 5.0 6.0 7.0 8.1 9.0
11 (9_2) 		9.0b
11 (9_2) 		9.0c
11 (9_3) 		10.0
11 (10_0) 		10.1
11 (10_1) 		11 (11_0) 11 (11_1)
12 (11_1) 		11 (12_0)
12 (12_0) 		11 (12_1)
12 (12_1) 		11 (12_1)
12 (12_2)
Shader model — 1.4 2.0+ 2.0b 3.0 4.0 4.1 5.0 5.1 5.1
6.5 		6.7
OpenGL — 1.1 1.2 1.3 2.1[b][11] 3.3 4.5[12][13][14][c] 4.6
Vulkan — 1.1 1.3
OpenCL — Close to Metal 1.1 (not supported by Mesa) 1.2+ (on Linux: 1.1+ (no Image support on clover, with by rustiCL) with Mesa, 1.2+ on GCN 1.Gen) 2.0+ (Adrenalin driver on Win7+)
(on Linux ROCM, Mesa 1.2+ (no Image support in clover, but in rustiCL with Mesa, 2.0+ and 3.0 with AMD drivers or AMD ROCm), 5th gen: 2.2 win 10+ and Linux RocM 5.0+ 		2.2+ and 3.0 windows 8.1+ and Linux ROCM 5.0+ (Mesa rustiCL 1.2+ and 3.0 (2.1+ and 2.2+ wip))[15][16][17]
HSA / ROCm —   ?
Video decoding ASIC — Avivo/UVD UVD+ UVD 2 UVD 2.2 UVD 3 UVD 4 UVD 4.2 UVD 5.0 or 6.0 UVD 6.3 UVD 7 [18][d] VCN 2.0 [18][d] VCN 3.0 [19] VCN 4.0
Video encoding ASIC — VCE 1.0 VCE 2.0 VCE 3.0 or 3.1 VCE 3.4 VCE 4.0 [18][d]
Fluid Motion [e]       ?
Power saving ? PowerPlay PowerTune PowerTune & ZeroCore Power ?
TrueAudio — Via dedicated DSP Via shaders
FreeSync — 1
2
HDCP[f] — ? 1.4 2.2 2.3 [20]
PlayReady[f] — 3.0   3.0
Supported displays[g] 1–2 2 2–6 ?
Max. resolution ? 2–6 ×
2560×1600 		2–6 ×
4096×2160 @ 30 Hz 		2–6 ×
5120×2880 @ 60 Hz 		3 ×
7680×4320 @ 60 Hz [21]
7680×4320 @ 60 Hz PowerColor 		7680x4320

@165 HZ

/drm/radeon[h]   —
/drm/amdgpu[h] — Optional [22]  
  1. ^ The Radeon 100 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders.
  2. ^ R300, R400 and R500 based cards do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power of two (NPOT) textures.
  3. ^ OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware.
  4. ^ a b c The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega.
  5. ^ Video processing for video frame rate interpolation technique. In Windows it works as a DirectShow filter in your player. In Linux, there is no support on the part of drivers and / or community.
  6. ^ a b To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  7. ^ More displays may be supported with native DisplayPort connections, or splitting the maximum resolution between multiple monitors with active converters.
  8. ^ a b DRM (Direct Rendering Manager) is a component of the Linux kernel. AMDgpu is the Linux kernel module. Support in this table refers to the most current version.

Feature overview for AMD APUs

edit
Main article: List of AMD APUs

AMD Eyefinity is also available in AMD's APU branded product line. The A10-7850K is said to support up to four displays.

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

[ VisualEditor ]
Platform High, standard and low power Low and ultra-low power
Codename Server Basic Toronto
Micro Kyoto
Desktop Performance Raphael Phoenix
Mainstream Llano Trinity Richland Kaveri Kaveri Refresh (Godavari) Carrizo Bristol Ridge Raven Ridge Picasso Renoir Cezanne
Entry
Basic Kabini Dalí
Mobile Performance Renoir Cezanne Rembrandt Dragon Range
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso Renoir
Lucienne 		Cezanne
Barceló 		Phoenix
Entry Dalí Mendocino
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge Pollock
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon 		Great Horned Owl Grey Hawk Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family 		Prairie Falcon Banded Kestrel River Hawk
Released Aug 2011 Oct 2012 Jun 2013 Jan 2014 2015 Jun 2015 Jun 2016 Oct 2017 Jan 2019 Mar 2020 Jan 2021 Jan 2022 Sep 2022 Jan 2023 Jan 2011 May 2013 Apr 2014 May 2015 Feb 2016 Apr 2019 Jul 2020 Jun 2022 Nov 2022
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+"[23] Zen Zen+ Zen 2 Zen 3 Zen 3+ Zen 4 Bobcat Jaguar Puma Puma+[24] "Excavator+" Zen Zen+ "Zen 2+"
ISA x86-64 v1 x86-64 v2 x86-64 v3 x86-64 v4 x86-64 v1 x86-64 v2 x86-64 v3
Socket Desktop Performance — AM5 — —
Mainstream — AM4 — —
Entry FM1 FM2 FM2+ FM2+[a], AM4 AM4 —
Basic — — AM1 — FP5 —
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FP7 FL1 FP7
FP7r2
FP8 		? FT1 FT3 FT3b FP4 FP5 FT5 FP5 FT6
PCI Express version 2.0 3.0 4.0 5.0 4.0 2.0 3.0
CXL — —
Fab. (nm) GF 32SHP
(HKMG SOI) 		GF 28SHP
(HKMG bulk) 		GF 14LPP
(FinFET bulk) 		GF 12LP
(FinFET bulk) 		TSMC N7
(FinFET bulk) 		TSMC N6
(FinFET bulk) 		CCD: TSMC N5
(FinFET bulk)
cIOD: TSMC N6
(FinFET bulk) 		TSMC 4nm
(FinFET bulk) 		TSMC N40
(bulk) 		TSMC N28
(HKMG bulk) 		GF 28SHP
(HKMG bulk) 		GF 14LPP
(FinFET bulk) 		GF 12LP
(FinFET bulk) 		TSMC N6
(FinFET bulk)
Die area (mm2) 228 246 245 245 250 210[25] 156 180 210 CCD: (2x) 70
cIOD: 122 		178 75 (+ 28 FCH) 107 ? 125 149 ~100
Min TDP (W) 35 17 12 10 15 65 35 4.5 4 3.95 10 6 12 8
Max APU TDP (W) 100 95 65 45 170 54 18 25 6 54 15
Max stock APU base clock (GHz) 3 3.8 4.1 4.1 3.7 3.8 3.6 3.7 3.8 4.0 3.3 4.7 4.3 1.75 2.2 2 2.2 3.2 2.6 1.2 3.35 2.8
Max APUs per node[b] 1 1
Max core dies per CPU 1 2 1 1
Max CCX per core die 1 2 1 1
Max cores per CCX 4 8 2 4 2 4
Max CPU[c] cores per APU 4 8 16 8 2 4 2 4
Max threads per CPU core 1 2 1 2
Integer pipeline structure 3+3 2+2 4+2 4+2+1 1+3+3+1+2 1+1+1+1 2+2 4+2 4+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF    
IOMMU[d] — v2 v1 v2
BMI1, AES-NI, CLMUL, and F16C   —  
MOVBE —  
AVIC, BMI2, RDRAND, and MWAITX/MONITORX —  
SME[e], TSME[e], ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing —   —  
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT —   —  
MPK, VAES —   —
SGX — —
FPUs per core 1 0.5 1 1 0.5 1
Pipes per FPU 2 2
FPU pipe width 128-bit 256-bit 80-bit 128-bit 256-bit
CPU instruction set SIMD level SSE4a[f] AVX AVX2 AVX-512 SSSE3 AVX AVX2
3DNow! 3DNow!+ — —
PREFETCH/PREFETCHW    
GFNI —   —
AMX —
FMA4, LWP, TBM, and XOP —   — —   —
FMA3    
AMD XDNA —   —
L1 data cache per core (KiB) 64 16 32 32
L1 data cache associativity (ways) 2 4 8 8
L1 instruction caches per core 1 0.5 1 1 0.5 1
Max APU total L1 instruction cache (KiB) 256 128 192 256 512 256 64 128 96 128
L1 instruction cache associativity (ways) 2 3 4 8 2 3 4 8
L2 caches per core 1 0.5 1 1 0.5 1
Max APU total L2 cache (MiB) 4 2 4 16 1 2 1 2
L2 cache associativity (ways) 16 8 16 8
Max on--die L3 cache per CCX (MiB) — 4 16 32 — 4
Max 3D V-Cache per CCD (MiB) — 64 — —
Max total in-CCD L3 cache per APU (MiB) 4 8 16 64 4
Max. total 3D V-Cache per APU (MiB) — 64 — —
Max. board L3 cache per APU (MiB) — —
Max total L3 cache per APU (MiB) 4 8 16 128 4
APU L3 cache associativity (ways) 16 16
L3 cache scheme Victim Victim
Max. L4 cache — —
Max stock DRAM support DDR3-1866 DDR3-2133 DDR3-2133, DDR4-2400 DDR4-2400 DDR4-2933 DDR4-3200, LPDDR4-4266 DDR5-4800, LPDDR5-6400 DDR5-5200 DDR5-5600, LPDDR5x-7500 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3-1866, DDR4-2400 DDR4-2400 DDR4-1600 DDR4-3200 LPDDR5-5500
Max DRAM channels per APU 2 1 2 1 2
Max stock DRAM bandwidth (GB/s) per APU 29.866 34.132 38.400 46.932 68.256 102.400 83.200 120.000 10.666 12.800 14.933 19.200 38.400 12.800 51.200 88.000
GPU microarchitecture TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 2nd gen GCN 3rd gen GCN 5th gen[26] RDNA 2 RDNA 3 TeraScale 2 (VLIW5) GCN 2nd gen GCN 3rd gen[26] GCN 5th gen RDNA 2
GPU instruction set TeraScale instruction set GCN instruction set RDNA instruction set TeraScale instruction set GCN instruction set RDNA instruction set
Max stock GPU base clock (MHz) 600 800 844 866 1108 1250 1400 2100 2400 400 538 600 ? 847 900 1200 600 1300 1900
Max stock GPU base GFLOPS[g] 480 614.4 648.1 886.7 1134.5 1760 1971.2 2150.4 3686.4 102.4 86 ? ? ? 345.6 460.8 230.4 1331.2 486.4
3D engine[h] Up to 400:20:8 Up to 384:24:6 Up to 512:32:8 Up to 704:44:16[27] Up to 512:32:8 768:48:8 128:8:4 80:8:4 128:8:4 Up to 192:12:8 Up to 192:12:4 192:12:4 Up to 512:?:? 128:?:?
IOMMUv1 IOMMUv2 IOMMUv1 ? IOMMUv2
Video decoder UVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0[28] VCN 2.1[29] VCN 2.2[29] VCN 3.1 ? UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.2 VCN 1.0 VCN 3.1
Video encoder — VCE 1.0 VCE 2.0 VCE 3.1 — VCE 2.0 VCE 3.4
AMD Fluid Motion            
GPU power saving PowerPlay PowerTune PowerPlay PowerTune[30]
TrueAudio —  [31] ? —  
FreeSync 1
2 		1
2
HDCP[i] ? 1.4 2.2 2.3 ? 1.4 2.2 2.3
PlayReady[i] — 3.0 not yet — 3.0 not yet
Supported displays[j] 2–3 2–4 3 3 (desktop)
4 (mobile, embedded)		 4 2 3 4 4
/drm/radeon[k][33][4]   —   —
/drm/amdgpu[k][34] —  [35] —  [35]
  1. ^ For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  2. ^ A PC would be one node.
  3. ^ An APU combines a CPU and a GPU. Both have cores.
  4. ^ Requires firmware support.
  5. ^ a b Requires firmware support.
  6. ^ No SSE4. No SSSE3.
  7. ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  8. ^ Unified shaders : texture mapping units : render output units
  9. ^ a b To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  10. ^ To feed more than two displays, the additional panels must have native DisplayPort support.[32] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  11. ^ a b DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

Software support

edit
 
Support for the Eyefinity display controller is available in the Linux kernel device driver amdgpu and accessible via the DRM/KMS API.

AMD Catalyst supports Eyefinity and enables the user to independently configure and run each attached displays. It facilitates the configuration of "cloned mode", i.e. to copy one desktop onto multiple screens or "extended mode", i.e. to span the workspace across multiple screens and combine the resolutions of all of those displays into one big resolution. AMD calls the extended modes Single Large Surface (SLS) and Catalyst support of certain range of display group configurations. For example, 5x1 landscape and 5x1 portrait are supported since AMD Catalyst version 11.10 from October 2011.[2][36]

Starting in Catalyst 14.6, AMD supports mixed resolution support, so a single Eyefinity display group can drive each monitor at a different resolution. This is provided through two new Eyefinity display modes, Fit and Expand, in addition to the existing Fill mode. In Fit or Expand mode, AMD compensates for mismatched resolutions by creating a virtual desktop of a different resolution than the monitors, and then either padding it out or cropping it as is necessary.[37]

AMD Eyefinity works with games that support non-standard aspect ratios, which is required for panning across multiple displays. SLS ("Single Large Surface") mode requires an identical display resolution on all configured displays. AMD validated some video games to support Eyefinity. The short list includes titles such as Age of Conan, ARMA 2: Operation Arrowhead, S.T.A.L.K.E.R.: Call of Pripyat, Serious Sam 3: BFE, Singularity (video game), Sleeping Dogs, Assassin's Creed II, Sniper Elite V2, Soldier of Fortune Online, Tom Clancy's Splinter Cell: Conviction, Star Wars: The Force Unleashed 2, Marvel Super Hero Squad Online, R.U.S.E., Supreme Commander 2 among others.[38] However, some games not on this short list seem to work as well, e.g. Dirt 3 and The Elder Scrolls V: Skyrim.

KMS driver supports AMD Eyefinity.[4]

See also

edit
 
Wikimedia Commons has media related to AMD Eyefinity.

References

edit
  1. ^ "AMD's Radeon HD 5870 Eyefinity 6 Edition Reviewed". AnandTech. 2010-03-31. Retrieved 2014-07-02.
  2. ^ a b "AMD Eyefinity: FAQ". AMD. 2011-05-17. Retrieved 2014-07-02.
  3. ^ "How do I connect three or More Monitors to an AMD Radeon HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 2014-12-08.
  4. ^ a b c d "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
  5. ^ "Configuring and Running a Large Video Wall using ATI FirePro Graphics" (PDF). Retrieved 2014-07-04.
  6. ^ "Carrizo introduces a new video playback pathways".
  7. ^ a b "AMD Eyefinity on AMD Radeon HD 5870". Tom's Hardware. 2009-09-23. Retrieved 2014-07-02.
  8. ^ "Presenting Radeon HD 5000" (PDF).
  9. ^ "AMD Radeon HD 6900 (AMD Cayman) series graphics cards". HWlab. hw-lab.com. December 19, 2010. Archived from the original on August 23, 2022. Retrieved August 23, 2022. New VLIW4 architecture of stream processors allowed to save area of each SIMD by 10%, while performing the same compared to previous VLIW5 architecture
  10. ^ "GPU Specs Database". TechPowerUp. Retrieved August 23, 2022.
  11. ^ "NPOT Texture (OpenGL Wiki)". Khronos Group. Retrieved February 10, 2021.
  12. ^ "AMD Radeon Software Crimson Edition Beta". AMD. Retrieved 2018-04-20.
  13. ^ "Mesamatrix". mesamatrix.net. Retrieved 2018-04-22.
  14. ^ "RadeonFeature". X.Org Foundation. Retrieved 2018-04-20.
  15. ^ "AMD Radeon RX 6800 XT Specs". TechPowerUp. Retrieved January 1, 2021.
  16. ^ "AMD Launches The Radeon PRO W7500/W7600 RDNA3 GPUs". Phoronix. 3 August 2023. Retrieved 4 September 2023.
  17. ^ "AMD Radeon Pro 5600M Grafikkarte". TopCPU.net (in German). Retrieved 4 September 2023.
  18. ^ a b c Killian, Zak (March 22, 2017). "AMD publishes patches for Vega support on Linux". Tech Report. Retrieved March 23, 2017.
  19. ^ Larabel, Michael (September 15, 2020). "AMD Radeon Navi 2 / VCN 3.0 Supports AV1 Video Decoding". Phoronix. Retrieved January 1, 2021.
  20. ^ Edmonds, Rich (February 4, 2022). "ASUS Dual RX 6600 GPU review: Rock-solid 1080p gaming with impressive thermals". Windows Central. Retrieved November 1, 2022.
  21. ^ "Radeon's next-generation Vega architecture" (PDF). Radeon Technologies Group (AMD). Archived from the original (PDF) on September 6, 2018. Retrieved June 13, 2017.
  22. ^ "AMDGPU". Retrieved December 29, 2023.
  23. ^ "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
  24. ^ "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
  25. ^ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  26. ^ a b "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  27. ^ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  28. ^ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  29. ^ a b "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021.
  30. ^ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
  31. ^ "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
  32. ^ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
  33. ^ Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
  34. ^ Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
  35. ^ a b Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
  36. ^ "AMD's Eyefinity Technology Explained". Tom's Hardware. 2010-02-28. Retrieved 2014-07-02.
  37. ^ "AMD Catalyst 14.6 beta adds new Eyefinity functionality". AnandTech. 2014-05-27. Retrieved 2014-07-02.
  38. ^ "AMD Eyefinity Validated and Ready Software".
edit
Retrieved from "https://en.wikipedia.org/w/index.php?title=AMD_Eyefinity&oldid=1211250953"