Logic optimization

For other uses, see Minimisation.

Logic optimization is a process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. This process is a part of a logic synthesis applied in digital electronics and integrated circuit design.

Generally, the circuit is constrained to a minimum chip area meeting a predefined response delay. The goal of logic optimization of a given circuit is to obtain the smallest logic circuit that evaluates to the same values as the original one. The smaller circuit with the same function is cheaper, takes less space, consumes less power, have shorter latency, and minimizes risks of unexpected cross-talk, hazard of delayed signal processing, and other issues present at the nano-scale level of metallic structures on a integrated circuit.

In terms of Boolean algebra, the optimization of a complex boolean expression is a process of finding a simpler one, which would upon evaluation ultimately produce the same results as the original one.

Motivation

The problem with having a complicated circuit (i.e. one with many elements, such as logic gates) is that each element takes up physical space in its implementation and costs time and money to produce in itself. Circuit minimization may be one form of logic optimization used to reduce the area of complex logic in integrated circuits.

With the advent of logic synthesis, one of the biggest challenges faced by the electronic design automation (EDA) industry was to find the most simple circuit representation of the given design description. While two-level logic optimization had long existed in the form of the Quine–McCluskey algorithm, later followed by the Espresso heuristic logic minimizer, the rapidly improving chip densities, and the wide adoption of Hardware description languages for circuit description, formalized the logic optimization domain as it exists today, including Logic Friday (graphical interface), Minilog, and ESPRESSO-IISOJS (many-valued logic).

Methods

The methods of logic circuit simplifications are equally applicable to the boolean expression minimization.

Classification

Today, logic optimization is divided into various categories:

Based on circuit representation

Two-level logic optimization

Multi-level logic optimization

Based on circuit characteristics

Sequential logic optimization

Combinational logic optimization

Based on type of execution

Graphical optimization methods

Tabular optimization methods

Algebraic optimization methods

Graphical methods

Graphical methods represent the required logical function by a diagram representing the logic variables and value of the function. By manipulating or inspecting a diagram, much tedious calculation may be eliminated. Graphical minimization methods for two-level logic include:

• Euler diagram (aka Eulerian circle) (1768) by Leonhard P. Euler (1707–1783)
• Venn diagram (1880) by John Venn (1834–1923)
• Karnaugh map (1953) by Maurice Karnaugh

Boolean expression minimization

The same methods of boolean expression minimization (simplification) listed below may be applied to the circuit optimization.

For the case when the Boolean function is specified by a circuit (that is, we want to find an equivalent circuit of minimum size possible), the unbounded circuit minimization problem was long-conjectured to be $\Sigma _{2}^{P}$-complete in time complexity (the complexity class of decision problems that can be solved on a deterministic Turing machine in polynomial time), a result finally proved in 2008, but there are effective heuristics such as Karnaugh maps and the Quine–McCluskey algorithm that facilitate the process.

Boolean function minimizing methods include:

• Quine–McCluskey algorithm

• Petrick's method

Espresso heuristic logic minimizer

This section is an excerpt from Espresso heuristic logic minimizer § ESPRESSO algorithm.[edit]

A different approach to this issue is followed in the ESPRESSO algorithm, developed by Brayton et al. at the University of California, Berkeley. It is a resource and performance efficient algorithm aimed at solving the heuristic hazard-free two-level logic minimization problem.

Rather than expanding a logic function into minterms, the program manipulates "cubes", representing the product terms in the ON-, DC-, and OFF- covers iteratively. Although the minimization result is not guaranteed to be the global minimum, in practice this is very closely approximated, while the solution is always free from redundancy. Compared to the other methods, this one is essentially more efficient, reducing memory usage and computation time by several orders of magnitude. Its name reflects the way of instantly making a cup of fresh coffee. There is hardly any restriction to the number of variables, output functions and product terms of a combinational function block. In general, e.g. tens of variables with tens of output functions are readily dealt with.

The input for ESPRESSO is a function table of the desired functionality; the result is a minimized table, describing either the ON-cover or the OFF-cover of the function, depending on the selected options. By default, the product terms will be shared as much as possible by the several output functions, but the program can be instructed to handle each of the output functions separately. This allows for efficient implementation in two-level logic arrays such as a PLA (Programmable Logic Array) or a PAL (Programmable Array Logic).

The ESPRESSO algorithm proved so successful that it has been incorporated as a standard logic function minimization step into virtually any contemporary logic synthesis tool. For implementing a function in multi-level logic, the minimization result is optimized by factorization and mapped onto the available basic logic cells in the target technology, whether this concerns a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

Two-level versus multi-level representations

While a two-level circuit representation of circuits strictly refers to the flattened view of the circuit in terms of SOPs (sum-of-products) — which is more applicable to a PLA implementation of the design — a multi-level representation is a more generic view of the circuit in terms of arbitrarily connected SOPs, POSs (product-of-sums), factored form etc. Logic optimization algorithms generally work either on the structural (SOPs, factored form) or functional (Binary decision diagrams, Algebraic Decision Diagrams (ADDs)) representation of the circuit. In sum-of-products (SOP) form, AND gates form the smallest unit and are stitched together using ORs, whereas in product-of-sums (POS) form it is opposite. POS form requires parentheses to group the OR terms together under AND gates, because OR has lower precedence than AND. Both SOP and POS forms translate nicely into circuit logic.

If we have two functions F₁ and F₂:

$F_{1}=AB+AC+AD,\,$

$F_{2}=A'B+A'C+A'E.\,$

The above 2-level representation takes six product terms and 24 transistors in CMOS Rep.

A functionally equivalent representation in multilevel can be:

P = B + C.

F₁ = AP + AD.

F₂ = A'P + A'E.

While the number of levels here is 3, the total number of product terms and literals reduce because of the sharing of the term B + C.

Similarly, we distinguish between sequential and combinational circuits, whose behavior can be described in terms of finite-state machine state tables/diagrams or by Boolean functions and relations respectively. Combinational circuits are defined as the time independent circuits which do not depends upon previous inputs to generate any output are termed as combinational circuits. Examples – Encoder, Decoder, Multiplexer, Demultiplexer.

Sequential circuits are those which are dependent on clock cycles and depends on present as well as past inputs to generate any output. Examples – Flip-flops, Counters.

Example

Original and simplified example circuit

While there are many ways to minimize a circuit, this is an example that minimizes (or simplifies) a Boolean function. The Boolean function carried out by the circuit is directly related to the algebraic expression from which the function is implemented. Consider the circuit used to represent $(A\wedge {\bar {B}})\vee ({\bar {A}}\wedge B)$. It is evident that two negations, two conjunctions, and a disjunction are used in this statement. This means that to build the circuit one would need two inverters, two AND gates, and an OR gate.

The circuit can simplified (minimized) by applying laws of Boolean algebra or using intuition. Since the example states that $A$ is true when $B$ is false and the other way around, one can conclude that this simply means $A\neq B$. In terms of logical gates, inequality simply means an XOR gate (exclusive or). Therefore, $(A\wedge {\bar {B}})\vee ({\bar {A}}\wedge B)\iff A\neq B$. Then the two circuits shown below are equivalent, as can be checked using a truth table:

A	B		(A	∧	B)	∨	(A	∧	B)		A	≠	B
F	F		F	F	T	F	T	F	F		F	F	F
F	T		F	F	F	T	T	T	T		F	T	T
T	F		T	T	T	T	F	F	F		T	T	F
T	T		T	F	F	F	F	F	T		T	F	T

See also

• Binary decision diagram (BDD)
• Don't care condition
• Prime implicant
• Circuit complexity — on estimation of the circuit complexity
• Function composition
• Function decomposition
• Gate underutilization
• Harvard minimizing chart (Wikiversity) (Wikibooks)

Further reading

• Hwa, "Sherman" Hsuen Ren (June 1974). "A Method of Generating Prime Implicants of a Boolean Expression". IEEE Transactions on Computers. C-23 (6). IEEE: 637–641. doi:10.1109/T-C.1974.224003. eISSN 1557-9956. ISSN 0018-9340. S2CID 10646917. CD-ISSN 2326-3814. 1F09. Retrieved 2020-05-12; Hwa, "Sherman" Hsuen Ren (April 1973). A Method of Generating Prime Implicants of a Boolean Expression. Basser Department of Computer Science, University of Sydney. Technical Report 82.
• Lind, Larry Frederick; Nelson, John Christopher Cunliffe (1977). Analysis and Design of Sequential Digital Systems. Macmillan Press. ISBN 0-33319266-4. [1] (146 pages)
• Ghosh, Debidas (June 1977) [1977-01-21]. "A method of generating prime factors of a Boolean Expression in a conjunctive normal form with the possibility of inclusion of Don't care combination" (PDF). Journal of Technology. XXII (1). Department of Mathematics, Bengal Engineering College, Howrah, India. Archived (PDF) from the original on 2020-05-12. Retrieved 2020-05-12.
• De Micheli, Giovanni (1994). Synthesis and Optimization of Digital Circuits. McGraw-Hill. ISBN 0-07-016333-2. (NB. Chapters 7–9 cover combinatorial two-level, combinatorial multi-level, and respectively sequential circuit optimization.)
• Hachtel, Gary D.; Somenzi, Fabio (2006) [1996]. Logic Synthesis and Verification Algorithms. Springer Science & Business Media. ISBN 978-0-387-31005-3.
• Kohavi, Zvi; Jha, Niraj K. (2009). "4–6". Switching and Finite Automata Theory (3rd ed.). Cambridge University Press. ISBN 978-0-521-85748-2.
• Knuth, Donald Ervin (2010). "7.1.2: Boolean Evaluation". The Art of Computer Programming. Vol. 4A. Addison-Wesley. pp. 96–133. ISBN 978-0-201-03804-0.
• Rutenbar, Rob A. Multi-level minimization, Part I: Models & Methods (PDF) (lecture slides). Carnegie Mellon University (CMU). Lecture 7. Archived (PDF) from the original on 2018-01-15. Retrieved 2018-01-15; Rutenbar, Rob A. Multi-level minimization, Part II: Cube/Cokernel Extract (PDF) (lecture slides). Carnegie Mellon University (CMU). Lecture 8. Archived (PDF) from the original on 2018-01-15. Retrieved 2018-01-15.
• Tomaszewski, Sebastian P.; Celik, Ilgaz U.; Antoniou, George E. (December 2003) [2003-03-05, 2002-04-09]. "WWW-based Boolean function minimization" (PDF). International Journal of Applied Mathematics and Computer Science. 13 (4): 577–584. Archived (PDF) from the original on 2020-05-10. Retrieved 2020-05-10. [2][3] (7 pages)
• Wilhelmy, Alexander; Kudielka, Viktor; Deussen, Peter; Böhling, Karl Heinz [in German]; Händler, Wolfgang; Neander, Joachim (January 1963) [1961-10-18]. Dörr, Johannes; Peschl, Ernst Ferdinand; Unger, Heinz [in German] (eds.). 2. Colloquium über Schaltkreis- und Schaltwerk-Theorie - Vortragsauszüge vom 18. bis 20. Oktober 1961 in Saarbrücken. Internationale Schriftenreihe zur Numerischen Mathematik [International Series of Numerical Mathematics] (ISNM) (in German). Vol. 4 (2013-12-20 reprint of 1st ed.). Institut für Angewandte Mathematik, Universität Saarbrücken, Rheinisch-Westfälisches Institut für Instrumentelle Mathematik: Springer Basel AG / Birkhäuser Verlag Basel. doi:10.1007/978-3-0348-4156-6. ISBN 978-3-0348-4081-1. Retrieved 2020-04-15. (152 pages)
• Brayton, Robert King; Rudell, Richard L.; Sangiovanni-Vincentelli, Alberto Luigi; Wang, Albert R. (December 1987). "MIS: A Multiple-Level Logic Optimization System". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 6 (6): 1062–1081. doi:10.1109/TCAD.1987.1270347. {{cite journal}}: Check |author-link1= value (help) (MIS) (20 pages)
• De Geus, Aart J.; Cohen, William W. (July–August 1985). "A Rule-Based System for Optimizing Combinational Logic". IEEE Design & Test of Computers. 2 (4): 22–32. doi:10.1109/MDT.1985.294719. eISSN 1558-1918. ISSN 0740-7475. S2CID 46651690. Archived from the original on 2021-02-19. Retrieved 2021-02-19. (11 pages) [4] (SOCRATES)
• Khatri, Sunil P.; Gulati, Kanupriya, eds. (2011). Advanced Techniques in Logic Synthesis, Optimizations and Applications (1 ed.). New York / Dordrecht / Heidelberg / London: Springer Science+Business Media, LLC. ISBN 978-1-4419-7517-1. (xxii+423+1 pages)
• Jesse, Jobst E. (February 1972). Written at Sunnyvale, California, USA. "A More Efficient Use of Karnaugh Maps". Computer Design. Vol. 11, no. 2. Concord, Massachusetts, USA: Computer Design Publishing Corporation. pp. 80–82. ISSN 0010-4566. OCLC 828863003. CODEN CMPDA. (3 pages)
• Reusch, Bernd (September 1975). "Generation of Prime Implicants from Subfunctions and a Unifying Approach to the Covering Problem". IEEE Transactions on Computers. C-24 (9). IEEE: 924–930. doi:10.1109/T-C.1975.224338. eISSN 1557-9956. ISSN 0018-9340. S2CID 32090834. CD-ISSN 2326-3814. Retrieved 2021-02-19. (7 pages)
• Dineley, R. L. (April 1969). "To the Editor". Letters to the editor. Computer Design. Vol. 8, no. 4. Concord, Massachusetts, USA: Computer Design Publishing Corporation. p. 16. ISSN 0010-4566. OCLC 828863003. CODEN CMPDA. p. 16: […] I would like to offer a method for the simplification of maxterm type Boolean expression by use of the Veitch diagram. To the best of my knowledge, I am the originator of the method, having derived it in 1960 while attending the Digital Computer Fundamentals course at Redstone Arsenal. Most texts simplify the maxterm (product of sums) type expression by plotting the individual terms on separate Veitch diagrams and then overlaying the diagrams to discover the intersects, or "anded," function. […] The method offered here permits the plotting of all terms on one diagram with the "anded" relationship easily discernible. […] Each sum term of the expression is assigned a symbol. This symbol is plotted on the Veitch for each of the or'd factors of the term. The "and" function occurs whenever any square or combination of 2ⁿ adjacent squares contain all of the assigned symbols. A simple example will illustrate. […] (A + BC)^[1] (A + C)^[2] = A + BC […] Yours truly, R. L. Dineley, Sperry Rand Corp. (1 page) (NB. Referred to in Schultz's letter above.)
• Perkowski, Marek A.; Grygiel, Stanislaw (1995-11-20). "6. Historical Overview of the Research on Decomposition". A Survey of Literature on Function Decomposition (PDF). Version IV. Functional Decomposition Group, Department of Electrical Engineering, Portland University, Portland, Oregon, USA. CiteSeerX 10.1.1.64.1129. Archived (PDF) from the original on 2021-03-28. Retrieved 2021-03-28. (188 pages)
• Stanković, Radomir S.; Sasao, Tsutomu; Astola, Jaakko T. (August 2001). "Publications in the First Twenty Years of Switching Theory and Logic Design" (PDF). Tampere International Center for Signal Processing (TICSP) Series. Tampere University of Technology / TTKK, Monistamo, Finland. ISSN 1456-2774. S2CID 62319288. #14. Archived (PDF) from the original on 2017-08-09. Retrieved 2021-03-28. (4+60 pages)