MIPS_PROCESSOR

This project describes Verilog code for a 32-bit pipelined MIPS processor.

It is a combination of gate-level, dataflow and behavioural modelling.

Features:

Instruction Memory for 32-bit MIPS instructions.
32 32-bit Data Memory locations.
Instruction Memory consisting of arithmetic, logical, branch, jump, and memory-access instructions. Immediate arguments and argument registers are hard-coded.
5-stage pipelining; stages are: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), Writeback (WB).
Data Forwarding Unit to partially resolve hazards in R-type instructions.
Hazard Detection Unit to insert stalls (nop cycles) wherever required.

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
ALU.v		ALU.v
ALUControlUnit.v		ALUControlUnit.v
Adder.v		Adder.v
DFF.v		DFF.v
DataForwardingUnit.v		DataForwardingUnit.v
DataMemory32.v		DataMemory32.v
Decoder.v		Decoder.v
EX_MEM.v		EX_MEM.v
Gates.v		Gates.v
HazardDetectionUnit.v		HazardDetectionUnit.v
ID_EX.v		ID_EX.v
IF_ID.v		IF_ID.v
InstructionMemory32.v		InstructionMemory32.v
JumpConcat.v		JumpConcat.v
LeftShift.v		LeftShift.v
MEM_WB.v		MEM_WB.v
MainController.v		MainController.v
Mux.v		Mux.v
Mux32.v		Mux32.v
Mux5bit2to1.v		Mux5bit2to1.v
ProgramCounter.v		ProgramCounter.v
README.md		README.md
Reg32.v		Reg32.v
RegFile.v		RegFile.v
RegFile32.v		RegFile32.v
SignExtend.v		SignExtend.v

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