anmol109 / AMBA-AXI4-Lite Public

An implementation of AMBA AXI4Lite on an FPGA using verilog

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 78 Commits
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
test bench		test bench
.gitignore		.gitignore
AXI_lite.qpf		AXI_lite.qpf
AXI_lite.qsf		AXI_lite.qsf
AXI_lite.qws		AXI_lite.qws
AXI_lite.v		AXI_lite.v
AXI_lite.v.bak		AXI_lite.v.bak
License		License
README.md		README.md
documentation.pdf		documentation.pdf
master.v		master.v
master.v.bak		master.v.bak
master_ar.v		master_ar.v
master_ar.v.bak		master_ar.v.bak
master_slave.v		master_slave.v
master_slave.v.bak		master_slave.v.bak
read_address_ms.v		read_address_ms.v
read_address_ms.v.bak		read_address_ms.v.bak
read_data_ms - Copy.v		read_data_ms - Copy.v
read_data_ms.v		read_data_ms.v
read_data_ms.v.bak		read_data_ms.v.bak
slave1.v		slave1.v
slave1.v.bak		slave1.v.bak
slave2.v		slave2.v
stp1.stp		stp1.stp
top.v		top.v
top.v.bak		top.v.bak
top2.v		top2.v
top2.v.bak		top2.v.bak
write_address.v		write_address.v
write_address.v.bak		write_address.v.bak
write_address_master.v		write_address_master.v
write_address_master.v.bak		write_address_master.v.bak
write_address_ms.v		write_address_ms.v
write_address_ms.v.bak		write_address_ms.v.bak
write_address_slave.v		write_address_slave.v
write_address_slave.v.bak		write_address_slave.v.bak
write_data.v		write_data.v
write_data.v.bak		write_data.v.bak
write_data_ms		write_data_ms
write_data_ms.v		write_data_ms.v
write_data_ms.v.bak		write_data_ms.v.bak
write_response_ms.v		write_response_ms.v
write_response_ms.v.bak		write_response_ms.v.bak