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计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15
A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划
Collect some IC specs for learning.
Collect some CS textbooks for learning.
The official NaplesPU hardware code repository
A Fast, Low-Overhead On-chip Network
Network on Chip Implementation written in SytemVerilog
Biometric recognition system using fingerprint images for Verification and Authentication - Universidad Nacional de San Agustin (Arequipa - 2017).
128KB AXI cache (32-bit in, 256-bit out)
Simple cache design implementation in verilog
Everything we actually know about the Apple Neural Engine (ANE)
IC implementation of Systolic Array for TPU
Small-scale Tensor Processing Unit built on an FPGA
A FPGA Based CNN accelerator, following Google's TPU V1.
An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"
Convolutional accelerator kernel, target ASIC & FPGA
This is a java app that generates systolic array or NPU verilog code
hardware design of universal NPU(CNN accelerator) for various convolution neural network
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
A minimal GPU design in Verilog to learn how GPUs work from the ground up