MF8A18: MicroFPGA 8 bit engine rev A year 2018

Emulated instructions

PC unit should use 10 LUT5, 3 x CARRY4 and 10 FF and fit to 2 Slices, but it did show 25 LUT and 5 slice initially. First attempt to optimize PC unit did reduce its own resources but overall design used more LUT and more Slices then before optimization. Forcing PC unit to 2 Slices and 10 LUT5 did yield overall LUT decrease from 187 to 181 but had more slices used than initial design. One potential possible optimization found: the PC unit as re-designed used only 4 inputs of the LUT5, so one input was free in all 10 LUT and as "keep hierarchy" was set the logic from higher level was not able to merge into the LUT inside PC unit. Another bigger issue is merging of offset select multiplexer into the PC unit, keep hierarchy disables that too.

Note: 6 CARRY 4 are used because one extra CARRY4 is used as route through for the addsub unit, Xilinx optimization does not use transparent latches as route through. This CARRY4 could be optimized away also with manual ALU/addsub.

Offset selector manually merged into PC unit, now the main PC logic seems to be optimized, there are 3 extra LUT, one is inverting active low reset, the other two are used to generate freeze and carry in logic values. Next step would be to use active high reset.

Different cleanup on RTL, several times reducing logic complexity added new LUT to final design. Still some cleanup possible to reduce a few more LUT/FF.