This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
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Oct 19, 2023 - SystemVerilog
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fifo
Here are 19 public repositories matching this topic...
Repository gathering basic modules for CDC purpose
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Dec 31, 2019 - SystemVerilog
Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
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Aug 11, 2024 - SystemVerilog
Final project for the class "Application Specific Integrated Circuit Development"
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Oct 21, 2021 - SystemVerilog
Synchronous and Asynchronous FIFO with AXI interface
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Nov 20, 2019 - SystemVerilog
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
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Jun 17, 2022 - SystemVerilog
An FPGA implementation of Cummings' Asynchronous FIFO
fpga rtl verilog xilinx synthesis systemverilog fifo uvm xilinx-fpga xilinx-vivado digilent hardware-description-language nexys4ddr universal-verification-methodology fpga-programming digilent-nexys-4-board synthesizable asynchronous-fifo uvm-verification register-transistor-level
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Apr 14, 2022 - SystemVerilog
A systemverilog implementation of the data structures: priority queue, queue and stack
system stack hardware open-hardware priority-queue data-structures rtl verilog systemverilog fifo hdl system-verilog hardware-description-language
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Apr 2, 2020 - SystemVerilog
Alchitry Au FPGA Board Example Project
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Jan 12, 2024 - SystemVerilog
This Repository contains the verification of a Synchronous FIFO design using SystemVerilog and SystemVerilogAssertions
systemverilog fifo verification-methodologies verification-code digitalverification systemverilog-assertions
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Oct 7, 2024 - SystemVerilog
Verilog Codes for various Design
pipeline multiplication verilog fifo uvm adder system-verilog verilog-hdl max-pooling sequence-detector one-detector reconfigurable-matrix-adder
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Nov 24, 2023 - SystemVerilog
This Repository contains the Universal Verification Methodology (UVM) verification of a Synchronous FIFO design
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Oct 14, 2024 - SystemVerilog
A simple and configurable FIFO, designed for efficient data buffering and transfer in hardware designs
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Dec 21, 2024 - SystemVerilog
In this repository, I have published my knowledge gained while working on FIFO Project implementation using Verilog, System Verilog, UVM
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Dec 3, 2024 - SystemVerilog
This project focuses on the design and verification of FIFOs, which is essential in digital systems for managing data flow between different components.
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Aug 21, 2024 - SystemVerilog
this repo contains a uvm testbench for a fifo memory
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Nov 4, 2024 - SystemVerilog
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