risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
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🛠️ Docker image with QEMU configured for RISC-V emulation. Perfectly suited for cross-debugging RISC-V.
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Sep 10, 2023 - Dockerfile
hello world in bare-metal rust / risc-v.
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Aug 26, 2023 - Rust
Hardware implementation of floating point unit (IEEE-754 compliant) for RISC-V architecture
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Dec 20, 2019 - Bluespec
My parsec-benchmark development fork, with some tweaks.
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Feb 13, 2021 - C
🖥️ A 32-bit 5-stage scalar pipelined RISC-V processor that follows the RV32I ISA specification (ECE 411 Final Project).
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May 14, 2021 - Verilog
This docker container simplify building risc-v toolchain for Ergochip processor.
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Dec 21, 2020 - Dockerfile
Rust implementation of spike's RISC-V disassembler, spike-dasm
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Dec 1, 2020 - Rust
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Oct 7, 2023 - Rust
A collection of RISC-V assembly programs I wrote for use with RARS
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Jun 2, 2023 - Assembly