synopsys-vcs

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learn the combinational and sequential logic circuit.

simulator fpga simulation vhdl verilog iverilog ice40up5k fpga-programming synopsys-vcs synopsys-dc

RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.

digital rtl aes-128 synthesis aes-encryption digital-design verilog-project encription synopsys-vcs synopsys-dc ee4415

Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

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