SystemRDL 2.0 language compiler front-end

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

HiSilicon ip camera SoCs SystemRDL registers description

A Xtext based SystemRDL editor with syntax highlighting and context sensitive help

Generate verilog register file from systemRDL description

C++ 17 Hardware abstraction layer generator from systemrdl

VHDL generator from SystemRDL

HiSilicon SoC`s U-Boot initial register table parser into human readable format

SystemRDL language support for VS Code

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

An abstract language model of SystemRDL written in Python.

Generate BEAM (Erlang and Elixir) modules from a SystemRDL register model

SystemRDL lexer for Pygments syntax highlighting