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jtag_vpi Public
Forked from fjullien/jtag_vpiTCP/IP controlled VPI JTAG Interface.
Verilog UpdatedMar 28, 2024 -
PeakRDL-regblock Public
Forked from SystemRDL/PeakRDL-regblockGenerate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Python GNU General Public License v3.0 UpdatedMar 14, 2024 -
my_vimrc Public
🐲Jude's vimrc for DV work(fine tuning for SV/UVM)
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YASA_tui Public
A simple tui based on Textualize/textual which can show user regression cmd history and regression testcases status
Python UpdatedMay 12, 2023 -
SVA-AXI4-FVIP Public
Forked from YosysHQ-GmbH/SVA-AXI4-FVIPYosysHQ SVA AXI Properties
SystemVerilog ISC License UpdatedFeb 7, 2023 -
jobrunner Public
Forked from wwade/jobrunnerJob runner with logging
Python GNU General Public License v3.0 UpdatedAug 10, 2022 -
pypyr Public
Forked from pypyr/pypyrpypyr task-runner cli & api for automation pipelines. Automate anything by combining commands, different scripts in different languages & applications into one pipeline process.
Python Apache License 2.0 UpdatedAug 4, 2022 -
second_edition Public
Forked from advanced-uvm/second_editionCode for the second edition of Advanced UVM.
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YASA Public
🐌Yet Another Simulation Architecture
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baremetal_verification_soc_perf Public
Forked from helen20191111/baremetal_verification_soc_perfC UpdatedAug 26, 2020 -
yuu_register_productor Public
Forked from seabeam/yuu_register_productorUVM register utility generation by inputting xls table
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ExtremeDV_UVM Public
UVM resource from github, run simulation use YASAsim flow
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uvm_candy_lover Public
🍬UVM candy lover testbench which uses YASA as simulation script
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YasaUvk Public
🐛UVM verification kits which uses YASA as simulation script
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RALBot-header Public
🪲Generate C/Verilog header file from compiled SystemRDL input
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Open_RegModel Public
🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
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gitflow Public
Forked from nvie/gitflowGit extensions to provide high-level repository operations for Vincent Driessen's branching model.
Shell Other UpdatedOct 23, 2019 -
vunit Public
Forked from VUnit/vunitVUnit is a unit testing framework for VHDL/SystemVerilog
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RALBot-gen Public
Uset systemRDL to generate UVM regmodel or Verilog C use header files
Python UpdatedOct 18, 2019 -
edalize Public
Forked from olofk/edalizeAn abstraction library for interfacing EDA tools
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gnu-eprog Public
Forked from bravegnu/gnu-eprogEmbedded Programming with the GNU Toolchain
XSLT UpdatedJun 8, 2019 -
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fusesoc Public
Forked from olofk/fusesocFuseSoC is a package manager and a set of build tools for FPGA/ASIC development
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systemctlm-cosim-demo Public
Forked from Xilinx/systemctlm-cosim-demoC++ Other UpdatedMar 11, 2019 -
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sv_bfms Public
Forked from mballance/sv_bfmsSystemVerilog BFMs with bindings for UVM, etc
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UVM-1 Public
Forked from mayurkubavat/UVM-ExamplesUVM examples and projects
SystemVerilog Apache License 2.0 UpdatedJan 8, 2019 -
honcho Public
Forked from nickstenning/honchoHoncho: a python clone of Foreman. For managing Procfile-based applications.
Python MIT License UpdatedDec 18, 2018