Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This pa... more Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.
2018 IEEE International Electron Devices Meeting (IEDM), 2018
Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology nodes as... more Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology nodes as they can offer better electrostatics than FinFETs. In this paper, we show another advantage of strained Ge NW pFET over strained Ge FinFET, which lies in the preservation of Strain-Relaxed-Buffer (SRB)-induced strain through fin cut and S/D recess. This benefit comes from the presence of the sacrificial SiGe layers. Lowering the Ge concentration in the SiGe sacrificial layer is a way to further suppress the strain loss. Furthermore, a comparison of Ge NW pFETs integrated on Ge SRB and SiGe SRB reveals that SiGe SRB provides a huge advantage not only in the strain engineering but also in IOFF control. These are key enablers in maximizing the performance while minimizing the IOFF of strained Ge NW pFETs.
2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2021
We report on nanosheet (NS) FETs as promising candidates to replace finFETs and continue deliveri... more We report on nanosheet (NS) FETs as promising candidates to replace finFETs and continue delivering profitable node to node scaling gains. Key fabrication challenges addressed here include device parasitics' reduction via inner spacers integration and channels' stress control. Further scaling options may involve evolution into a forksheet (FS) type of configuration with shrunk p-n spacing, and/or stacking of different polarity devices into a single 3D structure. Lastly, by fully exploring the third dimension, vertical NS (VNS) FETs are also considered for applications such as the selector of ultra-scaled MRAM cells.
For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects... more For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1-μm and 70-nm gate lengths. Hole mobility at 1-μm gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.
2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM), 2014
ABSTRACT S/D epitaxial layers and SRBs are the most effective stressors in scaled FinFETs. While ... more ABSTRACT S/D epitaxial layers and SRBs are the most effective stressors in scaled FinFETs. While S/D stressors are well established, for SRBs the remaining technical difficulties are significant. However, its expected performance boost and enhanced scalability makes developing SRBs worthwhile, especially when combined with alternative channel materials.
ABSTRACT Calculations of stress enhanced mobilities are performed for n- and p-FinFETs with both ... more ABSTRACT Calculations of stress enhanced mobilities are performed for n- and p-FinFETs with both Si and Ge channels for the 14 nm node and beyond. Relaxed Ge p-FinFETs and even Ge with a GeSn5% source / drain stressor cannot outperform strained Si. However, growing the Ge channel strained on a SiGe75% strain relaxed buffer (SRB) provides a 49% mobility boost over strained Si. For Si n-FinFETs, SRB mobility boost is also possible, with Si on a SiGe 25% SRB improving mobility by 83%. Addition of a Si:C 2% S/D stressor increases that benefit to 109%. For Ge n-FinFETs, relaxed channels outperform strained Si by 120%, owing primarily to the 6× increase in fin sidewall mobility. Adding a SiGe 75% S/D stressor increases that benefit to 210%. In general, the SRB stressors have excellent scalability to future nodes. TCAD trends are qualitatively confirmed by Nano-Beam Diffraction.
ABSTRACT Novel device architectures offer improved scalability but come often at the price of inc... more ABSTRACT Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1-yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1-yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.
2006 International Conference on Advanced Semiconductor Devices and Microsystems, 2006
ABSTRACT The paper reports the simultaneous improvement of both on- and off-properties for nMOSFE... more ABSTRACT The paper reports the simultaneous improvement of both on- and off-properties for nMOSFETs by means of fluorineine co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with fluorineine co-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted and C co-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (REXT) vs. effective channel length (Leff) trade-off are examined
A CMOS ring oscillator circuit is observed to operate even after a number of its FET&... more A CMOS ring oscillator circuit is observed to operate even after a number of its FET's have undergone a hard gate oxide breakdown. The first breakdown is identified with emission microscopy and statistical tools to most likely occur in the circuit's nFET's. A physical ...
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This pa... more Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.
2018 IEEE International Electron Devices Meeting (IEDM), 2018
Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology nodes as... more Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology nodes as they can offer better electrostatics than FinFETs. In this paper, we show another advantage of strained Ge NW pFET over strained Ge FinFET, which lies in the preservation of Strain-Relaxed-Buffer (SRB)-induced strain through fin cut and S/D recess. This benefit comes from the presence of the sacrificial SiGe layers. Lowering the Ge concentration in the SiGe sacrificial layer is a way to further suppress the strain loss. Furthermore, a comparison of Ge NW pFETs integrated on Ge SRB and SiGe SRB reveals that SiGe SRB provides a huge advantage not only in the strain engineering but also in IOFF control. These are key enablers in maximizing the performance while minimizing the IOFF of strained Ge NW pFETs.
2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2021
We report on nanosheet (NS) FETs as promising candidates to replace finFETs and continue deliveri... more We report on nanosheet (NS) FETs as promising candidates to replace finFETs and continue delivering profitable node to node scaling gains. Key fabrication challenges addressed here include device parasitics' reduction via inner spacers integration and channels' stress control. Further scaling options may involve evolution into a forksheet (FS) type of configuration with shrunk p-n spacing, and/or stacking of different polarity devices into a single 3D structure. Lastly, by fully exploring the third dimension, vertical NS (VNS) FETs are also considered for applications such as the selector of ultra-scaled MRAM cells.
For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects... more For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1-μm and 70-nm gate lengths. Hole mobility at 1-μm gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.
2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM), 2014
ABSTRACT S/D epitaxial layers and SRBs are the most effective stressors in scaled FinFETs. While ... more ABSTRACT S/D epitaxial layers and SRBs are the most effective stressors in scaled FinFETs. While S/D stressors are well established, for SRBs the remaining technical difficulties are significant. However, its expected performance boost and enhanced scalability makes developing SRBs worthwhile, especially when combined with alternative channel materials.
ABSTRACT Calculations of stress enhanced mobilities are performed for n- and p-FinFETs with both ... more ABSTRACT Calculations of stress enhanced mobilities are performed for n- and p-FinFETs with both Si and Ge channels for the 14 nm node and beyond. Relaxed Ge p-FinFETs and even Ge with a GeSn5% source / drain stressor cannot outperform strained Si. However, growing the Ge channel strained on a SiGe75% strain relaxed buffer (SRB) provides a 49% mobility boost over strained Si. For Si n-FinFETs, SRB mobility boost is also possible, with Si on a SiGe 25% SRB improving mobility by 83%. Addition of a Si:C 2% S/D stressor increases that benefit to 109%. For Ge n-FinFETs, relaxed channels outperform strained Si by 120%, owing primarily to the 6× increase in fin sidewall mobility. Adding a SiGe 75% S/D stressor increases that benefit to 210%. In general, the SRB stressors have excellent scalability to future nodes. TCAD trends are qualitatively confirmed by Nano-Beam Diffraction.
ABSTRACT Novel device architectures offer improved scalability but come often at the price of inc... more ABSTRACT Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1-yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1-yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.
2006 International Conference on Advanced Semiconductor Devices and Microsystems, 2006
ABSTRACT The paper reports the simultaneous improvement of both on- and off-properties for nMOSFE... more ABSTRACT The paper reports the simultaneous improvement of both on- and off-properties for nMOSFETs by means of fluorineine co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with fluorineine co-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted and C co-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (REXT) vs. effective channel length (Leff) trade-off are examined
A CMOS ring oscillator circuit is observed to operate even after a number of its FET&... more A CMOS ring oscillator circuit is observed to operate even after a number of its FET's have undergone a hard gate oxide breakdown. The first breakdown is identified with emission microscopy and statistical tools to most likely occur in the circuit's nFET's. A physical ...
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Papers by A. Keersgieter