PT/LDD

... a , Corresponding Author Contact Information , 1 , E-mail The Corresponding Author , BJ Pawlak b , S. Kubicek a , T. Hoffmann a , T. Chiarella a , C. Kerner a , S. Severi a , A. Falepin a , 2 , J. Ramos a , 3 , A. De Keersgieter a , P. Eyben a , D. Vanhaeren a , W. Vandervorst a , M ...

ABSTRACT Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and reduced or changed effectiveness of stressors. This work focuses on stress effects in n-type FinFETs with gate-first or gate-last stacks, and relies mainly on TCAD results. On n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. CESL becomes very ineffective for layouts with narrow fin pitches with merged fins: about 3 times lower mobility increase is predicted than for isolated fins. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. Si:C source/drain stressors are very effective and show similar width dependence as on planar FETs. Significant mobility enhancement is predicted both in isolated and tight-pitch/merged fin configurations.

This paper shows, for the first time, the successful introduction of recessed, strained Si0.8Ge0.2 in the source and drain regions of pMOS MuGFET devices, improving the on-state current of these devices by 25%, at a fixed off-state condition. The improvement is shown to be a combined effect of compressive stress introduced along the channel, and of a reduced series resistance.

ABSTRACT A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4F2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.

Channel hot-carrier (CHC) degradation in nMOS transistors is studied for different SiO2/HfSiON dielectric stacks and compared to SiO2. We show that, independent of the gate dielectric, in short-channel transistors, the substrate current peak (used as a measure for the highest degradation) is at VG = VD, whereas for longer channels, the maximum peak is near VG = VD/2. We demonstrate that this shift in the most damaging CHC condition is not caused by the presence of the high- k layer but by short-channel effects. Furthermore, the CHC lifetime of short-channel transistors was evaluated at the most damaging condition VG = VD, revealing sufficient reliability and even larger operating voltages for the high-k stacks than for the SiO2 reference.

Abstract A method to determine the breakdown position in short channel nMOSFETs is introduced. We find that soft breakdown occurs exclusively in the transistor channel, while the hardest circuit-killing breakdowns occur above the source and drain extension regions ...