ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D NAND Flash memory is successfully developed. It achieves minimum cell area (4F2) without the need for pipeline connections. We introduced a... more
ABSTRACT A new vertical cylindrical cell with 25nm diameter bi layer poly-silicon channel for 3D NAND Flash memory is successfully developed. It achieves minimum cell area (4F2) without the need for pipeline connections. We introduced a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This additional silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole. The smallest working cells have been fabricated with feature size F down to 45 nm corresponding to an equivalent 11nm planar cell technology node for the case of 16 stacked cells.
... 3J). Understanding the gate-to-channel BD is more complex. ... The BD spot acts as an additional drain of two narrow FETs with gates G and sources at S and D, respectively [4]. VD influ-ences the electric field at the BD spot, and... more
... 3J). Understanding the gate-to-channel BD is more complex. ... The BD spot acts as an additional drain of two narrow FETs with gates G and sources at S and D, respectively [4]. VD influ-ences the electric field at the BD spot, and therefore affects the FET characteristics (Fig 3h). ...
ABSTRACT FinFETs are being considered as an attractive alternative to enable further CMOS Scaling. In this paper, a device scaling model for the electrostatics of bulk FinFETs is presented. Device parameters such as subthreshold slope... more
ABSTRACT FinFETs are being considered as an attractive alternative to enable further CMOS Scaling. In this paper, a device scaling model for the electrostatics of bulk FinFETs is presented. Device parameters such as subthreshold slope (SS), threshold voltage (Vth), off-state current (IOFF)> drain-induced-barrier lowering (DIBL) are modeled showing good agreement with TCAD and experimental results. Besides predicting the effects of technology scaling, this model provides good insight in terms of device design. By accounting for the effects of fin geometry variation and the drain voltage (Vd) on the effective fin doping (Na(ef)), the present work is very useful in determining Na(ff)) for low Vth, standard Vth and high Vth applications. Based on this model, it is also possible to determine the geometrical parameters required to achieve SS = 80 mV/dec, DIBL = 50 mV/V.
In this paper, the suitability of the MUGFET technology as an alternative device architecture for 32 nm CMOS generation is discussed. In particular, the requirements for the MUGFET devices with focus on FIN geometry, gate stack, and... more
In this paper, the suitability of the MUGFET technology as an alternative device architecture for 32 nm CMOS generation is discussed. In particular, the requirements for the MUGFET devices with focus on FIN geometry, gate stack, and junctions are analyzed. Technological challenges related to the processing of MUGFET devices such as, FIN and gate patterning, junctions and spacer formation, are
We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled... more
We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of
ABSTRACT As CMOS technology goes into the nanoscale regime, the impact of layout on the device performance becomes increasingly important. In this paper, we propose a physics-based analytical model for Layout Dependent Effects (LDE) due... more
ABSTRACT As CMOS technology goes into the nanoscale regime, the impact of layout on the device performance becomes increasingly important. In this paper, we propose a physics-based analytical model for Layout Dependent Effects (LDE) due to shallow trench isolation (STI) stress in 28 nm technology using “gate-last” process (Replacement Gate - RMG). The impact of active size and active width are considered and the model links between stress and device parameters such as the mobility and threshold voltage. The model is validated with experimental data. In addition, we investigate the impact of embedded Silicon-Germanium source/drain (eSiGe S/D) stressors in PMOS. Stronger mobility degradation is predicted for small width devices once eSiGe S/D is used. It results in a larger drop of normalized current (μA/μm) (-16%) once compared to transistors without eSiGe (-7%).
Doping Fig. 1: Simulated Fin structures (Fin width=20nm/Fin height=55nm) with Lgate=35nm used for device simulation. Conformal SDE junction (Xj=5nm, overlap=4nm) is compared with standard ion implant doping distribution (top active... more
Doping Fig. 1: Simulated Fin structures (Fin width=20nm/Fin height=55nm) with Lgate=35nm used for device simulation. Conformal SDE junction (Xj=5nm, overlap=4nm) is compared with standard ion implant doping distribution (top active doping=5x1020/cm3).
Optimum device design for high performance applications has been investigated assuming a fixed oxide thickness of 2.5nm and supply voltage of 1.5V. The optimal performance is achieved by minimizing parasitic effects. The influence of... more
Optimum device design for high performance applications has been investigated assuming a fixed oxide thickness of 2.5nm and supply voltage of 1.5V. The optimal performance is achieved by minimizing parasitic effects. The influence of experimental splits in source/drain (S/D) ...
ABSTRACT In this work, we propose a new triple junction approach for aggressively scaled CMOS transistors. It is formed by means of conventional ion implantation in three phases: before offset spacer (LDD), after offset spacer (MDD) and... more
ABSTRACT In this work, we propose a new triple junction approach for aggressively scaled CMOS transistors. It is formed by means of conventional ion implantation in three phases: before offset spacer (LDD), after offset spacer (MDD) and after second spacers (HDD). We demonstrate that the triple junction has great potential in reducing significantly the variation of the device parameters such as drive current, off-state current, and overlap capacitance, originating from the non-uniformity of the offset spacer commonly used in CMOS devices below the 90 nm node.
ABSTRACT Unexpected gate oxide failure has been observed during HBM ESD stress on high-voltage tolerant nLDMOS-SCR devices in standard low-voltage CMOS technology. TCAD simulations show that this early gate-oxide failure is due to high... more
ABSTRACT Unexpected gate oxide failure has been observed during HBM ESD stress on high-voltage tolerant nLDMOS-SCR devices in standard low-voltage CMOS technology. TCAD simulations show that this early gate-oxide failure is due to high current injection originating from the additional discharge current of the inherent HBM board capacitance.
The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures... more
The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins
Channel hot-carrier (CHC) degradation in short channel transistors with a high-k gate stack processed in CMOS technology has been analysed. For short channel transistors (L < 0.15mum), the most... more
Channel hot-carrier (CHC) degradation in short channel transistors with a high-k gate stack processed in CMOS technology has been analysed. For short channel transistors (L < 0.15mum), the most damaging stress condition has been found to be VG = VD instead of the "classical" VG = VD/2 for long channel transistors. In this work, we have demonstrated that this shift
In this study we demonstrate the capabilities of scanning spreading resistance microscopy (SSRM), which is an atomic force microscope based technique, for two-dimensional (2D) carrier profiling with nanometer spatial resolution, high... more
In this study we demonstrate the capabilities of scanning spreading resistance microscopy (SSRM), which is an atomic force microscope based technique, for two-dimensional (2D) carrier profiling with nanometer spatial resolution, high quantification accuracy, and high ...
