Circuit Design

In this paper we report the extent to which dielectric relaxation in typical monolithic capacitors degrades the performance of chargemedistrihution analog-to-digital (A/D) converters, We show experimental device data from a monolithic capacitor test circuit, describe an empirical capacitor model fit to the rneasnrements, and compare simulated A/D system errors with those observed in a monolithic, 10-b, 3.3m&s A/D converter. The excellent agreement found in this comparison demonstrates that the transient error in A/D-converter code transition voltages due to dielectric relaxation may be accurately predicted. The modeling and simulation techniques discussed are important tools both for the selection of proper capacitor technology and iu the development of circuit designs insensitive to dielectric relaxation. This analysis is also applicable to any circnit where precision is derived from capacitor characteristics, such as sample-and-hold circuits aud switchedcapacitor filters.

In this paper a novel rail-to-rail fully differential operational transconductance amplifier (OTA) working at low- supply voltages (1.5 V) with reduced consumption and showing high DC gain is presented. An adaptive biasing circuit allows to obtain low stand-by power dissipation (lower than 0.19 mW in the rail-to-rail version), while the high DC gain (over 80 dB) is ensured by a positive feedback. The circuit, designed in a standard CMOS integrated technology (AMS 0.35 mum), has a 40 V/mus slew-rate for a capacitive load of 15 pF. The calculated values of two quality factors, named FOMS/L, in the literature, show the validity of the proposed OTA.

and the Electrical Engineering Department of the Arizona State University, in Tempe, and he serves as its Director. His research interests include design automation, verification, and testing of digital systems. His teaching experience includes undergraduate and graduate courses in digital systems design and testing, CMOS VLSI design, VLSI physical design, synthesis and formal verification, and discrete mathematics.

The increasing complexity of circuit design needs to be managed with appropriate optimization algorithms and accurate statistical description of design models in order to reach the design specifics, guaranteeing ''zero defects''. In the Design for Yield open problems are the design of effective optimization algorithms and statistical analysis for yield design, which require time consuming techniques. New methods have to balance accuracy, robustness and computational effort. Typical analog integrated circuit optimization problems are computationally hard and require the handling of multiple, conflicting, and non-commensurate objectives having strong nonlinear interdependence. This paper tackles the problem by evolutionary algorithms to produce tradeoff solutions on the Pareto Front. In this research work Integrated Circuit (IC) design has been formulated as a constrained multi-objective optimization problem defined in a mixed integer/discrete/continuous domain. The following real-life circuits, RF Low Noise Amplifier, Leapfrog Filter, and Ultra Wideband LNA, were selected as test bed. The proposed algorithm, A-NSGAII, was shown to produce acceptable and robust solutions in the tested applications, where state-of-art algorithms and circuit designers failed. The results show significant improvement in all the chosen IC design problems.

With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice, the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. A chain of 1000 ADL inverters has been constructed in 0.9 pm CMOS and successfully tested at 250 MHz. This result, together with comprehensive circuit simulation, suggest that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry.

We investigate hot-carrier degradation of the 1 -noise behavior of n-and p-MOS transistors under typical bias conditions for analog and RF operation. The mechanisms responsible for the degradation and a model are discussed for both n-and p-MOS devices. A method for lifetime prediction concerning 1 -noise degradation is presented and consequences for reliability assurance by measures of circuit design are drawn. Index Terms-1 -noise, analog, flicker noise, hot carrier, MOS, MOSFET, noise, RF.

Modeling and analyzing detailed die temperature with a full-chip thermal model at early design stages is important to discover and avoid potential thermal hazards. However, omitting important aspects of package details in a thermal model can result in significant temperature estimation errors. In this paper, we discuss the applications of an existing compact thermal model that models both die and package temperature details. As an example, a thermally selfconsistent leakage power calculation of a POWER4-like microprocessor design is presented. We then demonstrate the importance of including detailed package information in the thermal model by several examples considering the impact of thermal interface material (TIM), which glues the die to the heat spreader. The fact that detailed package information is needed to build an accurate compact thermal model implies a design flow, in which the chip-and package-level compact thermal model acts as a convenient medium for more productive collaborations among circuit designers, computer architects and package designers, leading to early and efficient evaluations of different design tradeoffs for an optimal design from a thermal point of view.

In this paper, the Simulated Evolution algorithm (SimE) is engineered to solve the optimization problem of multi-objective VLSI netlist bi-partitioning. The multi-objective version of the problem is addressed in which, power dissipation, timing performance, as well as cut-set are optimized while Balance is taken as a constraint. Fuzzy rules are used in order to design the overall multiobjective cost function that integrates the costs of three objectives in a single overall cost value. Fuzzy goodness functions are designed for delay and power, and proved efficient. A series of experiments are performed to evaluate the efficiency of the algorithm. ISCAS-85/89 benchmark circuits are used and experimental results are reported and compared to earlier algorithms like GA and TS.

Fault simulation is commonly used in the development or evaluation of test vectors for integrated circuit designs. The computational requirements, however, often discourage, or even prohibit, complete fault simulation of circuit designs having greater than 20000 single stuck-at faults. To circumvent this problem, statistical sampling methods have been proposed [l], [2] that provide fault coverage values within a small, predictable error range by simulating only a fraction of the circuit's total faults and using the result fault coverage value as an estimate of the fault coverage for the total circuit. Since only a fraction of the stuck-at faults are used in the simulation, it requires but a fraction of the time required for complete fault simulation. As an introduction to the application of sampling methods to fault simulation of integrated circuits, the statistical theory behind these sampling methods and proposed augmentations of these methods for improving the precision of the sample fault coverage is presented. Various proposed sampling schemes are applied to example circuit designs, and the results are analyzed.

We present for the first time, a fully integrated battery powered RFID integrated circuit (IC) for operation at ultrahigh frequency (UHF) and microwave bands. The battery powered RFID IC can also work as a passive RFID tag without a battery or when the battery has died (i.e., voltage has dropped below 1.3 V); this novel dual passive and battery operation allays one of the major drawbacks of currently available active tags, namely that the tag cannot be used once the battery has died. When powered by a battery, the current consumption is 700 nA at 1.5 V (400 nA if internal signals are not brought out on testpads). This ultra-low-power consumption permits the use of a very small capacity battery of 100 mA hr for lifetimes exceeding ten years; as a result a battery tag that is very close to a passive tag both in form factor and cost is made possible. The chip is built on a 1m digital CMOS process with dual poly layers, EEPROM and Schottky diodes. The RF threshold power at 2.45 GHz is -19 dBm which is the lowest ever reported threshold power for RFID tags and has a range exceeding 3.5 m under FCC unlicensed operation at the 2.4-GHz microwave band. The low threshold is achieved with architectural choices and low-power circuit design techniques. At 915 MHz, based on the experimentally measured tag impedance (92-j837) and the threshold spec of the tag (200 mV), the theoretical minimum range is 24 m. The tag initially is in a "low-power" mode to conserve power and when issued the appropriate command, it operates in "full-power" mode. The chip has on-chip voltage regulators, clock and data recovery circuits, EEPROM and a digital state machine that implements the ISO 18000-4 B protocol in the "full-power" mode. We provide detailed explanation of the clock recovery circuits and the implementation of the binary sort algorithm, which includes a pseudorandom number generator. Other than the antenna board and a battery, no external components are used.

This paper emphasizes concurrent consideration of the partitioning of a microelectronic circuit design into multiple dies and the selection of the appropriate packaging technology for implementation of the entire system. Partitioning a large design into a multichip package is a non-trivial task. Similarly, selection of the MCM packaging technology to accommodate a multichip solution can also be puzzling. The interdependencies

Verbmobil, a German research project, aims at machine translation of spontaneous speech input. The ultimate goal is the development of a portable machine translator that will allow people to negotiate in their native language. Within this project the University of Karlsruhe has developed a speech recognition engine that has been evaluated on a yearly basis during the project and shows very promising speech recognition word accuracy results on large vocabulary spontaneous speech. We introduce the Janus Speech Recognition Toolkit underlying the speech recognizer. The main new contributions to the acoustic modeling part of our 1996 evaluation system-speaker normalization, channel normalization and polyphonic clustering-are discussed and evaluated. Besides the acoustic models we delineate the different language models used in our evaluation system: word trigram models interpolated with class based models and a separate spelling language model were applied. As a result of using the toolk...

A microprocessor implementing IBM S/390 architecture operates in a 10 + 2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-m L e CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm 2 17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units (IU's), two fixed point units (FXU's), two floating point units (FPU's), a buffer control element (BCE) with a unified 64-KB L1 cache, and a register unit (RU). The microprocessor dispatches one instruction per cycle. The dual-instruction, fixed, and floating point units are used to check each other to increase reliability and not for improved performance. A phase-locked-loop (PLL) provides a processor clock that runs at 22 the system bus frequency. High-frequency operation was achieved through careful static circuit design and timing optimization, along with limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. Timing-driven synthesis and placement of the control logic provided the maximum flexibility with minimum turnaround time. Extensive use of self-resetting CMOS (SRCMOS) circuits in the on-chip L1 cache provides a 2.0-ns access time and up to 500 MHz operation.

EKV3 is a circuit-design-oriented compact MOSFET model for analog/RF IC design. The paper presents parameter extraction guidelines and modelling using EKV3 for TOSHIBA's 90nm RF-CMOS technology covering DC, CV and RF (S-parameter) and temperature scalability. RF verification was done by the use of multi-finger MOSFETs with many variations of gate length, width of unit fingers and number of fingers. A scalable RF model was successfully created. Extraction of RF parasitics and their scaling with RF layout is investigated. The EKV3 model successfully predicted high-frequency behaviour of 90nm CMOS up to 20GHz over a wide range of bias conditions. 74

This paper discusses design issues and the microwave properties of CMOS devices. A qualitative understanding of the microwave characteristics of MOS transistors is provided. The paper is directed toward helping analog IC circuit designers create better front-end radio-frequency CMOS circuits. The network properties of CMOS devices, the frequency response, and the microwave noise properties are reviewed, and a summary of the microwave scaling rules are presented.

A new design of a hysteresis chaotic circuit is proposed. The simple circuit consists of one capacitor, one inductor, one resistor (negative) and one hysteresis VCVS. Computer simulation results, showing the existence of the double scroll attractor, are reported.

A current source for neural stimulation is presented which converts arbitrary voltage signals to currentcontrolled signals while regulating the offset-voltage across the stimulation electrodes in order to keep the electrodes in an electrochemical state that allows for injecting a maximum charge. The offset-voltage can either be set to 0 V or to a bias-voltage, e.g. of a few 100 mV, as it can be advantageous for fully exploiting the charge injection capacity of iridium oxide electrodes.

This paper describes the measurement method and experimental technique with advanced instrumentation setup for analysing the metastability behavior and performance measurement of flip-flops used in programmable logic devices. In order to demonstrate this testing approach, the results for metastable characteristics parameters of one FPGA digital circuit fabricated commercially in 90 nm CMOS process are presented. The same test methods can also be used for evaluation of timing reliability in digital circuits as well.

Geometric programming (GP) has been employed in automatic design of analog integrated circuits. Its major advantage is the ability to find the globally optimum solution to a problem. It however, suffers from dependency on the accuracy of the initial equations and the parameters used in these equations. This, in circuit design, causes discrepancies between GP predictions and simulation results-especially in sub-micron devices-thus resulting in a non-globally optimum circuit design. In this paper, two major sources of this discrepancy are introduced and resolved by an iterative simulation-equation-based design methodology based on GP for operational amplifiers. In order to show the effectiveness of the methodology, it has been applied to two op-amp architectures.

This paper characterizes the potentially catastrophic effect of crosstalk glitches on representative circuit implementations of two widely used asynchronous protocols. It is demonstrated that the crosstalk glitches can induce false events, which can undesirably propagate into asynchronous interface circuits and may cause system failure. Conventionally, to a circuit designer, glitch propagation (GP) due to aggressor-to-quiet-line crosstalk (AQX) in asynchronous handshake schemes can only be observed through circuit-level analysis/simulation. In this paper, circuit-level analysis is first performed to prove that even optimized conventional asynchronous circuits allow crosstalk glitches produced over moderate-length interconnects (1.5 mm) to propagate. This is a precursor to a more problematic crosstalk glitch occurrence due to further scaling of technologies. To warn the digital designers from GP due to AQX, a novel modeling technique is proposed. This modeling method works at the logic level to facilitate asserting asynchronous interface robustness to crosstalk glitches. This model can accurately identify the possibility of intrinsic (to the asynchronous interface) crosstalk GP in asynchronous circuits at the logic level and, hence, provides a foundation to formally verify such circuits. To our knowledge, this is the first work on modeling GP due to AQX at the logic level for asynchronous circuits.

As CMOS technology scaling is advancing beyond 100 nm, it has become increasingly difficult to meet the power and performance goals for various product applications while achieving aggressive area scaling in static random access memory (SRAM) development. This paper addresses many of the most pressing challenges in today's SRAM design from perspectives of both process technology optimization and design innovation. Key process tradeoff and optimization along with the advanced circuit design techniques for power management and low-voltage operation are discussed.

It is known that circuit delays and timing skews in input vector changes influence choice of tests to detect delay faults. Tests for stuck-open faults in CMOS logic circuits can also be invalidated by circuit delays and timing skews in input vector changes. Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. In this paper we propose an integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests. We also demonstrate that the proposed method guarantees the design of CMOS logic circuits in which all path delay faults are locatable.

The Switched reluctance Motor (SRM) is an old member of the Electric Machines Family. Its simple structure, ruggedness and inexpensive manufacturing capability make it more attractive for Industrial applications. However these merits are overshadowed by its inherent high torque ripple, acoustic noise and difficulty to control. In this work Design, modeling, simulation and analysis of Switched Reluctance motor has been done. Various models of Switched reluctance Motor Linear and nonlinear model with different control strategies are simulated in MATLAB/SIMULINK. The control strategies used are PI Control, Hysteresis Control and voltage control. The result obtained from simulation has been verified practically. The control signal and circuit design for operation of a Switched Reluctance Motor (SRM) drive has been described. The control circuit has been realized using microcomputer system. The technique developed is suitable for implementation with recent DSP processors. The result obta...

Schmitt trigger design with given circuit thresholds is described. The approach is based on studying the transient from one stable state to another when the trigger is in linear operation. The trigger is subdivided into two subcircuits; each of them is considered as a passive load for the other. This allows the relations governing the deviations of the circuit thresholds from their given values to be obtained. The trigger device sizes are thus determined by the threshold tolerances.

This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered. The analog building blocks can roughly be divided into two subgroups: the switched-capacitor and the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected. Next, the CAD tool development for analog CMOS is discussed, showing that there is still a lot to be done in the field of automated analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more general sense are described.

CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. Carbon Nanotube Field Effect Transistor (CNTFET) is a very promising and superior technology for its applications to circuit design. In this paper we intend to evaluate and compare the performance parameters of a traditional 6T SRAM cell between a predictive 16nm Complementary Metal Oxide Semiconductor (CMOS) technology and CNTFET.

In this article, the large-signal, small-signal, and noise performance of the Cherry-Hooper amplifier with emitter-follower feedback are analyzed from a design perspective. A method for choosing the component values to obtain a low group delay distortion or Bessel transfer function is given. The design theory is illustrated with an implementation of the circuit in a 47-GHz SiGe process. The amplifier has 19.7-dB gain, 13.7-GHz bandwidth, and 10-ps group delay distortion. The amplifier core consumes 34 mW from a 3.3-V supply.

Semiconductor manufacturing industry is moving into the production of 300-mm wafers. To solve the increased workload problem in manual wafer handling, some personal guided vehicles (PGVs) have been developed to help in the transfer of Front Opening Unified Pods (FOUP). This study compares two kinds of PGVs with a traditional cart and evaluates the feasibility of using them for manual FOUP handling tasks. Manual FOUP handling capability was assessed. The results indicate that there is no obvious advantage in using any of the two evaluated PGVs over the manual cart. There is potential risk of causing musculoskeletal disorders for female operators to handle the 300 mm FOUP manually. Since the development of a fully automated intra-bay FOUP handling system is a project of high technical difficulty, a combination of manual and automated handling is the current approach. To enhance the operator's health, safety and productivity, selection and training of operators, adequate design of handling tools and machine interface, assessment and balancing of workload are necessary.

Mine hoists and elevators have experienced accidents with the potential for injuring or killing numerous miners. These accidents occurred on counterweighted hoisting systems when the mechanical brake failed while the cage was empty. This allowed the counterweight to fall to the bottom of the shaft, causing the cage to overspeed and crash into the headframe. Direct-current hoist motors have the potential for preventing this type of accident by incorporating a passive electrical braking system known as dynamic braking. Installation of dynamic braking required minimal control-system modifications and modest expense. The various circuit designs that can be configured to implement dynamic braking on a dc mine hoisting system are discussed. Selection of the load resistance for the desired dynamic braking system performance will be addressed. In addition, analysis of data obtained from tests conducted on a mine hoisting system, which was modified in the field to incorporate dynamic braking, will be discussed to provide technical credibility to the dynamic braking concept.

Abstnrct-CMOS Schmitt trigger design with given circuit thresholds is described. The approach is based on studying the transient from one stable state to another when the trigger is in linear operation. The trigger is subdivided into two subcircuits; each of them is considered as a passive load for the other. This allows the relations governing the deviations of the circuit thresholds from their given values to be obtained. The trigger device sizes are thus determined by the threshold tolerances.

This paper surveys the design of embedded computer systems, which use software running on programmable computers to implement system functions. Creating an embedded computer system which meets its performance, cost, and design time goals is a hardware-software co-design p r o b l e w h e design of the hardware and software components influence each other. This paper emphasizes a historical approach to show the relationships between well-understood design problems and the as-yet unsolved problems in co-design. We describe the relationship between hardware and sofhvare architecture in the early stages of embedded system design. We describe analysis techniques for hardware and software relevant to the architectural choices required for hardware-software co-design. We also describe design and synthesis techniques for co-design and related problems.

this paper reports a PFD/CP linearization technique and a new charge pump circuit to enhance the performance of a delta-sigma (∆Σ) fractional-N PLL. The proposed method improves the PLL linearity by forcing the PFD/CP to operate in a linear part of its transfer characteristic; while the CP circuit minimizes the current mismatch between the up and down currents by feedback. These circuit techniques are employed in the design of a 2.4-GHz ∆Σ fractional-N PLL. This chip has been fabricated in the TSMC 0.18-µm CMOS process. The experimental results demonstrate that the proposed techniques considerably improve the fractional-N PLL performance. This fully-integrated PLL dissipate 22 mW under a 1.8-V supply.

A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock phases. In order to verify the functionality of the proposed device, some physical proofs are provided. The proper functionality of the FA is checked by means of computer simulations using QCADesigner tool. Both simulation results and physical relations confirm our claims and its usefulness in designing every digital circuit.

The 16-way set associative, single-ported 16-MB cache for the Dual-Core Intel Xeon Processor 7100 Series uses a 0.624 m 2 cell in a 65-nm 8-metal technology. Low power techniques are implemented in the L3 cache to minimize both leakage and dynamic power. Sleep transistors are used in the SRAM array and peripherals, reducing the cache leakage by more than 2X. Only 0.8% of the cache is powered up for a cache access. Dynamic cache line disable (Intel Cache Safe Technology) with a history buffer protects the cache from latent defects and infant mortality failures.

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model. Index Terms-Circuit modeling, integrated circuit design, MOS analog integrated circuits, MOS devices.

Due to the quadratic reduction in the switching power dissipation, lowering supply voltage is obviously one of the most e ective ways to reduce p ower consumption. However, the performance will degrade. In order to satisfy the high performance r equirements, threshold voltage has to be s c aled. Unfortunately, such scaling leads to a dramatic increase in leakage current, which becomes a new concern for low voltage and high performance circuit designs. Multiple transistor threshold and supply voltages can be used to achieve low power and high performance while maintaining low leakage current. In this tutorial, di erent multiple-V th , multiple-V dd and standby leakage control techniques are presented.

A new algorithm is developed which transforms the truth table or implicant table of a Boolean function into a canonical form under any permutation of inputs. The algorithm is used for Boolean matching for large libraries that contain cells with large numbers of inputs and implicants. The minimum cost canonical form is used as a unique identifier for searching for the cell in the library. The search time is nearly constant if a hash table is used for storing the cells' canonical representations in the library. Experimental results on more than 100 000 gates confirm the validity and feasible runtime of the algorithm.

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, without involving formal design procedures. Hence, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented. This new cell can reliably operate within certain bounds when the power supply voltage is scaled down, as long as due consideration is given to the sizing of the MOS transistors during the initial design step. A low transistor count full adder cell using the new XOR-XNOR cell is also presented.

An improved full-bridge ZVS PWM using a twoinductor rectifier dddc converter is presented in this paper. For this improved topology, the main devices are switched on under zero-voltage (ZVS) conditions using the energy stored in the secondary filter inductors. In addition, it utilizes the low leakage inductance of a coaxial winding transformer to reset the currents in the rectifier diodes and eliminate the secondary voltage spike. The two-inductor rectifier has only one diode conduction drop in addition to frequency doubling in the output capacitor. The secondary filter size in the proposed topology is rather small. The advantages of the new topology include a wide loa d range with ZVS, no lost duty cycle due to diode recovery, no secondary voltage spikes, in addition to high power density and high efficiency.

In this paper, we propose a new approach to thermometer-to-binary encoder of Flash ADCs. Instead of integrating bubble error correction circuit as previous approaches, proposed approach integrates a bubble error detection circuit. The advantage of this approach is that it can handle all types of bubble error whereas previous approaches often deal with first-order bubble error only. Simulation results show that the bubble error detection circuit consumes very little energy.