Microwave CMOS-device physics and design

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999 277 Microwave CMOS—Device Physics and Design Tajinder Manku, Member, IEEE Abstract—This paper discusses design issues and the microwave properties of CMOS devices. A qualitative understanding of the microwave characteristics of MOS transistors is provided. The paper is directed toward helping analog IC circuit designers create better front-end radio-frequency CMOS circuits. The network properties of CMOS devices, the frequency response, and the microwave noise properties are reviewed, and a summary of the microwave scaling rules are presented. Index Terms—CMOS, microwave CMOS, radio frequency, RF MOSFET design. I. INTRODUCTION T HE majority of radio-frequency (RF) integrated circuits (IC’s) are typically implemented in GaAs or silicon bipolar technologies [1], [2]. Bipolar junction transistors (BJT’s) and GaAs devices have historically been used for high-speed applications because of their relatively high unity-gain cutoff frequency ( ). However, advances in CMOS processing technology have continued to reduce the minimum channel of the length of the MOS device, thereby increasing the transistor [3]–[7]. For example, with a deep submicrometer CMOS technology, devices with ’s exceeding 100 GHz and minimum noise figures less than 0.5 dB at 2 GHz have been realized, as shown in Fig. 1. Because of these relatively high values, CMOS is becoming a viable technology choice for RF integrated components for the wireless communication market. Furthermore, as the linewidths continue to scale downwards, CMOS technology will start challenging GaAs and bipolar technologies for RF markets in the C, Ku, and Ka bands. Another advantage CMOS offers over bipolar and MESFET technologies is the ability to integrate a high degree of functionality on a single chip [8]–[11]. In this paper, the microwave properties including the physics and small-signal RF performance of MOS devices are discussed [12]. In Section II, a physical model for the linear network behavior of a MOS transistor that can be used is described. The differences and with frequencies up to similarities between the linear network model of a MESFET/bipolar device and that of a MOSFET are also discussed. In Section III, a discussion on the frequency response figures as well as the of merits for a device, including the (maximum available unity power gain frequency) is presented. In Section IV, a detailed discussion on the noise performance of MOS transistors is given. In this section, the various noise Manuscript received August 10, 1998; revised October 26, 1998. This work was supported by CITO and MicroNet. The author is with the RF Technology Group, Center for Wireless Communications, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ont. N2L 3G1 Canada. Publisher Item Identifier S 0018-9200(99)01641-8. Fig. 1. The RF trends of CMOS technology with the minimum defined line width of the gate. Fig. 2. Small-signal lumped microwave network model of a MOSFET. sources within the device, in particular the drain channel noise, the thermal gate noise, and the induced gate noise, are discussed. Based on simulation results, a simple network model for the noise parameters as well as some basic trends are derived. In Section V, these trends will be presented in a form that would enable circuit designers to optimize a MOS device for minimum noise. In Section VI, design strategies associated with bipolar and MOS devices for minimum noise are compared. II. MICROWAVE NETWORK MODEL A small-signal model of a MOS transistor is shown in Fig. 2. Aside from the well-known lumped elements (i.e., gatedrain capacitance , gate-source capacitance , output , output transconductance , etc.) [13], three conductance extra elements have been included. These include the channel charging resistance , the transconductance delay , and the and . The physical importance of gate resistance each of these elements is discussed below. 1) Channel Charging Resistance (see [13]–[15]): The channel charging resistance accounts for the fact channel 0018–9200/99$10.00  1999 IEEE 278 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999 Fig. 3. Experimental extracted results of the channel charging resistance as a function of bias current. Also plotted is 1/(1.8g ). m charge that cannot instantaneously respond to changes in the gate-source voltage. This resistance is by nature a nonquasistatic parameter that accounts for the distributed effect along the channel length . Electronic carriers (e.g., electrons) at any particular point within the channel of a MOSFET see a resistive element that “points” toward the source and a capacitive element that “points” toward the gate. Since the , one channel conductance seen by the source is related to would expect that the channel resistance ( ) is proportional —others have theoretically proven this. In [14], a to direct expression has been obtained for the channel charging resistance (1) The factor of five arises due to the distributed nature of the channel resistance between the source and drain. In Fig. 3, has been extracted from a MOSFET device using a similar extraction technique used for MESFET devices [16]. In this figure, the measurement data have been fitted to a curve of 1/1.8 . Note that the proportionality relationship between and holds. Since is related directly to the width of the device, it follows that is related to one over the width. is plotted in units of -(width) to make Because of this, it independent of the width of the device; e.g., a 10- m-width device operating at 0.4 mA would have a charging resistance of 800 . 2) Gate Resistance (see [17]–[21]): In Fig. 2, the gate re) and an extrinsic sistance is split up into an intrinsic part ( part ( ). The latter comprises the contact resistance to the gate material as well as any resistance prior to entering the intrinsic portion of the gate. For a one-fingered device, the intrinsic gate resistance is given by (2) is the sheet resistance of the gate material, where is the width of the device, and is the length of the channel region. The factor of three accounts for the distributed nature of the intrinsic gate region—a rigorous derivation of (2) is provided in [20]. Several researchers have discussed the impact of the gate resistance with regards to the microwave performance of MOS transistors [17]–[21]. The gate resistance of a MOS transistor affects the RF performance in three ways. First, if the gate resistance is not accounted for at the simulation stage of a circuit, errors would result in power matching the device to an off-chip source impedance (e.g., 50 ). Second, the value of the gate resistance strongly influences the minimum noise figure of the transistor—as will be shown later. Third, the power gain of the MOS transistor is strongly governed by the gate resistance—which will also be discussed later. 3) Transconductance Delay (see [13] and [16]): The transconductance delay accounts for the fact the transconductance cannot respond instantaneously to changes in gate voltage. by . This delay is included by multiplying Physically, the transconductance delay represents the time it takes for the charge to redistribute after an excitation of the gate voltage. This time is directly related to the charging time of gate-source capacitance with the charging resistance; i.e., . The transconductance delay is by far the most difficult parameter to measure for a MOSFET (or for a MESFET). The primary reason is that the data from which these values are derived are often quite noisy. Another reason is that this parameter only becomes important beyond the of the device. If the device is used at frequencies less than (or ), this parameter can be ignored for most applications or for all intended purposes. To extract the physics from the equivalent network model, only the intrinsic components of the device need be discussed. In Table I, expressions for the -parameters of the intrinsic device are presented. Also in Table I, approximate expressions for the -parameters that go up to second order in frequency are included. In the discussions to follow, the focus will be on the intrinsic model in order to obtain the basic properties of the device. Nevertheless, the extrinsic components should be used in the numerical simulations to obtain accurate values. III. FREQUENCY RESPONSE The unity current gain frequency is defined when the current gain of the device equals one (i.e., ); is often used to measure the speed of the device. The value is therefore given by of (3) are included and it is where only second-order terms in . Here, . assumed that An important observation that comes from (3) is that the current gain is independent of the gate resistance of the device. along with calculated In Fig. 4, measurement results of with results are shown. The results show an increase in . For larger values of , saturates drain-source current to approximately 10 GHz. Beyond this point, becomes , thus making independent on bias. independent of is defined as The maximum power gain of a device the power gain delivered by a device when both input and output ports are matched to the impedance of the source and load, respectively. This figure of merit provides a fundamental limit on how much power gain one can achieve from a device. MANKU: MICROWAVE CMOS 279 TABLE I Y -PARAMETERS FOR THE INTRINSIC PORTION OF A MOSFET. ALSO GIVEN IS AN APPROXIMATE SECOND-ORDER MODEL UP TO !2 Fig. 4. Experimental results for ft as a function of bias current. For any two-port network, Re is described by Re Re Re (4) Using the -parameters provided in Table I, it can be shown that (5) where only second-order terms in are included and it is that ; this is a reasonable assumed assumption for MOS transistors used for RF applications. Equation (5) reveals two important characteristics of a MOS transistor. First, the power gain is proportional to , and second, the power gain is inversely proportional to the gate . By setting , an expression for the resistance can be derived maximum oscillation frequency (6) Surprisingly enough, the expression looks very similar to the maximum oscillation frequency of a bipolar transistor if t Fig. 5. Experimental and simulated data for the f and fmax of a MOSFET as a function of g . m is replaced with the base resistance and scales as junction capacitance. Since scales as region, and with the collector , in the saturation (7) varies where (2) has been used. Equation (7) predicts that , shorter as 1/ . Therefore, in order to design for a high ) are desirable. In terms of biasing device widths (i.e., is proportional to . parameters, (6) predicts that In Fig. 5, and are plotted as a function of the transconductance for two device widths; 40 and 60 m. The trends observed in Fig. 5 are consistent with the results is proportional to , predicted by (3) and (6); i.e., whereas is proportional to itself. In terms of device in widths, the 40- m device has a relatively higher comparison to the 60- m device. This is to be expected since 280 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999 Fig. 6. Noise equivalent circuit mode of a MOSFET. the 40- m device has a smaller gate resistance in comparison to the 60- m device. Though the curve for the larger device is shifted to the right, the relative ’s values are independent of the width. This result is consistent with (3)—i.e., since is proportional to and is proportional to , is . independent of IV. PHYSICAL NOISE SOURCES Though MOSFET’s and MESFET’s are very different in their large-signal operation, their small-signal equivalent noise models are very similar. Consequently, one may use the results of the long time studies of the microwave noise behavior of MESFET’s [22]–[24] and apply the same sort of analysis to MOSFET’s. At microwave frequencies, the intrinsic and extrinsic noise sources of a MOSFET are generated thermally. A generalized noise model of a MOS transistor is shown in Fig. 6. The intrinsic noise sources are as follows. Fig. 7. Data for the noise parameter as a function of Vds . 1) Drain channel noise : this noise is due to the thermal noise generated by the carriers in the channel region.1 : this noise is due to the thermal 2) Gate resistance noise noise generated by the gate resistance. 3) Induced gate noise : this noise is due to the thermal noise generated by the carriers in the channel, which capacitively couples itself onto the gate node as a gate current. To understand the characteristics of drain channel noise and induced gate noise, both numerical simulation results [25] and experimental results will be presented. The thermal noise within the channel gives rise to both drain channel noise and induced gate noise. The drain channel noise is typically represented by (8) is a bias-dependent parameter, is zero drain Here, voltage conductance of the channel (this is typically taken is to be equal to the transconductance of the device), Boltzmann’s constant, is the temperature of the carriers in is the noise bandwidth. In Fig. 7, the the channel, and parameter is plotted as a function of drain-source voltage. Two other sources of data have been extracted from the literature [26], [27] and plotted in Fig. 7. As the drain-source 1 Strictly speaking, this noise should be treated as diffusion noise. Fig. 8. The ratio of the induced gate noise to the channel drain noise as a function of normalized frequency. voltage increases, the factor increases. This can be explained as follows. As one increases the drain-source voltage, the electric field within the channel increases. The increasing electric field causes more carriers to reach velocity saturation. With more carriers at velocity saturation, the amount of diffusion noise near the drain increases [25]. In Fig. 8, the relative magnitudes of and are plotted as a ratio; the results were extracted from a quasi-three-dimensional V, device noise simulator [25]. For these results, V, and the transconductance was extracted to be 0.13 mS/ m at 2 GHz. From these simulation results, it was noted that is approximately independent of frequency, whereas increases as . The ratio can be interpreted as the effective current noise gain seen from the gate port to the drain port; note that for a bipolar transistor, the current noise gain is equal to the dc current gain of the device. Since the channel drain noise and induced gate noise are physically generated by the same noise source, they are correlated. In Fig. 9, simulation results for the normalized correlation between the drain current noise and the gate current MANKU: MICROWAVE CMOS 281 (a) Fig. 9. The normalized correlation factor between the induced gate noise and the channel drain noise. noise are plotted, i.e., (9) (b) where and are defined as the real and imaginary part of the normalized correlation factor, respectively. The simulations is approximately equal to zero. This is to be reveal that expected since carriers travelling to the gate are displaced by 90 . For lower frequencies, our results extrapolate to a , which corresponds to the predicted value of value of long channel devices [23], [28]. As the frequency of operation approaches 0.3. increases, The gate thermal noise arises from the resistance of the gate material. It is commonly assumed that this noise source can be ignored if one uses a finger structure for the gate. However, in the next section, it will be shown that the gate thermal noise is very important in the design of low-noise devices even if a multifinger structure is employed. The noise introduced by the intrinsic portion of the gate structure of width and channel length is given by (10) As in (2), the factor of three arises from a distributed effect. V. MICROWAVE NOISE PROPERTIES To determine the noise parameters of the equivalent circuit and [see in Fig. 10(a), the input reference noise sources Fig. 10(b)] are determined, i.e., (11) (12) Note that the two noise sources (11) and (12) are correlated since they contain common noise terms. By using (11) and (12), all the measurable noise parameters (for definitions of the noise parameters see [29]) can be obtained (13) Fig. 10. (a) Approximate intrinsic noise model of a MOSFET and (b) equivalent noise model of (a). (14) (15) (16) is the noise conductance, is the optimum noise where in the optimum noise reactance, is the resistance, is the input reactance of the minimum noise figure, and – are weak functions of bias device. The parameters and are less than one—the details of these parameters will not be given here, but can be derived from (11) and (12). ), – are If induced gate noise is neglected (i.e., is equal to one if induced gate equal to one. The parameter noise is included and zero if it is ignored (i.e., ). In , it has been assumed that the approximate equation for is relatively small in value. The minimum noise figure of the device is directly propor. Therefore, the larger the gate resistance, the tional to higher the minimum noise figure. Another interesting point to note is that the minimum noise figure is directly proportional . Therefore, by increasing the of the device, to the minimum noise figure drops in value. One method to of the device is to increase the independently increase the drain-source biasing current. In Fig. 11, the minimum noise figure of a MOS device as a function of biasing current is plotted (also see [25]). For low values of bias current, the minimum noise figure decreases in value with bias current. At some point, however, any increase in the bias current causes 282 Fig. 11. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999 Minimum noise figure as a function of bias current. Fig. 12. the minimum noise to increase in value. When this occurs, becomes independent of bias current; the transconductance i.e., any increase in bias current will not cause a significant increase in . Using this argument, and the fact that gamma is a function of bias, causes the minimum noise figure to increase. in (15) can be shown to be approximately The factor equal to (17) is proportional to and is equal to the effective where . For long channel devices, is current gain noise, i.e., is predicted to be equal to 0.83 [23]; in [25], the factor also shown to be a function of bias and gate width. From the is predicted to be closer to one; results in Figs. 8 and 9, recall that if the overall contribution of induced gate noise is small, . This is the ideal situation since it corresponds to simultaneously matching the reactive part of the device for , there both power and minimum noise. However, if would exist an error in matching for both power and noise. To provide insight into the noise behavior of a MOSFET, it is convenient to compare the optimum noise reactance of a BJT to that of a MOS transistor. The optimum noise reactance of a BJT is approximately given by (18) is the dc beta of the BJT. For the case when , we see that . Therefore, the design criteria would be to bias the transistor such that the of the device is approximately three to five times the operating frequency. This would thus allow one to simultaneously match for both power and noise [30]. In terms of noise, the main similarity between a BJT and a MOSFET is that they both have an input and an output noise current. The input current noise for a MOSFET corresponds to the induced gate noise, whereas for a BJT, it corresponds to the base shot noise. The output current noise for a MOSFET corresponds to the drain channel noise, whereas for a BJT, it corresponds to collector shot noise. For a MOS transistor, induced gate noise varies and is correlated to the drain channel noise. However, as for a BJT, the base shot noise and the collector shot noise are not correlated and are independent of the frequency. It is these two differences that make it difficult for a MOSFET to simultaneously match for both noise and power in the same manner as a BJT. where X in and X opt as a function of bias current. To determine the importance of induced gate noise, we and for a MOS transistor.2 The have measured both results are shown in Fig. 12. The results were measured at a relatively high frequency in order to reduce measurement error. The randomness in the measurements is mainly due to random measurement error as opposed to systemic errors. Two different devices were measured. From the results in Fig. 12, it can be noted that the effect of induced gate noise with regards to the optimum noise reactance is small. That is to say, it should be possible to match for both noise and power or . This also implies that the since magnitude of induced gate noise is much less pronounced in MOS transistors as compared to the MESFET [24]. Other evidence supporting the above claims can be found in [31] and [32]. To completely match for noise, the optimum noise resistance has to be equal to the driving source resistance. For a BJT transistor, this is relatively easy to accomplish since the optimum source resistance is approximately equal to the base resistance; since this resistance scales as the emitter strip length, the optimum noise resistance also scales in this manner. Consequently, in order to match for noise, the emitter strip length is selected such that the optimum noise resistance is approximately equal to the driving resistance, which is typically 50 . However, this method is not easily applied to a MOS transistor because the scaling nature of the gate structure is different than that of the base of a BJT. This will be discussed later in greater detail. However, it will also be shown later that noise matching can be achieved by using the number of gate fingers as the parameter to adjust in order to . satisfy the condition If a single finger transistor has an equivalent input current and , respectively, the noise figure of and voltage of this transistor can be written as (19) is the minimum noise figure of the single finger, where is the noise conductance of a single finger, is the is the optimum noise driving source resistance, and impedance of a single finger. By adding fingers, the equivalent noise current and voltage can be shown to be equal and , respectively. An example using two to gate fingers is shown in Fig. 13(a), and the equivalent network 2 The measurements were performed using the ATN-Microwave NP5 system setup. MANKU: MICROWAVE CMOS 283 TABLE II EXPERIMENTAL OBSERVED SCALING RULES FOR THE SMALL-SIGNAL PARAMETERS AND THE MICROWAVE FIGURE OF MERITS OF A MOSFET (a) VI. SUMMARY OF SCALING RULES FOR ELEMENT VALUES (b) Fig. 13. (a) An illustration of a two-finger MOS device and (b) equivalent noise network representation of N gate fingers. Fe denotes the excess noise away from Fmin . Fig. 14. Ropt and Fmin as a function of the number of gate fingers. representation is shown in Fig. 13(b). Using these values for the equivalent noise current and voltage, the new expression for the noise figure becomes Scaling rules for the MOSFET equivalent circuit are easily arrived at from simple analytical expressions for the elements or from the measurements of different size devices from the same foundry. Most of the scaling rules are intuitively obvious, and element values are easily scaled up or down based on the total gate width and the number of fingers. In Table II, a summary of all the various scaling rules for the various parameters are provided. The scaling rules are given for both gate width and number of fingers. The scaling laws for a MOSFET are very similar to those of a MESFET. However, if one compares the scaling nature of a bipolar device to a MOS device, several differences can be noted. These differences stem from the fact that the base resistance and the gate resistance scale differently. For comparison purposes, the equivalent width and length of a BJT and a MOSFET are depicted in Fig. 15. Since the direction of current flow within the two devices is different, the base resistance scales as 1/ , whereas the gate resistance scales as . Because of this, the minimum noise figure of a bipolar transistor is independent of , whereas for a MOS transistor, it is proportional to (see Fig. 15): recall that the minimum noise figure of a BJT is approximately given by (20) (21) denotes the noise figure for the where the superscript fingered device. Note that the minimum noise is independent of , the noise conductance scales as , and the optimum noise impedance scales as 1/ . One of the important results here is that the minimum noise figure is independent of the number of fingers and is only a function of one finger. To illustrate and as a function of this, measurement results of the number of fingers are shown in Fig. 14. Note that is independent of the number of fingers and scales as 1/ . The advantage of using the number of fingers as the parameter for matching the optimum noise resistance to the source resistance is that the minimum achievable noise figure is not affected. is the transconductance, where is the base resistance and to the which scales as . However, in order to match source resistance, large values of are required. Since the of a bipolar transistor is independent of , the width of . However, the device can be altered to achieve the desired increases for a MOSFET, increases in value. It is if this very difference that makes a MOSFET and a BJT different in terms of designing for minimum noise. VII. CONCLUSIONS As mentioned earlier, the goal of this paper is to provide a qualitative understanding of the microwave properties of CMOS devices so as to help IC analog designers create better 284 Fig. 15. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999 Noise parameters as a function of W and L for a bipolar transistor and MOSFET for a fixed current density. front-end RF CMOS circuits. To optimize an RF circuit within a CMOS environment, it is important to couple the vast amount of knowledge gathered by the traditional microwave designer as well as by the IC analog designer—i.e., they cannot design in isolation. In this paper, we have tried to couple these two perspectives to better understand the RF properties of CMOS devices. [10] [11] ACKNOWLEDGMENT [12] The author would like to thank J. Molnar, J. Nisbet, B. Hadaway, and Dr. M. Maliepaard for their continual support, along with Prof. A. Nathan for his enlightening comments. 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Noise in Physical Systems and 1/f Fluctuations, Leuven, Belgium, C. Claeys and E. Simoen, Eds. Singapore: World Scientific Publishing, July 14–18, 1997, pp. 488–491. [32] Q. Huang, P. Orsatti, and F. Piazza, “Broadband, 0.25m CMOS LNA’s with sub-2dB NF for GSM applications,” in Proc. IEEE 1998 Custom Integrated Circuits Conf., 1998, pp. 67–70. 285 Tajinder Manku (S’92–M’94) was born in Kenya, Nairobi, in 1967. He received the B.Sc. degree in physics from the University of Manitoba, Winnipeg, Man., Canada, in 1990 and the M.A.Sc. and Ph.D. degrees in electrical engineering from the University of Waterloo, Waterloo, Ont., Canada, in 1991 and 1993, respectively. From 1993 to 1995, he was with Mitel Semiconductors, Canada, as a device and IC designer. From 1995 to 1997, he was with the Technical University of Nova Scotia, Halifax, N.S., Canada, as an Assistant Professor. He is currently an Associate Professor with the University of Waterloo. His research interests include microwave and RF design and semiconductor physics. Dr. Manku is a member of the Association of Professional Engineers of Nova Scotia (APENS).