Front end

We describe a method of generating and utilizing visual landmarks that is well suited for SLAM applications. The landmarks created are highly distinctive and reliably detected, virtually eliminating the data association problem present in other landmark schemes. Upon subsequent detections of a landmark, a 3-D pose can be estimated. The scheme requires a single camera.

One of the main goals of the HADES-at-FAIR upgrade project is to achieve sustained trigger rates of 20 kHz in the Au+Au heavy-ion collision system at energies up to 8 GeV/u. In this context, a fast and reliable data acquisition of the 24 Multiwire Drift Chambers (MDCs) is developed. The general concept of the upgrade is based on the Trigger and Readout Board (TRB). This hardware has two digital interface connectors for mounting add-on boards. In the special case of MDC, the add-on board is the interface to the detector Front End Electronic (FEE).

After a brief discussion of the recent development of SiGe HBT technology, the state-of- the-art achievement of the technology in circuits implementation is reviewed from an applied perspective, focusing on microwave and mm-wave applications. In particular, the performance of SiGe HBT-based oscillator and receiver front-end ICs are presented and relevant industry issues are addressed.

Objective: To evaluate the performance of continuous and pulsed Doppler systems a test signal generator has been developed, simulating an ultrasound radio frequency signal, to be injected by induction into the front-end of an ultrasound Doppler system. Unlike for flow rigs the characteristics of the simulated signal are exactly known and under full control of the user, allowing for an objective interpretation of the test results. Methods: Under software control specific signal characteristics, e.g. ultrasound carrier frequency, clutter frequency, amplitude of clutter signal with respect to Doppler signal amplitude, Doppler signal-to-noise ratio, mean Doppler frequency, shape and width of the Doppler spectral distribution, and its time-dependent behavior can be set and varied. Results: A software package was developed to manipulate the relevant characteristics of the radio frequency signal and to drive a PC compatible plug-in card for signal generation. To illustrate the applicabilit...

In the nanometer regime, especially the RF and analog circuits exhibit wide parameter variability, and consequently every chip produced needs to be tested. On-chip design for testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, artificial neural networks (ANN) are employed as multivariate regression technique to architect a general RF calibration scheme using DC- instead of RF stimuli. This relaxes the routing requirements on a chip for GHz test signals along with the reduction in test time and cost. The RF detector, a key element of a radio front-end DfT circuitry, designed in 65 nm CMOS is used to demonstrate the calibration scheme.

Abstract. This paper investigates the potential of recurrent spiking neurons for classification problems. It presents a hybrid approach based on the paradigm of Reservoir Computing. The practical applications based on recurrent spiking neurons are limited due to their ...

Three-level NPC active-front-end three-phase (3LAFE) converters can be applied to high-power medium voltage applications, with 4-quadrant unity-power-factor operation, allowing a broad range for power conversion systems, such as decentralized energy distribution and utilization. Switching losses and network interaction limit the operation of 3LAFE high-power converters, especially when GTO-converters are used.