Research Interests:
With the introduction of ever smaller dimensions in modern day semiconductor devices, Zener tunneling can no longer be neglected and is affecting device performance. On one hand Zener tunneling is responsible for a leakage current in... more
With the introduction of ever smaller dimensions in modern day semiconductor devices, Zener tunneling can no longer be neglected and is affecting device performance. On one hand Zener tunneling is responsible for a leakage current in classical devices such as the MOSFET, on the other hand it provides the drive current for some new devices under investigation such as the
Research Interests:
Abstract We describe on-chip circuits specially designed and fabricated for the purpose of measuring the effect of AC NBTI on an individual, well-defined device in the wide frequency range on a single wafer. The circuits are designed to... more
Abstract We describe on-chip circuits specially designed and fabricated for the purpose of measuring the effect of AC NBTI on an individual, well-defined device in the wide frequency range on a single wafer. The circuits are designed to allow measurements in multiple ...
Research Interests: Iedm and Charge Pump
In this paper, breakdown of a deep trench isolation structure has been analysed and modeled. In particular, it is shown that the breakdown voltage of the p-n junction in the silicon can be strongly affected by the presence of charges on... more
In this paper, breakdown of a deep trench isolation structure has been analysed and modeled. In particular, it is shown that the breakdown voltage of the p-n junction in the silicon can be strongly affected by the presence of charges on the floating polysilicon within the trench. These charges might appear not only as process- induced charges but also as a consequence of hot carrier injection during avalanche operation. The measured breakdown instabilities can be reproduced by TCAD simulations as well as by a simple theoretical model within which these results can be understood and predictions can be made.
Research Interests:
A novel "plug-and-play" ESD protection methodology for wideband RF applications is demonstrated. This methodology utilizes an integrated transformer together with classical ESD protection elements. As a demonstrator, a wideband... more
A novel "plug-and-play" ESD protection methodology for wideband RF applications is demonstrated. This methodology utilizes an integrated transformer together with classical ESD protection elements. As a demonstrator, a wideband RF LNA in 0.18 mum CMOS is protected above 4.5 kV HBM without degrading its bandwidth.
Research Interests:
Channel hot-carrier (CHC) degradation in short channel transistors with a high-k gate stack processed in CMOS technology has been analysed. For short channel transistors (L < 0.15mum), the most damaging stress... more
Channel hot-carrier (CHC) degradation in short channel transistors with a high-k gate stack processed in CMOS technology has been analysed. For short channel transistors (L < 0.15mum), the most damaging stress condition has been found to be VG = VD instead of the "classical" VG = VD/2 for long channel transistors. In this work, we have demonstrated that this shift
Research Interests:
Research Interests:
The electrical stability of CMOS devices with conventional gate dielectrics is commonly studied using static (DC) measurement techniques. By applying the same methods to MOS devices with alternative gate dielectrics, it has been shown... more
The electrical stability of CMOS devices with conventional gate dielectrics is commonly studied using static (DC) measurement techniques. By applying the same methods to MOS devices with alternative gate dielectrics, it has been shown that alternative gate stacks suffer from severe charge trapping and that the trapped charge is not stable, leading to fast transient charging components. In this paper,
Research Interests:
ABSTRACT In this paper, we focus on comparing the VTH-instability in scaled stacks with the trapping behavior of thick HfO2 layers. We show that a large part of the instability is caused by charging/discharging of HfO2 bulk defects,... more
ABSTRACT In this paper, we focus on comparing the VTH-instability in scaled stacks with the trapping behavior of thick HfO2 layers. We show that a large part of the instability is caused by charging/discharging of HfO2 bulk defects, independent of the HfO2 thickness. The interfacial oxide thickness influence the mechanism of charging and discharging of the HfO2 defects.
Research Interests:
... Digesf, 2001 and 2002. [2] A. Kerber et al., IEEE Electron Device Leu., accepted for publication. [3] Y. Kim et al.; IEDM Tech. Digesl, pp. 455,2001. 141 G. Van den Bosch et al.. IEEE Electron . _ Devicekerr.,Vol. 14, pp. 107, 1993.... more
... Digesf, 2001 and 2002. [2] A. Kerber et al., IEEE Electron Device Leu., accepted for publication. [3] Y. Kim et al.; IEDM Tech. Digesl, pp. 455,2001. 141 G. Van den Bosch et al.. IEEE Electron . _ Devicekerr.,Vol. 14, pp. 107, 1993. [5] L.-A. Ragnarsson et al., Appl. Phys. ...
Research Interests: Digest and Charge Pump
In this work we present a novel trap spectroscopy based on stress induced leakage current measurements for constant voltage stress and substrate hot carrier injection stresses in nMOSFET devices. Peaks in the stress induced leakage... more
In this work we present a novel trap spectroscopy based on stress induced leakage current measurements for constant voltage stress and substrate hot carrier injection stresses in nMOSFET devices. Peaks in the stress induced leakage current at several gate voltages are attributed specifically to defects in the bulk and at the interface by using the substrate hot electron injection technique
Research Interests:
High power devices can generate large amount of heat dissipation that limits severely their power handling capability. In this paper, we propose intensive investigations of the electro-thermal characteristics of lateral nDMOS transistors... more
High power devices can generate large amount of heat dissipation that limits severely their power handling capability. In this paper, we propose intensive investigations of the electro-thermal characteristics of lateral nDMOS transistors processed in a 0.7 μm CMOS based smart power technology. In particular, it is demonstrated, both experimentally and theoretically, that the thermal management improves substantially when a layer
Research Interests:
Research Interests:
This paper describes the implementation of High Injection MOS Flash E2PROM devices in a 0.7¿m CMOS technology. The cell has been optimized from the point of view of cell area as well as programming speed. A virtual ground array... more
This paper describes the implementation of High Injection MOS Flash E2PROM devices in a 0.7¿m CMOS technology. The cell has been optimized from the point of view of cell area as well as programming speed. A virtual ground array configuration is proposed to scale the cell area down to the range of 15¿m2. The device is programmed in a few
Research Interests:
Most Flash memories rely on channel hot-electron injection or on Fowler-Nordheim tunnelling for programming. However, Source-Side Injection (SSI) has also been suggested as an alternative programming mechanism since it combines a high... more
Most Flash memories rely on channel hot-electron injection or on Fowler-Nordheim tunnelling for programming. However, Source-Side Injection (SSI) has also been suggested as an alternative programming mechanism since it combines a high injection efficiency with a low power consumption1-6). In the meanwhile, the viability of using this programming mechanism for state-of-the-art nonvolatile applications has been sufficiently demonstrated and the ability
Research Interests:
An alternative device architecture for improved hot carrier reliability which is based on the GOLD concept is proposed. The gate overlap is accurately controlled independently of the implant conditions. A comparison with LDD devices shows... more
An alternative device architecture for improved hot carrier reliability which is based on the GOLD concept is proposed. The gate overlap is accurately controlled independently of the implant conditions. A comparison with LDD devices shows a large improvement in resistance against hot-carrier degradation with this new device architecture for the n- and p-MOSFET. The optimized FOND devices have the highest
Research Interests:
Negative bias temperature instabilities (NBTI) in SiOx(N)/HfSiO(N)/TaN based pMOSFETs are investigated. It is shown that nitrogen-incorporation in the gate stack (either by NH3 anneals or decoupled plasma nitridation, DPN) result in much... more
Negative bias temperature instabilities (NBTI) in SiOx(N)/HfSiO(N)/TaN based pMOSFETs are investigated. It is shown that nitrogen-incorporation in the gate stack (either by NH3 anneals or decoupled plasma nitridation, DPN) result in much enhanced NBTI. Device degradation is mainly due to fast (interface) state generation in the non-nitrided stacks, while a substantial contribution of the defects produced in the nitrided stacks
Research Interests:
This paper discusses the electrical characterization of complementary multiple-gate tunneling field effect transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard complementary metal oxide semiconductor (CMOS)... more
This paper discusses the electrical characterization of complementary multiple-gate tunneling field effect transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard complementary metal oxide semiconductor (CMOS) processing, emphasizing the dependence of the tunneling current on the fin-width. A linear dependence of the tunneling current for narrow fins with the square root of the fin width is experimentally reported for
Research Interests:
As a solution to the low on-current of silicon-based tunnel-FETs (TFETs), the source material of the n-channel TFET is replaced with the small-bandgap material germanium, which results in a current boost up to the same level as the... more
As a solution to the low on-current of silicon-based tunnel-FETs (TFETs), the source material of the n-channel TFET is replaced with the small-bandgap material germanium, which results in a current boost up to the same level as the current of MOSFETs. However, no solution has been reported to boost the on-current of the all-silicon p-TFET, a necessity for making an
Research Interests:
In this paper we present a thermal simulation tool based on analytical equations, which is able to calculate temperature distributions on a die as a function of time for any number of arbitrary power sources. The tool is much faster than... more
In this paper we present a thermal simulation tool based on analytical equations, which is able to calculate temperature distributions on a die as a function of time for any number of arbitrary power sources. The tool is much faster than dedicated numerical software and offers a large flexibility to circuit designers. The results have been found to agree well with results from commercial software. Moreover, pulsed DMOS measurements have been performed in order to validate the temperature predictions.
Research Interests:
This work discusses the discrete nature of Stress-Induced Leakage Current (SILC) in small samples with ultrathin SiON. We isolate the current-voltage characteristics of single-trap leakage paths and we evaluate their statistical... more
This work discusses the discrete nature of Stress-Induced Leakage Current (SILC) in small samples with ultrathin SiON. We isolate the current-voltage characteristics of single-trap leakage paths and we evaluate their statistical properties. Each leakage path can - to a first order approximation ~ be described by the gate voltage at which it becomes conducting and by its conductivity at fixed
Research Interests:
When characterizing semiconductor components to determine their ESD robustness using a transmission line pulse test system, there is no universally accepted standard procedure for performing the test available at present. In this paper,... more
When characterizing semiconductor components to determine their ESD robustness using a transmission line pulse test system, there is no universally accepted standard procedure for performing the test available at present. In this paper, we address this issue whereby we study the impact of the following TLP characterization related variables: failure criterion, influence of stress step-size and cumulative stress effects. We
Research Interests:
This paper investigates on the transient pulse response of the device under test, which is becoming a critical aspect in determining the ESD reliability of a variety of technology products. For the first time, the feasibility to calibrate... more
This paper investigates on the transient pulse response of the device under test, which is becoming a critical aspect in determining the ESD reliability of a variety of technology products. For the first time, the feasibility to calibrate or tune the artifacts arising out of system parasitic to `see' the device transient response is presented in this paper with experimental
Research Interests:
Optoelectronics, Displays, and Imaging Effect of Dislocations on the Zero-Bias Resistance-Area Product, Quantum Efficiency, and Spectral Response of LWIR HgCdTe Photovoltaic Detectors............................................... V. Gopal and S. Gupta 1220 The Noise Performance of Electron Multi...more
For the first time, the degradation of a DMOS transistor is shown to be due to hot hole injection in the drift region field oxide. The saturation effects observed in the parameter shifts are reproduced by a new degradation model using the... more
For the first time, the degradation of a DMOS transistor is shown to be due to hot hole injection in the drift region field oxide. The saturation effects observed in the parameter shifts are reproduced by a new degradation model using the bulk current as the driving force. A very good agreement with experimental data is obtained for various stressing
Research Interests:
Lifetime of pMOSFETs is limited by negative bias temperature instability (NBTI). For the first time, we show that the NBTI-induced threshold voltage shift, DeltaVth, measured in early works by using either the... more
Lifetime of pMOSFETs is limited by negative bias temperature instability (NBTI). For the first time, we show that the NBTI-induced threshold voltage shift, DeltaVth, measured in early works by using either the 'on-the-fly' or the conventional transfer characteristics extrapolation techniques is not the real DeltaVth under practical operation. A new method is proposed for estimating the real DeltaVth.
Research Interests:
In order to maintain the trend of ever-increasing performance, several directions have been pursued by the semiconductor industry in the past decade. i) Conventional Si and SiO2 are being replaced by more exotic materials, from high-k... more
In order to maintain the trend of ever-increasing performance, several directions have been pursued by the semiconductor industry in the past decade. i) Conventional Si and SiO2 are being replaced by more exotic materials, from high-k gate dielectrics to metal gates and to high-mobility substrates, ii) new (3D) device architectures are being developed, iii) devices are downscaled toward atomic dimensions, while iv) supply voltages are not correspondingly reduced.
Research Interests:
ABSTRACT For the Si-based TFET to beat the MOSFET performance and allow ultra-low voltage operation with re-use of a lot of the existing processing expertise, critical device optimization is needed whereby a combination of several... more
ABSTRACT For the Si-based TFET to beat the MOSFET performance and allow ultra-low voltage operation with re-use of a lot of the existing processing expertise, critical device optimization is needed whereby a combination of several performance boosters must be implemented. Heterostructures and an appropriate stress profile are necessary requirements. The largest design impact is expected from scaling the effective oxide thickness and the body thickness. Field-induced quantum confinement affects most theoretical predictions today and needs to be addressed in the design optimization. Overall, there are still significant challenges both in modeling, processing and characterization of the device. Progress in all three areas is required to uncover the full potential of the TFET.
Research Interests: Low Power and Logic Gate
Research Interests:
1. Electrical Properties of Low-$ V_ {T} $ Metal-Gated n-MOSFETs Using $ hbox {La} _ {2} hbox {O} _ {3}/hbox {SiO} _ {x} $ as Interfacial Layer Between HfLaO High-$ kappa $ Dielectrics and Si Channel, Chang, SZ Yu, HY Adelmann, C.... more
1. Electrical Properties of Low-$ V_ {T} $ Metal-Gated n-MOSFETs Using $ hbox {La} _ {2} hbox {O} _ {3}/hbox {SiO} _ {x} $ as Interfacial Layer Between HfLaO High-$ kappa $ Dielectrics and Si Channel, Chang, SZ Yu, HY Adelmann, C. Delabie, A. Wang, XP Van ...
Research Interests:
The reliability of a one Transistor Floating Body Random Access Memory (1T-FBRAM) bulk FinFET cell using Bipolar Junction Transistor (BJT) programming is investigated. It is shown that hot holes generated by impact ionization create... more
The reliability of a one Transistor Floating Body Random Access Memory (1T-FBRAM) bulk FinFET cell using Bipolar Junction Transistor (BJT) programming is investigated. It is shown that hot holes generated by impact ionization create interface defects close to the drain and positively charged oxide traps, especially at high transverse electric field. These created defects degrade the cell endurance. Moreover, this
Research Interests:
The impact of nitridation anneal of Hf-silicates based metal-gated pMOSFETs on negative bias temperature instability (NBTI) is investigated. Non-nitrided stacks annealed in N2 or O2 and nitrided stacks either annealed in NH3 or exposed to... more
The impact of nitridation anneal of Hf-silicates based metal-gated pMOSFETs on negative bias temperature instability (NBTI) is investigated. Non-nitrided stacks annealed in N2 or O2 and nitrided stacks either annealed in NH3 or exposed to decoupled plasma nitridation (DPN) are measured. For non-nitrided stacks, NBT degradation is mainly due to fast-states generation. A much enhanced NBT degradation is observed, in
Research Interests:
This paper presents a comparison of several different programming mechanisms utilised to store Multilevel information on a specifc device. Such comparison shows that Source Side Injection (SSI) is indeed a very viable approach for... more
This paper presents a comparison of several different programming mechanisms utilised to store Multilevel information on a specifc device. Such comparison shows that Source Side Injection (SSI) is indeed a very viable approach for Multi-Level Charge Storage (MLCS) which could be applied without requiring program verify.
Research Interests:
The field and temperature dependence of the leakage current of low-k material is studied by using planar capacitors. First it is shown that our planar capacitors are suitable test vehicles to analyze the intrinsic properties of low-k... more
The field and temperature dependence of the leakage current of low-k material is studied by using planar capacitors. First it is shown that our planar capacitors are suitable test vehicles to analyze the intrinsic properties of low-k materials. Then an evaluation of the trap density of the investigated low-k material is performed. Eventually different models such as Poole-Frenkel emission, Schottky
Research Interests:
Research Interests:
Abstract A consistent model for the intrinsic time dependent dielectric breakdown (TDDB) of thin oxides is introduced. This model links the existing anode hole injection and the electron trap generation models together and describes... more
Abstract A consistent model for the intrinsic time dependent dielectric breakdown (TDDB) of thin oxides is introduced. This model links the existing anode hole injection and the electron trap generation models together and describes wearout as a hole induced generation of ...
Research Interests:
In this study the field acceleration of intrinsic and extrinsic breakdown is studied. For the intrinsic mode an exp(1/E)-acceleration law is found, while for the extrinsic mode an new exp(E)-acceleration law for Q/sub BD/ is proposed.... more
In this study the field acceleration of intrinsic and extrinsic breakdown is studied. For the intrinsic mode an exp(1/E)-acceleration law is found, while for the extrinsic mode an new exp(E)-acceleration law for Q/sub BD/ is proposed. This field acceleration model is implemented in a maximum likelihood algorithm together with a new analytical expression for fitting competing Weibull distributions. With this
Research Interests:
ABSTRACT We derive an analytical model based on circular tunnel paths along the electric field to describe the behavior of a tunnel FET with a junction angle at the source. The model is compared with simulation results and qualitative... more
ABSTRACT We derive an analytical model based on circular tunnel paths along the electric field to describe the behavior of a tunnel FET with a junction angle at the source. The model is compared with simulation results and qualitative agreement is observed. We further demonstrate that a small junction angle prevents TFET performance degradation resulting from a high-k spacer. Finally we optimize the junction angle with an encroaching source structure, studying the dependence on oxide thickness and semiconductor material.
Research Interests:
Abstract This paper presents the general and analytical solution of a fourth-order lumped element model (LEM) to describe human body model (HBM) electrostatic discharge (ESD) testers including the main tester parasitic elements. The... more
Abstract This paper presents the general and analytical solution of a fourth-order lumped element model (LEM) to describe human body model (HBM) electrostatic discharge (ESD) testers including the main tester parasitic elements. The analytical fitting to the LEM of ...
Research Interests:
The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. In general, the TFET current can be decomposed into two components referred to as point tunneling and line... more
The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. In general, the TFET current can be decomposed into two components referred to as point tunneling and line tunneling. In this paper we derive a compact analytical model for the current due to point tunneling complementing the previously derived analytical model for
Research Interests:
The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. Due to the absence of a simple analytical model for the TFET, the working principle is generally not well... more
The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. Due to the absence of a simple analytical model for the TFET, the working principle is generally not well understood. In this paper a new TFET structure is introduced and using Kanepsilas model, an analytical expression for the current through the TFET