We have investigated the dynamics of hard intrinsic dielectric breakdown of gate oxide layers wit... more We have investigated the dynamics of hard intrinsic dielectric breakdown of gate oxide layers with thickness between 35 and 5.6 nm in n+ polycrystalline Si-SiO2-Si metal/oxide/semiconductor capacitors after constant voltage Fowler-Nordheim stress. The buildup of defects in the oxide during the degradation phase was monitored by quasi static C-V measurements. The dynamics of the final breakdown event was followed with high time resolution, allowing to measure voltage, current, and power versus time during the breakdown transient. Transmission electron microscopy data quantifying the damage produced during this transient are reported. Finally, we propose a phenomenological model concerning the dynamics of breakdown with model parameters adjusted on the basis of the experimental data.
In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channe... more In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide field effect transistors (pMOSFETs) with a Si passivated surface. The gate stack consists of HfO2/SiO2 dielectric with TiN /TaN metal gate. The observed temperature dependence of the gate current indicates that the dominant charge transport mechanism through the gate dielectric consists of Poole-Frenkel conduction. Gate current 1/f noise is more than two orders higher in the case of Ge pMOSFETs when compared to reference Si pMOSFETs. Ge outdiffusion into the gate oxide is the suspected cause for the enhanced Poole-Frenkel conduction and the high gate current 1/f noise in Ge pMOSFETs.
In this paper we critically review and compare experimental methods, based on the Lundstrom model... more In this paper we critically review and compare experimental methods, based on the Lundstrom model, to extract the channel backscattering ratio in nano MOSFETs. Basically two experimental methods are currently used, the most common of them is based on the measurement of the saturation drain current at different temperatures. We show that this method is affected by very poor assumptions and that the extracted backscattering ratio strongly underestimates its actual value posing particular attention to the backscattering actually extracted in nano devices. The second method is based on the direct measurement of the inversion charge by CV characteristics and gets closer to the physics of the backscattering model. We show, through measurements in high mobility p-germanium devices, how the temperature based method gives the same result of the CV based method once that its approximations are removed. Moreover we show that the CV based method uses a number of approximations which are partially inconsistent with the model. In particular we show, with the aid of 2D quantum corrected device simulations, that the value of the barrier lowering obtained through the CV based method is totally inconsistent with the barrier lowering used to correct the inversion charge and that the extracted saturation inversion charge is underestimated.
The temperature dependence of the trap-assisted tunneling (TAT) current component in Ge p + n jun... more The temperature dependence of the trap-assisted tunneling (TAT) current component in Ge p + n junctions has been studied between 25 • C and 140 • C. It is shown that the impact of TAT reduces significantly due to the combination of the negative thermal activation of the TAT-enhancement factor and the exponential increase of the diffusion current with temperature. It is shown that the experimental data can be well described in the frame of the Hurkx analytical model, which allows a fairly easy assessment of the TAT current contribution to the junction leakage current at realistic operation temperatures of Ge CMOS circuits.
I E E E Transactions on Electron Devices, Aug 1, 2012
We developed an analytical model that is able to predict the evolution of the subthreshold slope ... more We developed an analytical model that is able to predict the evolution of the subthreshold slope variability associated with hot carrier (HC) stress. The model assumes that HC stress generates interface states with a Poisson distribution and that the number of HC-induced interface states increases linearly with the HC-induced subthreshold slope variation. We validate the model by means of extensive variability data sets collected on n-channel MOSFETs in 45-and 65-nm CMOS technologies. Furthermore, we investigate the correlation between the threshold voltage and the subthreshold slope fluctuations in order to fully characterize their impact on the subthreshold current variability.
ABSTRACT The on-off fluctuations of the tunnel current in thin oxide MOS structures before breakd... more ABSTRACT The on-off fluctuations of the tunnel current in thin oxide MOS structures before breakdown is a well known phenomenon since 1985. Notwithstanding this, most of the models proposed in the last years to justify the failure of the structure ignore this phenomenon. The physical mechanism responsible for it is not completely clear, even if some possible explanations have been proposed. Some new results, obtained by using a novel characterization tool, are presented in this paper. These results could open new perspectives in the comprehension of the final stage of time dependent breakdown of thin oxides. .
2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012
This paper discusses the low-frequency noise behavior of SiGe-channel bulk FinFETs processed on (... more This paper discusses the low-frequency noise behavior of SiGe-channel bulk FinFETs processed on (100) and (110) Si wafers. A comparison is also made with planar SiGe-channel pMOSFETs. It is shown that for devices with carriers confined in the quantum well, only 1/f noise is observed, dominated by mobility fluctuations. Surprisingly, SiGe pMOSFETs fabricated on (110) Si wafers exhibit the highest mobility but also the highest 1/f noise, corresponding with trapping/detrapping. This is also consistent with the density of interface traps extracted from charge pumping measurements.
The impact of a submonolayer of HfO2 sandwiched between the SiON gate dielectric and the polycrys... more The impact of a submonolayer of HfO2 sandwiched between the SiON gate dielectric and the polycrystalline silicon layer on the low frequency noise of a n-channel metal oxide semiconductor field effect transistor is investigated. Fermi-level pinning at polycrystalline silicon-HfO2 interface acts as a dramatic source of the drain noise due to charge carrier number fluctuations, and of the gate noise due to work function fluctuations. These 1/f noise measurements are a strong indicator that the defects at the top HfO2/polycrystalline silicon interface, rather than bulk defects in the high-k layer, are responsible for the noise degradation observed in HfO2 gate dielectrics.
Journal of Nanoscience and Nanotechnology, Feb 1, 2007
In this paper we present experimental evidence for single-electron phenomena in solid-state memor... more In this paper we present experimental evidence for single-electron phenomena in solid-state memories based on silicon nanocrystals as storage elements. The stepwise evolution of the channel current of a written memory cell biased in the subthreshold regime is monitored by means of a purposely designed low noise acquisition system with a bandwidth of 1 kHz. Each channel current step-up is ascribed to a single-electron emission from the silicon nanocrystal to the silicon substrate and each current step-down is ascribed to a single-electron capture from the silicon substrate into the silicon nanocrystal. The effect of the measurement system bandwidth on the detection of singleelectron events is discussed and a procedure for extracting the threshold voltage shift associated to these events is proposed. It is shown that single-electron charging and discharging events in a memory cell with an area of 4 5 × 10 −10 cm 2 can cause threshold voltage shift at room-temperature of the order of several millivolts. Qualitative explanation for the observed threshold voltage shift distribution is given.
We have compared the thermal damage in ultrathin gate SiO2 layers of 5.6 and 3 nm thickness after... more We have compared the thermal damage in ultrathin gate SiO2 layers of 5.6 and 3 nm thickness after intrinsic dielectric breakdown due to constant voltage Fowler-Nordheim stress. The power dissipated through the metal-oxide-semiconductor capacitor during the breakdown transient, measured with high time resolution, strongly decreases with oxide thickness. This is reflected in a noticeable reduction of the thermal damage found in the structure after breakdown. The effect can be explained as the consequence of the lower amount of defects present in the oxide at the breakdown instant and of the occurrence of a softer breakdown in the initial spot. The present data allow us to estimate the power threshold at the boundary between soft and hard breakdown, and they are compared to numerical simulations of heat flow.
32nd European Solid-State Device Research Conference, 2002
breakdown-position dependence of normalized currents in nFETs with 2.4 nm gate oxide is observed ... more breakdown-position dependence of normalized currents in nFETs with 2.4 nm gate oxide is observed after soft and hard breakdowns. This suggests that electron energy is conserved in the soft breakdown path. It is concluded that the observed soft breakdown is best modeled by a lowered oxide barrier in the breakdown conduction path. The static behavior of an nFET immediately after SBD is discussed and tested using the MEDICI device simulator.
The power spectral densities of the current fluctuations through fresh and stressed thin oxide ar... more The power spectral densities of the current fluctuations through fresh and stressed thin oxide are investigated by means of a purposely designed ultra low noise measurement system. It is reported for the first time that the SILC noise spectrum exhibits partially suppressed shot noise down to about 70% with respect to the full shot noise observed for fresh oxide in Fowler-Nordheim regime. It is shown that a single trap assisted tunneling model with a uniform trap distribution in both energy and space is able to justify the observed noise behavior.
We have investigated the dynamics of hard intrinsic dielectric breakdown of gate oxide layers wit... more We have investigated the dynamics of hard intrinsic dielectric breakdown of gate oxide layers with thickness between 35 and 5.6 nm in n+ polycrystalline Si-SiO2-Si metal/oxide/semiconductor capacitors after constant voltage Fowler-Nordheim stress. The buildup of defects in the oxide during the degradation phase was monitored by quasi static C-V measurements. The dynamics of the final breakdown event was followed with high time resolution, allowing to measure voltage, current, and power versus time during the breakdown transient. Transmission electron microscopy data quantifying the damage produced during this transient are reported. Finally, we propose a phenomenological model concerning the dynamics of breakdown with model parameters adjusted on the basis of the experimental data.
In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channe... more In this paper, we report the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide field effect transistors (pMOSFETs) with a Si passivated surface. The gate stack consists of HfO2/SiO2 dielectric with TiN /TaN metal gate. The observed temperature dependence of the gate current indicates that the dominant charge transport mechanism through the gate dielectric consists of Poole-Frenkel conduction. Gate current 1/f noise is more than two orders higher in the case of Ge pMOSFETs when compared to reference Si pMOSFETs. Ge outdiffusion into the gate oxide is the suspected cause for the enhanced Poole-Frenkel conduction and the high gate current 1/f noise in Ge pMOSFETs.
In this paper we critically review and compare experimental methods, based on the Lundstrom model... more In this paper we critically review and compare experimental methods, based on the Lundstrom model, to extract the channel backscattering ratio in nano MOSFETs. Basically two experimental methods are currently used, the most common of them is based on the measurement of the saturation drain current at different temperatures. We show that this method is affected by very poor assumptions and that the extracted backscattering ratio strongly underestimates its actual value posing particular attention to the backscattering actually extracted in nano devices. The second method is based on the direct measurement of the inversion charge by CV characteristics and gets closer to the physics of the backscattering model. We show, through measurements in high mobility p-germanium devices, how the temperature based method gives the same result of the CV based method once that its approximations are removed. Moreover we show that the CV based method uses a number of approximations which are partially inconsistent with the model. In particular we show, with the aid of 2D quantum corrected device simulations, that the value of the barrier lowering obtained through the CV based method is totally inconsistent with the barrier lowering used to correct the inversion charge and that the extracted saturation inversion charge is underestimated.
The temperature dependence of the trap-assisted tunneling (TAT) current component in Ge p + n jun... more The temperature dependence of the trap-assisted tunneling (TAT) current component in Ge p + n junctions has been studied between 25 • C and 140 • C. It is shown that the impact of TAT reduces significantly due to the combination of the negative thermal activation of the TAT-enhancement factor and the exponential increase of the diffusion current with temperature. It is shown that the experimental data can be well described in the frame of the Hurkx analytical model, which allows a fairly easy assessment of the TAT current contribution to the junction leakage current at realistic operation temperatures of Ge CMOS circuits.
I E E E Transactions on Electron Devices, Aug 1, 2012
We developed an analytical model that is able to predict the evolution of the subthreshold slope ... more We developed an analytical model that is able to predict the evolution of the subthreshold slope variability associated with hot carrier (HC) stress. The model assumes that HC stress generates interface states with a Poisson distribution and that the number of HC-induced interface states increases linearly with the HC-induced subthreshold slope variation. We validate the model by means of extensive variability data sets collected on n-channel MOSFETs in 45-and 65-nm CMOS technologies. Furthermore, we investigate the correlation between the threshold voltage and the subthreshold slope fluctuations in order to fully characterize their impact on the subthreshold current variability.
ABSTRACT The on-off fluctuations of the tunnel current in thin oxide MOS structures before breakd... more ABSTRACT The on-off fluctuations of the tunnel current in thin oxide MOS structures before breakdown is a well known phenomenon since 1985. Notwithstanding this, most of the models proposed in the last years to justify the failure of the structure ignore this phenomenon. The physical mechanism responsible for it is not completely clear, even if some possible explanations have been proposed. Some new results, obtained by using a novel characterization tool, are presented in this paper. These results could open new perspectives in the comprehension of the final stage of time dependent breakdown of thin oxides. .
2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012
This paper discusses the low-frequency noise behavior of SiGe-channel bulk FinFETs processed on (... more This paper discusses the low-frequency noise behavior of SiGe-channel bulk FinFETs processed on (100) and (110) Si wafers. A comparison is also made with planar SiGe-channel pMOSFETs. It is shown that for devices with carriers confined in the quantum well, only 1/f noise is observed, dominated by mobility fluctuations. Surprisingly, SiGe pMOSFETs fabricated on (110) Si wafers exhibit the highest mobility but also the highest 1/f noise, corresponding with trapping/detrapping. This is also consistent with the density of interface traps extracted from charge pumping measurements.
The impact of a submonolayer of HfO2 sandwiched between the SiON gate dielectric and the polycrys... more The impact of a submonolayer of HfO2 sandwiched between the SiON gate dielectric and the polycrystalline silicon layer on the low frequency noise of a n-channel metal oxide semiconductor field effect transistor is investigated. Fermi-level pinning at polycrystalline silicon-HfO2 interface acts as a dramatic source of the drain noise due to charge carrier number fluctuations, and of the gate noise due to work function fluctuations. These 1/f noise measurements are a strong indicator that the defects at the top HfO2/polycrystalline silicon interface, rather than bulk defects in the high-k layer, are responsible for the noise degradation observed in HfO2 gate dielectrics.
Journal of Nanoscience and Nanotechnology, Feb 1, 2007
In this paper we present experimental evidence for single-electron phenomena in solid-state memor... more In this paper we present experimental evidence for single-electron phenomena in solid-state memories based on silicon nanocrystals as storage elements. The stepwise evolution of the channel current of a written memory cell biased in the subthreshold regime is monitored by means of a purposely designed low noise acquisition system with a bandwidth of 1 kHz. Each channel current step-up is ascribed to a single-electron emission from the silicon nanocrystal to the silicon substrate and each current step-down is ascribed to a single-electron capture from the silicon substrate into the silicon nanocrystal. The effect of the measurement system bandwidth on the detection of singleelectron events is discussed and a procedure for extracting the threshold voltage shift associated to these events is proposed. It is shown that single-electron charging and discharging events in a memory cell with an area of 4 5 × 10 −10 cm 2 can cause threshold voltage shift at room-temperature of the order of several millivolts. Qualitative explanation for the observed threshold voltage shift distribution is given.
We have compared the thermal damage in ultrathin gate SiO2 layers of 5.6 and 3 nm thickness after... more We have compared the thermal damage in ultrathin gate SiO2 layers of 5.6 and 3 nm thickness after intrinsic dielectric breakdown due to constant voltage Fowler-Nordheim stress. The power dissipated through the metal-oxide-semiconductor capacitor during the breakdown transient, measured with high time resolution, strongly decreases with oxide thickness. This is reflected in a noticeable reduction of the thermal damage found in the structure after breakdown. The effect can be explained as the consequence of the lower amount of defects present in the oxide at the breakdown instant and of the occurrence of a softer breakdown in the initial spot. The present data allow us to estimate the power threshold at the boundary between soft and hard breakdown, and they are compared to numerical simulations of heat flow.
32nd European Solid-State Device Research Conference, 2002
breakdown-position dependence of normalized currents in nFETs with 2.4 nm gate oxide is observed ... more breakdown-position dependence of normalized currents in nFETs with 2.4 nm gate oxide is observed after soft and hard breakdowns. This suggests that electron energy is conserved in the soft breakdown path. It is concluded that the observed soft breakdown is best modeled by a lowered oxide barrier in the breakdown conduction path. The static behavior of an nFET immediately after SBD is discussed and tested using the MEDICI device simulator.
The power spectral densities of the current fluctuations through fresh and stressed thin oxide ar... more The power spectral densities of the current fluctuations through fresh and stressed thin oxide are investigated by means of a purposely designed ultra low noise measurement system. It is reported for the first time that the SILC noise spectrum exhibits partially suppressed shot noise down to about 70% with respect to the full shot noise observed for fresh oxide in Fowler-Nordheim regime. It is shown that a single trap assisted tunneling model with a uniform trap distribution in both energy and space is able to justify the observed noise behavior.
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Papers by Felice Crupi