The Physics and Technology of Amorphous SiO2, 1988
The accurate prediction of thin insulator reliability is of significant importance to the develop... more The accurate prediction of thin insulator reliability is of significant importance to the development of MOS VLSI technologies. In most reliability studies1,5, the time-to-failure tbd and/or the total injected charge prior to breakdown Qbd are measured under high field stresses typically greater than or equal to 8 MV/cm. These data are then extrapolated down to normal operating fields to give a prediction of device wear-out. The important assumptions of this procedure are: a) the phenomena that take place at high fields and eventually lead to oxide failure also occur at the operating field and b) no additional failure mechanisms exist at low fields. These assumptions have been used routinely but never been proven to be valid to our knowledge.
8th International Symposium on Quality Electronic Design (ISQED'07), 2007
This paper presents a fault analysis applied to a novel optical, label-free sensors array for DNA... more This paper presents a fault analysis applied to a novel optical, label-free sensors array for DNA detection. The IFA approach to extract and model the possible defects has been used. A critical equivalent resistance for the possible faults has been defined and it allowed defining the threshold values of current to discriminate the occurrence of the failures mechanisms. Particularly critical
... 1984. E. Sangiorgi, B. Ricco', F. Venturi; to be published. Y. Park, T. Tang, DH Nav... more ... 1984. E. Sangiorgi, B. Ricco', F. Venturi; to be published. Y. Park, T. Tang, DH Navon: "Monte Carlo surface scat-tering simulation in MOSFET structures."; IEEE trans. ... 55., p.645-675, 1983. J. Tang, K. Hess: "Impact ionization of electrons in silicon (steady state).", J. Appl. ...
Device simulation is adopted to investigate the main implications of scaling SOI MOSFETs to gate ... more Device simulation is adopted to investigate the main implications of scaling SOI MOSFETs to gate length well below 0.1.¿m. Effects of the reduction of silicon layer thickness and of the back oxide thickness are discussed. Reduction of the silicon layer thickness is effective in suppressing short channel effects (SCE) by ensuring better gate control of the back interface. Furthermore, the results of Monte Carlo simulations predict, in agreement with recent experiments, a decrease of hot carrier effects. On the other hand, by reducing the silicon layer thickness, an increase of the carrier transit time may be expected.
This paper describes a test chip and an accurate system to measure the injection probability of h... more This paper describes a test chip and an accurate system to measure the injection probability of hot holes from silicon into silicon dioxide, and to extract the corresponding mean free path in the silicon substrate, overcoming some of the difficulties inherent to the measurement of small hole gate currents. The results cover a wide range of substrate and oxide fields, and represent a suitable data set to: 1) extend the use of the simple “lucky electron model” to holes; 2) to verify more complex transport and injection models for holes in MOS devices
... REFERENCES [11 E. Sangiorgi, B. Ricco, and L. Selmi, "Three dimen-sional distribution of... more ... REFERENCES [11 E. Sangiorgi, B. Ricco, and L. Selmi, "Three dimen-sional distribution of CMOS latch-up current", IEEE Electron Device Lett., vol. EDL-8, p.154, 1987. [2] A. G Lewis, RA Martin, TY Huang, JY Chen, 'Three-dimensional effects in CMOS latch-up", IEDM Tech. ...
... distribution of CMOS latch-up current,” IEEE Electron Device Lett., vol. EDL-8, p. 154, 1987.... more ... distribution of CMOS latch-up current,” IEEE Electron Device Lett., vol. EDL-8, p. 154, 1987. A. G. Lewis, R. A. Martin, TY Huang, and J. Y. Chen, “Three-dimensional effects in CMOS latch-up,” in IEDM Tech. Dig., 1986, p. 248. [2]
The Physics and Technology of Amorphous SiO2, 1988
The accurate prediction of thin insulator reliability is of significant importance to the develop... more The accurate prediction of thin insulator reliability is of significant importance to the development of MOS VLSI technologies. In most reliability studies1,5, the time-to-failure tbd and/or the total injected charge prior to breakdown Qbd are measured under high field stresses typically greater than or equal to 8 MV/cm. These data are then extrapolated down to normal operating fields to give a prediction of device wear-out. The important assumptions of this procedure are: a) the phenomena that take place at high fields and eventually lead to oxide failure also occur at the operating field and b) no additional failure mechanisms exist at low fields. These assumptions have been used routinely but never been proven to be valid to our knowledge.
8th International Symposium on Quality Electronic Design (ISQED'07), 2007
This paper presents a fault analysis applied to a novel optical, label-free sensors array for DNA... more This paper presents a fault analysis applied to a novel optical, label-free sensors array for DNA detection. The IFA approach to extract and model the possible defects has been used. A critical equivalent resistance for the possible faults has been defined and it allowed defining the threshold values of current to discriminate the occurrence of the failures mechanisms. Particularly critical
... 1984. E. Sangiorgi, B. Ricco', F. Venturi; to be published. Y. Park, T. Tang, DH Nav... more ... 1984. E. Sangiorgi, B. Ricco', F. Venturi; to be published. Y. Park, T. Tang, DH Navon: "Monte Carlo surface scat-tering simulation in MOSFET structures."; IEEE trans. ... 55., p.645-675, 1983. J. Tang, K. Hess: "Impact ionization of electrons in silicon (steady state).", J. Appl. ...
Device simulation is adopted to investigate the main implications of scaling SOI MOSFETs to gate ... more Device simulation is adopted to investigate the main implications of scaling SOI MOSFETs to gate length well below 0.1.¿m. Effects of the reduction of silicon layer thickness and of the back oxide thickness are discussed. Reduction of the silicon layer thickness is effective in suppressing short channel effects (SCE) by ensuring better gate control of the back interface. Furthermore, the results of Monte Carlo simulations predict, in agreement with recent experiments, a decrease of hot carrier effects. On the other hand, by reducing the silicon layer thickness, an increase of the carrier transit time may be expected.
This paper describes a test chip and an accurate system to measure the injection probability of h... more This paper describes a test chip and an accurate system to measure the injection probability of hot holes from silicon into silicon dioxide, and to extract the corresponding mean free path in the silicon substrate, overcoming some of the difficulties inherent to the measurement of small hole gate currents. The results cover a wide range of substrate and oxide fields, and represent a suitable data set to: 1) extend the use of the simple “lucky electron model” to holes; 2) to verify more complex transport and injection models for holes in MOS devices
... REFERENCES [11 E. Sangiorgi, B. Ricco, and L. Selmi, "Three dimen-sional distribution of... more ... REFERENCES [11 E. Sangiorgi, B. Ricco, and L. Selmi, "Three dimen-sional distribution of CMOS latch-up current", IEEE Electron Device Lett., vol. EDL-8, p.154, 1987. [2] A. G Lewis, RA Martin, TY Huang, JY Chen, 'Three-dimensional effects in CMOS latch-up", IEDM Tech. ...
... distribution of CMOS latch-up current,” IEEE Electron Device Lett., vol. EDL-8, p. 154, 1987.... more ... distribution of CMOS latch-up current,” IEEE Electron Device Lett., vol. EDL-8, p. 154, 1987. A. G. Lewis, R. A. Martin, TY Huang, and J. Y. Chen, “Three-dimensional effects in CMOS latch-up,” in IEDM Tech. Dig., 1986, p. 248. [2]
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