ABSTRACT In this work we will present the experimental path followed to optimize the dynamic ON-r... more ABSTRACT In this work we will present the experimental path followed to optimize the dynamic ON-resistance (RDS-ON) dispersion and to reduce the threshold voltage shift of AlGaN/GaN transistors grown on 200 mm Si wafers. Firstly, it will be demonstrated that a SiN gate dielectric grown by means of plasma enhanced atomic layer deposition (PEALD) instead of rapid thermal chemical vapor deposition (RTCVD) reduces threshold voltage (Vth) shift induced by negative gate bias and the gate leakage. Secondly, the dynamic RDS-ON dispersion of two wafers with same gate dielectric (PEALD SiN) but different in situ metal organic chemical vapor deposition (MOCVD) capping layer, GaN or SiN, is compared. Results will show that the traps at the surface causing the RDS-ON dispersion can drastically be reduced by using in situ MOCVD SiN.
2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS), 2016
... Authors: Heyns, Marc Bellenger, Florence Brammertz, Guy Caymax, Matty De Gendt, Stefan De Jae... more ... Authors: Heyns, Marc Bellenger, Florence Brammertz, Guy Caymax, Matty De Gendt, Stefan De Jaeger, Brice Delabie, Annelies Eneman, Geert ... Geoffrey Scarrozza, Marco Simoen, Eddy Van Elshocht, Sven Vandenberghe, William Vandooren, Anne Verhulst, Anne Wang, Wei-E. ...
This work gives an overview of recent advances in IMEC's Ge pFET technology. Thin (330 nm) Ge epi... more This work gives an overview of recent advances in IMEC's Ge pFET technology. Thin (330 nm) Ge epitaxial layers, selectively grown in Shallow-Trench Isolation (STI)-patterned wafers are presented. These thin layers show a 70% higher area junction leakage than thick Ge virtual substrates at 1 V bias, but the presence of STI reduces the leakage at the isolation perimeter by a factor of 5.Low-temperature epitaxial growth of silicon for gate dielectric applications is proposed as a solution to reduce the Equivalent Oxide Thickness (EOT). It is shown that a low-temperature (350 °C) recipe with a Si3H8 precursor leads to reduced Ge segregation towards the Si surface, and facilitates EOT scaling to 1 nm and below.Junction leakage generated under the transistor's spacer regions is analysed, and it is shown that this is the dominant junction leakage component in short-channel Ge technologies. As the leakage scales with electric field, reducing the supply voltage is suggested as a solution to keep this leakage component under control.
Effective mobility measurements have been made at 4.2 K on high performance high-k gated germaniu... more Effective mobility measurements have been made at 4.2 K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from
2010 14th International Workshop on Computational Electronics, 2010
In this paper transport in the inversion layer of a Ge channel pMOS structure is studied using a ... more In this paper transport in the inversion layer of a Ge channel pMOS structure is studied using a full 6-band k·p Monte Carlo simulator. In addition to the usual bulk-scattering mechanisms, which are calibrated and validated against the available experimental data, effects of the gate stack are included via SO phonons and surface roughness scattering. Through careful calibration and consideration
ABSTRACT In this work we will present the experimental path followed to optimize the dynamic ON-r... more ABSTRACT In this work we will present the experimental path followed to optimize the dynamic ON-resistance (RDS-ON) dispersion and to reduce the threshold voltage shift of AlGaN/GaN transistors grown on 200 mm Si wafers. Firstly, it will be demonstrated that a SiN gate dielectric grown by means of plasma enhanced atomic layer deposition (PEALD) instead of rapid thermal chemical vapor deposition (RTCVD) reduces threshold voltage (Vth) shift induced by negative gate bias and the gate leakage. Secondly, the dynamic RDS-ON dispersion of two wafers with same gate dielectric (PEALD SiN) but different in situ metal organic chemical vapor deposition (MOCVD) capping layer, GaN or SiN, is compared. Results will show that the traps at the surface causing the RDS-ON dispersion can drastically be reduced by using in situ MOCVD SiN.
2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS), 2016
... Authors: Heyns, Marc Bellenger, Florence Brammertz, Guy Caymax, Matty De Gendt, Stefan De Jae... more ... Authors: Heyns, Marc Bellenger, Florence Brammertz, Guy Caymax, Matty De Gendt, Stefan De Jaeger, Brice Delabie, Annelies Eneman, Geert ... Geoffrey Scarrozza, Marco Simoen, Eddy Van Elshocht, Sven Vandenberghe, William Vandooren, Anne Verhulst, Anne Wang, Wei-E. ...
This work gives an overview of recent advances in IMEC's Ge pFET technology. Thin (330 nm) Ge epi... more This work gives an overview of recent advances in IMEC's Ge pFET technology. Thin (330 nm) Ge epitaxial layers, selectively grown in Shallow-Trench Isolation (STI)-patterned wafers are presented. These thin layers show a 70% higher area junction leakage than thick Ge virtual substrates at 1 V bias, but the presence of STI reduces the leakage at the isolation perimeter by a factor of 5.Low-temperature epitaxial growth of silicon for gate dielectric applications is proposed as a solution to reduce the Equivalent Oxide Thickness (EOT). It is shown that a low-temperature (350 °C) recipe with a Si3H8 precursor leads to reduced Ge segregation towards the Si surface, and facilitates EOT scaling to 1 nm and below.Junction leakage generated under the transistor's spacer regions is analysed, and it is shown that this is the dominant junction leakage component in short-channel Ge technologies. As the leakage scales with electric field, reducing the supply voltage is suggested as a solution to keep this leakage component under control.
Effective mobility measurements have been made at 4.2 K on high performance high-k gated germaniu... more Effective mobility measurements have been made at 4.2 K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from
2010 14th International Workshop on Computational Electronics, 2010
In this paper transport in the inversion layer of a Ge channel pMOS structure is studied using a ... more In this paper transport in the inversion layer of a Ge channel pMOS structure is studied using a full 6-band k·p Monte Carlo simulator. In addition to the usual bulk-scattering mechanisms, which are calibrated and validated against the available experimental data, effects of the gate stack are included via SO phonons and surface roughness scattering. Through careful calibration and consideration
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Papers by Brice de Jaeger