Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005., 2005
High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technol... more High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate devices with narrow fins. This makes selective epitaxial growth of Si in the S/D regions, the enabling process for multiple gate CMOS technologies. In this paper, we ...
Abstract We investigate scalability, performance and variability of high aspect ratio trigate Fin... more Abstract We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193nm immersion lithography and conventional dry etch. FinFETs with fin widths down to 5nm are achieved with record aspect ratios of 13. Excellent nMOS and pMOS ...
2007 IEEE International Electron Devices Meeting, 2007
Excellent performance (995 muA/mum at Ioff=94 n A/mum and Vdd=lV) and short channel effect contro... more Excellent performance (995 muA/mum at Ioff=94 n A/mum and Vdd=lV) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193 nm immersion lithography and dry etch. PVD TiN electrodes on Hf SiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both
At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short chan... more At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 [1,2]]. In addition, their undoped channels allow a substantial reduction of the threshold voltage (VT) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width (Wfin) and gate length (Lg) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance (RSD) engineering become more challenging.In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial RSD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10nm.
Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005., 2005
High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technol... more High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate devices with narrow fins. This makes selective epitaxial growth of Si in the S/D regions, the enabling process for multiple gate CMOS technologies. In this paper, we ...
Abstract We investigate scalability, performance and variability of high aspect ratio trigate Fin... more Abstract We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193nm immersion lithography and conventional dry etch. FinFETs with fin widths down to 5nm are achieved with record aspect ratios of 13. Excellent nMOS and pMOS ...
2007 IEEE International Electron Devices Meeting, 2007
Excellent performance (995 muA/mum at Ioff=94 n A/mum and Vdd=lV) and short channel effect contro... more Excellent performance (995 muA/mum at Ioff=94 n A/mum and Vdd=lV) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193 nm immersion lithography and dry etch. PVD TiN electrodes on Hf SiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both
At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short chan... more At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 [1,2]]. In addition, their undoped channels allow a substantial reduction of the threshold voltage (VT) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width (Wfin) and gate length (Lg) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance (RSD) engineering become more challenging.In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial RSD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10nm.
Uploads
Papers by Monja Kaiser