Yvon Savaria
École Polytechnique de Montréal, Génie électrique, Faculty Member
The reliability and lifetime of systems-on-chip (SoCs) are being seriously threatened by thermal issues. In modern SoCs, dynamic thermal management (DTM) uses the thermal data captured by thermal sensors to constantly track the hot spots... more
The reliability and lifetime of systems-on-chip (SoCs) are being seriously threatened by thermal issues. In modern SoCs, dynamic thermal management (DTM) uses the thermal data captured by thermal sensors to constantly track the hot spots and thermal peak locations in real time. Estimating peak temperatures and the location of these peaks can play a crucial role for DTM systems, as temperature underestimation can cause SoCs to fail and have shortened lifetime. In this paper, a novel sensor allocation algorithm (called thermal gradient tracker, TGT), based on the recursive elimination of regions that likely do not contain any thermal peaks, is proposed for determining regions that potentially contain thermal peaks. Then, based on an empirical source temperature detection technique called GDS (gradient direction sensor), a hybrid algorithm for detecting the position and temperature of thermal peaks is also proposed to increase the accuracy of temperature sensing while trying to keep th...
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Programmable network data planes have extended the capabilities of packet processing in network devices by allowing custom processing pipelines and agnostic packet processing. While a variety of applications can be implemented on current... more
Programmable network data planes have extended the capabilities of packet processing in network devices by allowing custom processing pipelines and agnostic packet processing. While a variety of applications can be implemented on current programmable data planes, there are significant constraints due to hardware limitations. One way to meet these constraints is by optimizing data plane programs. Program optimization can be achieved by specializing code that leverages architectural specificity or by compilation passes. In the case of programmable data planes, to respond to the varying requirements of large set of applications, data plane programs can target different architectures. This leads to difficulties when developers want to reuse the code. One solution to that is to use compiler optimization techniques. We propose performing data plane program specialization to reduce the generated program size. To this end, we propose to specialize programs written in P4, a Domain Specific L...
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In this article, the concept of a 22-kW microwave-powered unmanned aerial vehicle is presented. Its system architecture is analyzed and modeled for wirelessly transferring microwave power to the flying UAVs. The microwave system... more
In this article, the concept of a 22-kW microwave-powered unmanned aerial vehicle is presented. Its system architecture is analyzed and modeled for wirelessly transferring microwave power to the flying UAVs. The microwave system transmitting power at a 35 GHz frequency was found to be suitable for low-cost and compact architectures. The size of the transmitting and receiving systems are optimized to 108 m2 and 90 m2, respectively. A linearly polarized 4 × 2 rectangular microstrip patch antenna array has been designed and simulated to obtain a high gain, high directivity, and high efficiency in order to satisfy the power transfer requirements. The numerically simulated gain, directivity, and efficiency of the proposed patch antenna array are 13.4 dBi, 14 dBi, and 85%, respectively. Finally, a rectifying system (rectenna) is optimized using the Agilent advanced design system (ADS) software as a microwave power receiving system. The proposed rectenna at the core of the system has an ef...
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As a wide bandgap semiconductor, Gallium Nitride (GaN) device proves itself as a suitable candidate to implement high temperature (HT) integrated circuits. GaN500 is a technology available from the National Research Council of Canada to... more
As a wide bandgap semiconductor, Gallium Nitride (GaN) device proves itself as a suitable candidate to implement high temperature (HT) integrated circuits. GaN500 is a technology available from the National Research Council of Canada to serve RF applications. However, this technology has the potential to boost HT electronics to higher ranges of operating temperatures and to higher levels of integration. This paper summarizes the outcome of five years of research investigating the implementation of GaN500-based circuits to support HT applications such as aerospace missions and deep earth drilling. More than 15 integrated circuits were implemented and tested. We performed the HT characterization of passive elements integrated in GaN500 including resistors, capacitors, and inductors up to 600 °C. Moreover, we developed for the first time several digital circuits based on GaN500 technology, including logic gates (NOT, NAND, NOR), ring oscillators, D Flip-Flop, Delay circuits, and voltag...
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The P4 language has drastically changed the networking field as it allows to quickly describe and implement new networking applications. Although a large variety of applications can be described with the P4 language, current programmable... more
The P4 language has drastically changed the networking field as it allows to quickly describe and implement new networking applications. Although a large variety of applications can be described with the P4 language, current programmable switch architectures impose significant constraints on P4 programs. To address this shortcoming, FPGAs have been explored as potential targets for P4 applications. P4 applications are described using three abstractions: a packet parser, match-action tables, and a packet deparser, which reassembles the output packet with the result of the match-action tables. While implementations of packet parsers and match-action tables on FPGAs have been widely covered in the literature, no general design principles have been presented for the packet deparser. Indeed, implementing a high-speed and efficient deparser on FPGAs remains an open issue because it requires a large amount of interconnections and the architecture must be tailored to a P4 program. As a resu...
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Convolutional Neural Networks (CNNs) have a major impact on our society, because of the numerous services they provide. These services include, but are not limited to image classification, video analysis, and speech recognition. Recently,... more
Convolutional Neural Networks (CNNs) have a major impact on our society, because of the numerous services they provide. These services include, but are not limited to image classification, video analysis, and speech recognition. Recently, the number of researches that utilize FPGAs to implement CNNs are increasing rapidly. This is due to the lower power consumption and easy reconfigurability that are offered by these platforms. Because of the research efforts put into topics, such as architecture, synthesis, and optimization, some new challenges are arising for integrating suitable hardware solutions to high-level machine learning software libraries. This paper introduces an integrated framework (CNN2Gate), which supports compilation of a CNN model for an FPGA target. CNN2Gate is capable of parsing CNN models from several popular high-level machine learning libraries, such as Keras, Pytorch, Caffe2, etc. CNN2Gate extracts computation flow of layers, in addition to weights and biases...
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This paper presents a hierarchical framework to model, analyze, and estimate digital design vulnerability to soft errors due to Single Event Transients (SETs) based on Satisfiability Modulo Theories (SMTs). New strategies to mitigate SETs... more
This paper presents a hierarchical framework to model, analyze, and estimate digital design vulnerability to soft errors due to Single Event Transients (SETs) based on Satisfiability Modulo Theories (SMTs). New strategies to mitigate SETs with minimum area overhead is proposed by selectively hardening vulnerable nodes in the design. The reliability of a circuit can be improved by 30% with less than 5% area overhead.
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Soft errors due to Single Event Transients (SETs) have become one of the most challenging issues that impact the reliability of modern microelectronic systems at terrestrial altitudes. This is mainly due to the progressive shrinking of... more
Soft errors due to Single Event Transients (SETs) have become one of the most challenging issues that impact the reliability of modern microelectronic systems at terrestrial altitudes. This is mainly due to the progressive shrinking of device sizes. Traditionally, the analysis of SETs has been carried out by simulations and experimental analysis. However, these techniques are resource hungry and require full details of the design structure and SET characteristics. This paper develops a hierarchical framework for formal analysis of SET propagation by (1) introducing Register Transfer Level (RTL) abstraction and modeling approaches of the underlying behavior of SET propagation using Multiway Decision Graphs (MDGs); and (2) investigating SET propagation conditions at RTL using a formal model checker. In order to illustrate the practical utilization of our work, e have analyzed different RTL combinational designs. Experimental results demonstrate the proposed framework is orders of magnitude faster than other comparable contemporary techniques. Moreover, for the first time, a decision graph based technique s developed to analyze multiplier designs.
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ABSTRACT This paper presents a new experimental setup (to our knowledge, the first ever) and results obtained with that setup from which we report extra combinational delays in an SRAM FPGA (Virtex-5) due to transient ionizing radiations.... more
ABSTRACT This paper presents a new experimental setup (to our knowledge, the first ever) and results obtained with that setup from which we report extra combinational delays in an SRAM FPGA (Virtex-5) due to transient ionizing radiations. The results, obtained by proton irradiation at the TRIUMF laboratory, show that our setup can detect extra combinatorial delays as small as 40 ps, and that delays of more than 400 ps can affect the targeted FPGA. These results strongly suggest that delay faults can potentially be induced by transient ionizing radiations.
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This paper proposes a real-time thermal monitoring method using embedded integrated sensor interfaces dedicated to industrial integrated system applications. Industrial sensor interfaces are complex systems that involve analog and mixed... more
This paper proposes a real-time thermal monitoring method using embedded integrated sensor interfaces dedicated to industrial integrated system applications. Industrial sensor interfaces are complex systems that involve analog and mixed signals, where several parameters can influence their performance. These include the presence of heat sources near sensitive integrated circuits, and various heat transfer phenomena need to be considered. This creates a need for real-time thermal monitoring and management. Indeed, the control of transient temperature gradients or temperature differential variations as well as the prediction of possible induced thermal shocks and stress at early design phases of advanced integrated circuits and systems are essential. This paper addresses the growing requirements of microelectronics applications in several areas that experience fast variations in high-power density and thermal gradient differences caused by the implementation of different systems on th...
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A fully-integrated data transmission system based on gallium nitride (GaN) high-electron-mobility transistor (HEMT) devices is proposed. This system targets high-temperature (HT) applications, especially those involving pressure and... more
A fully-integrated data transmission system based on gallium nitride (GaN) high-electron-mobility transistor (HEMT) devices is proposed. This system targets high-temperature (HT) applications, especially those involving pressure and temperature sensors for aerospace in which the environmental temperature exceeds 350 °C. The presented system includes a front-end amplifying the sensed signal (gain of 50 V/V), followed by a novel analog-to-digital converter driving a modulator exploiting the load-shift keying technique. An oscillation frequency of 1.5 MHz is used to ensure a robust wireless transmission through metallic-based barriers. To retrieve the data, a new demodulator architecture based on digital circuits is proposed. A 1 V amplitude difference can be detected between a high-amplitude (data-on) and a low-amplitude (data-off) of the received modulated signal. Two high-voltage supply levels (+14 V and −14 V) are required to operate the circuits. The layout of the proposed system ...
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ABSTRACT This paper proposes a fully integrated asynchronous step-down switched capacitor DC-DC conversion structure. The circuit uses a fully digital asynchronous state machine as the heart of the control circuitry. To minimize the... more
ABSTRACT This paper proposes a fully integrated asynchronous step-down switched capacitor DC-DC conversion structure. The circuit uses a fully digital asynchronous state machine as the heart of the control circuitry. To minimize the switching losses, the asynchronous controller scales the switching frequency of the converter according to the load. It also turns on additional parallel switches when needed. This circuit regulates load voltages from 300 mV to 1.1 V derived from a 1.2 V input voltage. A total of 350 pF on chip capacitance was implemented to support a maximum of 250 μW load power, while providing efficiencies up to 80%. The circuit validating the proposed concepts was implemented in 0.13 μm CMOS technology.
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Page 1. Architecture ofa HyperTransport Tunnel Ami Castonguay and Yvon Savaria Ecole Polytechnique de Montreal CP 6079, succ. ... The link width varies from 2 to 32 bits, and all links are protected with a periodically inserted Cyclic... more
Page 1. Architecture ofa HyperTransport Tunnel Ami Castonguay and Yvon Savaria Ecole Polytechnique de Montreal CP 6079, succ. ... The link width varies from 2 to 32 bits, and all links are protected with a periodically inserted Cyclic Redundancy Check (CRC) to II. ...
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Research Interests: DFT and Fault Tolerant
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An efficient low power protection scheme for thin gate oxide of high voltage (HV) DMOS transistor is presented. To prevent gate-oxide breakdown and protect HV transistor, the voltage controlling its gate must be within 5 V from the HV... more
An efficient low power protection scheme for thin gate oxide of high voltage (HV) DMOS transistor is presented. To prevent gate-oxide breakdown and protect HV transistor, the voltage controlling its gate must be within 5 V from the HV supply. Thus signals from the low voltage domain must be level shifted to control the gate of this transistor. Usually this level
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ABSTRACT Image pyramids are multi-scale representations of images, and their calculation is computationally intensive. They can be a main bottleneck in image processing and computer vision tasks such as edge detection and feature... more
ABSTRACT Image pyramids are multi-scale representations of images, and their calculation is computationally intensive. They can be a main bottleneck in image processing and computer vision tasks such as edge detection and feature extraction. Thus, high speed computation of image pyramids is necessary. Moreover, when these algorithms are intended for embedded systems, other requirements such as area and energy consumption need to be satisfied. This paper presents a customized processor design to accelerate the execution of a stack of Gaussian low-pass filters. Using an instruction extension language, we added custom instructions to a 32-bit RISC-based configurable processor. We use three techniques to improve performance: operator fusion, single-instruction multiple-data vectorization and data reuse. The proposed processor achieves 12.3× speedup compared to the base processor, with 19% hardware overhead. The estimated improvement in energy consumption is 10.3×. The paper also presents the implementation results for the computation of a modified Gaussian pyramid in a tone mapping algorithm.
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In this paper, we describe a sub 1 V bandgap voltage reference (BGR) in CMOS technology. The proposed topology is based on a current-mode bandgap structure that uses a transimpedance amplifier. A feedback control in the bandgap produces... more
In this paper, we describe a sub 1 V bandgap voltage reference (BGR) in CMOS technology. The proposed topology is based on a current-mode bandgap structure that uses a transimpedance amplifier. A feedback control in the bandgap produces temperature compensation between a PTAT (Proportional To Absolute Temperature) current and a CTAT (Conversely proportional To Absolute Temperature) current derived from a nMOS threshold voltage. The proposed circuit was verified by extensive circuit simulations, using models, of a standard 0.18 μm CMOS technology, with a power supply of 1 V. The variations of the output voltage over a typical temperature range (0 to 100°C) were simulated to be less than 1%.
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The paper proposes a novel multi-layer AMBA high-speed bus (AHB) infrastructure designed to sustain a clock frequency of more than 2 GHz, which remarkably provides up to 4 giga data transfers per second of throughput. The interconnect... more
The paper proposes a novel multi-layer AMBA high-speed bus (AHB) infrastructure designed to sustain a clock frequency of more than 2 GHz, which remarkably provides up to 4 giga data transfers per second of throughput. The interconnect matrix is achieved through a collection of high-performance bridges that serialize transfers toward a high-throughput shared-memory. As a result, we guarantee a maximum
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Phase-locked loops (PLL) are important in numerous applications such as frequency synthesis and clock recovery. As the operating frequency of these devices increases, they are becoming more difficult to design. The classic block diagram... more
Phase-locked loops (PLL) are important in numerous applications such as frequency synthesis and clock recovery. As the operating frequency of these devices increases, they are becoming more difficult to design. The classic block diagram representation of a PLL is shown in ...
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This paper presents an efficient low power protection technique for thin gate oxide of DMOS transistors. By connecting a capacitive divider structure to the floating gate node of a DMOS transistor, its effective gate oxide thickness is... more
This paper presents an efficient low power protection technique for thin gate oxide of DMOS transistors. By connecting a capacitive divider structure to the floating gate node of a DMOS transistor, its effective gate oxide thickness is increased, and a protection from breakdown due to high voltages (HV) applied to its gate is achieved. Several HV circuits, including: positive voltage doubler and level-up shifter suitable for ultrasound sensing systems are built successfully around this technique. These circuits were implemented with the 0.8 mum CMOS/DMOS HV DALSA process. Experimental results prove the good functionality of the designed HV circuits using the proposed protection technique for voltages up to 120V.