System on a Chip

The design of scalable and reliable interconnection net-works for System on Chips (SoCs) introduce new design constraints not present in current multicomputer systems. Although regular topologies are preferred for building NoCs, heterogeneous blocks, fabrication faults and reliabil-ity ...

We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Math- works’ Simulink c environment,for functional specification and analysis of performance,criteria such as timing (latency and throughput) and power,dissipation. The flow can exploit trade-offs between,software and hardware,as well as between digital and analog implemen- tations, and it can

System-on-chip (SoC) architectures are called to be the platform for an ever increasing number of interactive applications. One of the most time- consuming tasks is to define communication interfaces between the different components through a number of scattered heterogeneous processing nodes. That is not only a complex task, but also very specific to a certain implementation, which may limit the flexibility of the system, and makes the solutions difficult to reuse. In this paper, we describe how the distributed systems paradigm can be extended to provide a unified abstraction for both hardware and software components. Moreover, based on that abstraction, we define a low-overhead system-wide communication architecture that offers communication transparency between all kinds of components. Since the architecture is highly compatible with standard distributed object software systems, it also allows seamless interaction with any other kind of external network.

This paper presents a fault injection platform that is currently developed and used to perform soft-error dependability analysis and hardening of complex SoCs. Primarily, it is oriented toward safety analysis, safety requirement conformance testing and hardening of complex SoCs. This platform makes use of clusters of hardware emulation resources available for SoC verification to achieve massive faults injection capabilities. It is able to distribute fault injection campaigns across multiple heterogeneous emulation platforms to achieve high fault coverage. It is able to virtually handle almost any circuit size and is designed to support all kind of designs. We present the first results obtained on a small design, the Leon2 IP, on which exhaustive fault injection have been performed.

The Blue Genet/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPCt cores, high-performance

Thermoplastics are highly attractive substrate materials for microfluidic systems, with important benefits in the development of low cost disposable devices for a host of bioanalytical applications. While significant research activity has been directed towards the formation of microfluidic components in a wide range of thermoplastics, sealing of these components is required for the formation of enclosed microchannels and other microfluidic

In this paper, we present a fast cycle-accurate instruction set simulator (CA-ISS) for system-on-chip development based on QEMU and SystemC. Even though most state-of-the-art commercial tools have tried very hard to provide all the levels of details to satisfy the different requirements of the software designer, the hardware designer, and even the system architect, the hardware/software co-simulation speed is dramatically slow when co-simulating the hardware models at the register-transfer level (RTL) with a full-fledged operating system (OS). Our experimental results show that the combination of QEMU and SystemC can make the co-simulation at the CA level much faster than the conventional RTL simulation, even with a full-fledged operating system up and running. Furthermore, the statistics indicate that with every instruction executed and every memory accessed since power-on traced at the CA level, it takes 28m15.804s on average to boot up a full-fledged Linux kernel, even on a personal computer. Compared to the kernel boot time reported by Xilinx and SiCortex, the proposed CA-ISS is about 6.09 times faster compared to “SystemC without trace” of Xilinx and about 30.32 times faster compared to “SystemC models converted from RTL” of SiCortex. The main contributions of this paper are threefold: 1) a hardware/software co-simulation environment capable of running a full-fledged OS at the early stage of the electronic system level design flow at an acceptable simulation speed is proposed; 2) a virtual platform constructed using the proposed CA-ISS as the processor model can be used to estimate the performance of a target system from system perspective, which all the previous works, such as QEMU-SystemC, do not provide; and 3) such a virtual platform also provides the modeling capability from the transaction level down to the CA level or the other way around.

There are many portable devices applications implemented in System On a Chip (SOC) technology, which need to have a safety operation in extreme conditions for voltage power supplies. Due to that, a good voltage level power supply evaluation is required. This paper proposes a possible design for bandgap reference (BGR) used to generate multiple reference voltage levels for a Power-On Reset (POR) circuit. In this way, a reduced sensitivity to temperature and various process variations is achieved for the POR voltage threshold levels. The BGR circuit has been designed, simulated, and implemented. The results show that the reference voltage VREF has only a 5% variation under the temperature range from -55.DEG.C. to 125.DEG.C. The power consumption is 40 uW considering a 3.3 V power supply.