VLSI

This paper presents a new intensity-to-time processing paradigm suitable for very large scale integration (VLSI) computational sensor implementation of global operations over sensed images. Global image quantities usually describe images with fewer data. When computed at the point of sensing, global quantities result in a low-latency performance due to the reduced data transfer requirements between an image sensor and a processor. The global quantities also help global top-down adaptation: the quantities are continuously computed on-chip, and are readily available to sensing for adaptation. As an example, we have developed a sorting image computational sensor-a VLSI chip which senses an image and sorts all pixel by their intensities. The first sorting sensor prototype is a 21 2 2 2 26 array of cells. It receives an image optically, senses it, and computes the image's cumulative histogram-a global quantity which can be quickly routed off chip via one pin. In addition, the global cumulative histogram is used internally on-chip in a top-down fashion to adapt the values in individual pixel so as to reflect the index of the incoming light, thus computing an "image of indices." The image of indices never saturates and has a uniform histogram.

This paper describes the development of a VLSI device that provides memory system self-testing and redundancy without incurring the overhead penalties of error-correction coding or page-swapping techniques. This device isolates hard errors in system memory by writing a true and complement pattern to each system memory location. Locations from an on-chip fully associative cache are then mapped into the address space in place of faulty locations. Since substitutions take place at the memory word level, this method is more efficient than page swapping. Access to the on-chip cache occurs in parallel with access to system memory, so memory access time is not increased, as it is with error detection and correction (EDAC). Analysis shows that this device can extend the mission time of a nonredundant memory system by as much as 35 times. and digital design for radar signal processing systems. He is currently an Associate Department Head in MITRE'S VLSI/VHSIC

This work addresses the problem of low power design in high-level synthesis in the scenario of the resources operating at multiple voltages. The problem of resource-and-latency constrained scheduling is tackled and a novel methodology for scheduling as well as design space exploration is proposed. The proposed methodology achieves maximal power reduction of functional units by identifying the maximal parallelism of power hungry operators in resource-constrained/time-constrained designs. A novel scheme is devised for recognizing the ''zones'' of parallel operators that result in maximal power savings when rescheduled to lower voltages. The proposed methodology is developed in the framework of a modified stochastic evolution mechanism in order to tame the computational complexity. The proposed scheduling technique is extremely fast and it runs in Oðn 2 Þ; where n is the number of the nodes in the data flow graph of the design. This is the fastest reported time of scheduling algorithms for resourceand-latency constrained scheduling with resources operating at multiple voltages. The algorithm produces results within accuracy of 3-5% of the integer-linear-programming based (i.e., exponential-timecomplexity) method. The details and the analysis of the results on the standard high-level synthesis benchmarks are provided. Further, analysis of schedules is given for considering generation of control signals for switching the resources. This is the first work to consider such analysis besides proposing an efficient algorithm. r

V. SUMMARY We have given parallel algorithms for recognizing and parsing context-free languages on a hypercube of p PE's, 1 5 p 5 n. The algorithms are both time-wise and space-wise optimal with respect to the most efficient sequential algorithm. The recognition algorithms were ...

Orthogonal variable spreading factor (OVSF) codes are standard in third generation UMTS cellular systems. The efficient generation of these codes is essential for reducing the area and power of wireless transceivers. In this paper, the basic properties of this family of codes are analyzed from an RTL perspective and two efficient hardware code generators are proposed. Tradeoffs and design solutions as well as low power considerations are discussed. These results represent the first reported implementation of an OVSF code generator. 1 *

Less than 116 ps overall clock skew has been achieved across the 15.02 mm/spl times/15.03 mm die by balanced clock path routing and differential clock signal distribution in the global clock tree of 300 MHz 128-bit 2-way superscalar microprocessor. The shared clock wire configuration and clock buffer layout patterns over the whole die enhance the clock skew insensitivity to process

We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8X over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5X. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7X using a 200 mV swing.

To subdivide the axis k into 2 new axes p and q, we place k=p+qN/r with p=0,1, ... , N/r s-1, s=0,1, ... ,logrN-1 and q = 0,1,...., r -1. Therefore, X(k) is replaced using new indices p and q where x [n] is the input sequence, X[k] is the output sequence, N is the transform length, w: k = e-j(2tr/N)nk is called the twiddle factor in the butterfly structure, and j2=_1. Both x [n] and X [k] are complex valued number sequences.

The scaled Chinese Remainder Theorem (CRT) is a very useful tool for the simplification of RNS to binary converters. The main drawback of this methodology is related to the use of large look-up tables that store the correspondence among the modular numbers and the corresponding scaled terms of the CRT. This fact limits the maximum speed allowed by this approach. In this paper a new method for the computation of the scaled factors is presented. It allows the computation of the scaled CRT output by using very small look-up tables implemented by conventional logic and simple and fast structures, that work in parallel. The only assumption made in order to develop the new algorithm is that the moduli must be odd

A joint sampling-time error and channel skew background calibration technique for time interleaved analog to digital converters (TI-ADC) is presented. The technique is aimed at applications in dual-polarization QPSK/QAM receivers for coherent optical communications at high data rates (e.g., 40Gb/s and beyond). Unlike previous proposals, the calibration algorithm introduced here is used to jointly compensate for samplingtime and channel skew errors. Estimates of the gradient of the mean squared error (MSE) or the bit error rate (BER) with respect to the sampling phases of the different signal lanes and interleaves are computed and used to iteratively minimize a cost function (i.e., MSE or BER). Computer simulations demonstrate the excellent behavior of the proposed compensation technique. The calibration algorithm can be implemented with minimal hardware requirements and with a slow clock. This allows power dissipation in a CMOS VLSI implementation to be minimized.

In this paper, the verification strategy of PROVER environment is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). PROVER is a rulebased framework for formal hardware verification. The environment supports verification at different levels of hardware specification. Verification strategy is illustrated in this paper using Carry select adder as a case study. Ref er en c e s (1) Elleithy, "Formal Hardware Verification: of VLSI Architectures: Current Status and Future directions" in T I-PC3.3

The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties permit the efficient estimation of the inductive characteristics of power distribution grids. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed performance distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground lines are considered. In the first scenario, the total area occupied by the grid lines is maintained constant and the grid inductance versus grid resistance tradeoff is evaluated as the width of the grid lines varies. In the second scenario, the metal area of the grid is maintained constant and the grid inductance versus grid area tradeoff is investigated. In both cases, the grid inductance increases virtually linearly with line width, rising more then eightfold for a tenfold increase in line width. The grid resistance and grid area, however, decrease relatively slowly with line width. This decrease in grid resistance and area is limited to a factor of two under assumed interconnect characteristics.

For a vision based vehicle guidance system a compact image processing wlit has been developed which extracts straight lines as symbols for the street boundaries. This unit consists of two ASICs for the segmentation of symbols and a micro controller for high level processing. The implemented sequence of algorithms comprises gradient operation. edge thinning. line verification, Hough transformation and a d e based post processing. Although the image processing unit is originally developed for vehicle guidance the hardware can be used for other industrial and robotic applications as well.

In this paper, the Simulated Evolution algorithm (SimE) is engineered to solve the optimization problem of multi-objective VLSI netlist bi-partitioning. The multi-objective version of the problem is addressed in which, power dissipation, timing performance, as well as cut-set are optimized while Balance is taken as a constraint. Fuzzy rules are used in order to design the overall multiobjective cost function that integrates the costs of three objectives in a single overall cost value. Fuzzy goodness functions are designed for delay and power, and proved efficient. A series of experiments are performed to evaluate the efficiency of the algorithm. ISCAS-85/89 benchmark circuits are used and experimental results are reported and compared to earlier algorithms like GA and TS.

The paper presents a study on the introduction of pipelining in parallel VLSI multipliers, built according to the column compression (CC) design techniques. A number of CC multiplier schemes have been proposed in the literature, aimed at reducing the number of stages of adders necessav to compute a multiplication. More recently CC multiplier schemes aimed at optimising the required silicon area, the regularity and the locality of the interconnections among the adders, have been proposed [5]. The paper affords the introduction ofpipelining in these last structures and compares the obtained results with existing structures, in terms of required number of components and operation frequency.

Transistor size optimization is one method to reduce the power dissipation of CMOS very large scale integration (VLSI) circuits. Analysis shows that parasitic capacitances and velocity saturation of submicron technologies favor wider than minimum transistor sizes. The reason is that they allow for a larger reduction of the supply voltage which results in more substantial power savings. SPICE simulation of prescalers with differently scaled transistors confirm the analysis. The same prescaler has been implemented in a 1.0-m CMOS technology with minimum sized transistors and with optimized transistors for high speed. Measurements confirm that power dissipation is reduced for optimized transistor sizes.

The introduction of HDLs (hardware description languages) have made a significant contribution to VLSI circuit design. While these languages are well suited to describe circuits in great detail, they are found wanting when attempting formal verification of circuits. One of the drawbacks lies in the lack of formal models of semantics. VHDL, with a wide variety of tools available to carry out circuit simulations, is the de facto standard used in VLSI design. On the other hand, the family of synchronous languages has been well studied for the design and synthesis of provably correct reactive systems. Thus, it behooves one to explore the possibility of interfacing languages such as VHDL with synchronous programming languages to handle higher levels of abstraction in circuit design with assured correctness. In this paper, we show how the paradigm of Multiclock ESTEREL provides a framework for the design of multi-clocked systems and asynchronous systems. Multiclock ESTEREL can be used for modeling in conjunction with VHDL to enable formal verification of circuit behavior. We shall also show that Multiclock ESTEREL captures the VHDL timing model succinctly. Multiclock ESTEREL can be used either in conjunction with VHDL or as a replacement depending on the requirements at hand. When used in conjunction, Multiclock ES-TEREL can be used to describe circuits at higher levels of abstraction while VHDL can be used to describe the signal propagation characteristics.

A digital current-mode controller for dc-dc converters is introduced. The current-mode loop is sensorless, relying on constants and internal loop states; removing the need to sense controlled voltages or currents for the inner loop. Furthermore, a fast current-mode control mechanism is implemented by utilizing dead-beat control. The resulting controller is robust and surprisingly uncomplicated. It is well suited to VLSI integration in a low geometry process. An interesting aspect of this control scheme is that it facilitates the application of a low resolution PWM.

Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series coupling capacitance offers preemphasis to lower wire delay, reduces the driven load, and lowers the wire voltage swing without a second power supply. A 0.18mum CMOS testchip shows 10.5times energy savings at a 50mV swing compared to full-swing repeated wires, and a 3times gain in wire bandwidth

In this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain. Results show that the clock slope requirement can be relaxed with respect to traditional assumptions, leading up to 30 40% energy savings and at a very small speed performance penalty. The effectiveness of the clock slope optimization is discussed in detail for the existing classes of FFs. The impact of such an optimization in terms of additive skew and jitter contributions is discussed, together to the analysis of the impact of technology scaling. Extensive post-layout simulations on a 65-nm CMOS technology are performed to check the validity of the underlying assumptions and approximations.

The present paper explores and analyses the performance of Carbon Nano Tube Field Effect Transistor (CNTFET) technology in analog domain through its application as a basic current mirror. 32nm channel length-single walled-one tube CNTFET technology has been assessed and compared with 45nm, 32nm and 22nm NMOS technologies through HSPICE simulations of current mirror circuitry. Different methods of comparison like current error, input-output resistances, AC small signal and transient analysis have been employed which highlight the benefits of CNTFET over NMOS technology and its potential to be used for analog VLSI.

Emerging semiconductor VLSI requires improved device density on a single chip solution that many parameters are becoming vital concern for cost reduction by lowering the chip area, lowering power dissipation, reducing operating voltage, increasing speed etc. A previously designed precision sensor application mirror-amplifier was considered for optimizing in chip area consumption and improves sensing to make it ultra-precise, also this work has reduced the IC to a subcompact die sizes. MAGIC is used as two-dimensional CAD layout tool. Also PSPICE is used for electrical simulation purposes employed by extraction tool. Feature size is taken from mSCN3M_SUBM.30 process for 0.6µm layout and 0.5µm enhanced fabrication process. The improved design has area of 101λX48λ (minimized from 126λX59λ) or 30.3µmX15µm (minimized from 37.8µmX17.7µm) in 0.6µm CMOS design process. For multi-die placement, two sets of chip are designed those are placed on the four sub-dies in a single MOSIS tinychip die. For one set of chip coincidence detector is designed to make the mirror-amplifier ultra precise, buffer stage is designed for another set of chip to drive large load. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

This paper presents a comparative study of Complementary MOSFET (CMOS) full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. Full adder circuit is an essential component for designing of various digital systems. It is used for different applications such as Digital signal processor, microcontroller, microprocessor and data processing units (DSP). In most of these systems the adder lies in the critical path that determines the overall speed of the system. Full adder is mainly used in VLSI devices like microprocessor for computational purposes. The proposed full adder cell has low power consumption, better area efficiency. Recently, there have been massive research interests in this area due to the growing need for low-power and highperformance computing systems. Our aim is to design and compare the full adder circuit in various technologies and compare their power capacity. By using the hybrid structure of NMOS and PMOS, we have implemented the circuit of full adder.

We have developed a full-custom IC design flow based on Synopsys custom design tools and the recently released Synopsys 90nm generic library. The developed design flow can be used for teaching VLSI and digital IC design courses. We have also developed a fullcustom design project that was used as a course project in teaching "Digital VLSI Design" course at San Francisco State University. The design project is to design a 4-bit ripple carry adder in a full custom fashion from schematic to layout in the generic 90nm CMOS technology. The developed design flow and the course project provide a very effective hands-on approach to teaching digital IC design and VLSI design in advanced CMOS technologies. The team project was conducted in a competition based format providing great enthusiasm and motivation among the students, enhancing their learning experience. The competition was to achieve the best design quality defined as the product of following design metrics: propagation delay, power dissipation, and layout area for the 4-bit ripple carry adder. The winning team achieved a delay of 82.2ps, power dissipation of 30.7 W, and layout area of 112.8 m 2 for the 4-bit adder.

This paper presents a scalable and systolic Montgomery's algorithm in GF(2m) using the Hankel matrix-vector representation. The hardware architectures derived from this algorithm represents low-complexity bit-parallel systolic multipliers with trinomials. The results reveal that our proposed multiplier saves approximately 36% space complexity as compared to an existing systolic Montgomery multiplier for trinomials. Moreover, the proposed architectures have the features of regularity, modularity, and local interconnect ability. Accordingly, they are well suited for VLSI implementation

Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I D DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

A new analytical model for carrier mobility in silicon is presented, which is strongly oriented to CAD and suitable for implementation in device simulators. The effects of the electric field, temperature, and doping concentration are accounted for. In particular, the model unifies the descriptions of majority-and minority-carrier mobility and includes the full temperature dependence. The effects of a high longitudinal field are included in the conventional velocity-saturation form; the doping dependence is also incorporated in the latter. The model has been worked out starting from a preliminary investigation using a Boltzmann solver, and has been validated by a number of comparisons with published experiments on silicon.

Year 2009 marks the completion of 50 years of the invention of CORDIC (COordinate Rotation DIgital Computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.

With the advancement in the field of electronics at an incredible pace, the power efficient and high-speed VLSI designs are gaining more popularity and are highly in demand. The decrease in battery weight, size and increase in the lifetime are the key factors for portable equipments. Most of the reported multipliers have very poor performance and/or become non-functional in case of low-voltage, low-power environment. This paper describes various applications of analog multiplier such as frequency doubler, modulator, demodulator etc. All the simulation work has been done on Tanner EDA tool at 45nm technology.

this paper presents a VLSI architecture of a framebased adaptive quantization technique based on the Fast Boundary Adaptation Rule (FBAR). The adaptive quantization algorithm is integrated together with a 128x128 pixel CMOS image sensor array. The pixel operation is based on biologically inspired time-to-first spike encoding scheme. System and circuit level simulations show the successful operation of the proposed architecture.

The paper proposes an ABCD modeling approach to model the crosstalk coupling noise on the victim interconnect due to single / multiple aggressor(s) in deep sub-micron (DSM) chips. After the order reduction the crosstalk model is utilized for the analysis of crosstalk coupling noise on the victim's far end signal. Various timing issues related to signal waveform such as, delay time, overshoot and undershoot occurrence time etc., that in effect help to ensure in prior the desired signal integrity (SI) and performance reliability of the SoCs, can be estimated analytically using the reduced order crosstalk model. It has been observed that the crosstalk coupling noise introduces the delay in the victim's far end signal which can be significant enough or even unacceptable if many aggressors simultaneously couple energy to the victim line, or the line spacing between the aggressor and victim is reduced due to manufacturing defect such as under-etching or even, length of the victim interconnect is increased due to improper layouts of / routings between cores and devices on chips. Influences of other interconnect parasitics on the victim´s far end signal can also be analyzed using the same model. Simulation results obtained with the proposed reduced order model is found to be quite comparable to the accuracy of the PSPICE simulation.

In this paper, we present a basis for treating, evaluating and measuring knowledge as an energy acquired by knowledge centric objects in society. The energy level acquired is indicated as their knowledge potential or KnP. Some objects get more charged in the knowledge domain and exhibit a longer and/or more intense energy trail. The Rate of knowledge acquisition, intellectual caliber and need intensity driving to acquire knowledge all play a role in the knowledge energy (Kenergy) thus acquired. Bounded by established principles of measurement, units, quantification and equations for dealing with knowledge, it becomes amenable to its own (knowledge) science with laws derived from the many disciplines and their own distinctive principles. We fall back on equations from thermodynamics, electrical engineering, fluid mechanics and transmission theory to quantify the flow-properties of knowledge. Though not completely precise and accurate at this stage of development in the science of kno...

Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. It is therefore imperative to design clock buffers to reduce the coupling effects. In this paper, we address the crosstalk effect on clock networks. We propose an algorithm to size clock buffers for given buffered clock trees such that the induced clock jitter is minimized. Our experimental results show a significant reduction of clock jitter by sizing the clock buffers without increasing the total area of buffer.

In the fast paced world of IC design, companies strive for ways to create competitive, robust designs, while delivering speedy time-to-market results. A top-down design flow provides a fast, results oriented design methodology, but, at most Universities, the strong legacy of the MeadKonway approach has lead to custom methods being the default way to teach students VLSI design. This paper discusses some experiences with teaching a top-down Sysrem-on-a-Chip (SoC) design class.

The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O's in VLSI designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In this paper, we introduce the routing problem for chip and package co-design and present the first work in the literature to handle the multiple Re-Distribution Layer (RDL) routing problem for flip-chip designs, considering pin and layer assignment, total wirelength minimization, and chip-package co-design. Our router adopts a two-stage technique of global routing followed by RDL routing. The global routing assigns each block port to a unique bump pad via an I/O pad and decides the RDL routing among I/O pads and bump pads. Based on the minimum-cost maximumflow algorithm, we can guarantee 100% RDL routing completion after the assignment and the optimal solution with the minimum wirelength. The RDL routing efficiently distributes the routing points between two adjacent bump pads and then generates a 100% routable sequence to complete the routing. Experimental results based on 10 industry designs demonstrate that our router can achieve 100% routability and the optimal routing wirelength under reasonable CPU times, while related works cannot.

This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks.

Ulysses is a VLSI computer-aided design environment that effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows for the integration of a collection of individual CAD tools into a design automation (DA) system that wifl execute a codified design methodology. Ulysses can track the multiple partial designs that result during a complete design cycle. Furthermore, Ulysses allows the designer to interrupt the design process at any time and take control.

Novel low-voltage swing CMOS and BiCMOS driverhceiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driverhceiver transmission delay. These level converters have no dc power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed.

Abstract: In thispaper, the notion of equivalent embedding of rectangular duals (jloorplans) is introduced which leads to a new concept of canonical embedding of a rectangular dual; this isajloorplan corresponding to agivenneighbor-hood graph such that the number of ...

A versatile Reed-Solomon (RS) decoder structure is developed based on the time-domain decoding algorithm (transform decoding without transforms). In this paper, the algorithm is restructured and a method is given to decode any RS code generated by any generator polynomial. The main advantage of the introduced decoder structure is the versatility. By versatile decoder we mean a decoder that can be programmed to decode any Reed-Solomon code defined in Galois field 2'" with a fixed symbol size m. This decoder can correct both errors and erasures for any RS code including shortened and singly extended codes. It is shown that the introduced versatile decoder has a very simple structure and can be used to design high-speed singlechip VLSI decoders. As an illustrative example, a Gate-Array-Based programmable RS decoder is implemented on a single chip. This decoder chip can decode any RS code defined in GF (2') with any code word length and any number of information symbols. The decoder chip is fabricated using low power, 1.5 1, 2-layer metal, HCMOS technology.

We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The highthroughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture. The proposed parallel Turbo decoder has been synthesized, placed and routed in a 65-nm CMOS technology with a core area of 8.3 mm 2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations &

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

Abstract-Digital VLSI design courses are a standard component in most electrical and computer engineering curricula. Electronic Design Automation (EDA) or Computer Aided Design (CAD) tools and frameworks are an integral and indispensable part of such courses. In this paper we present our findings during the preparation and setup of such a course, centered around nanoscale CMOS, standard cell based design. Practical issues, such as the choice of licensing model, hardware and software platform selection, point tool identification and deployment as well as the availability of readily useable standard cell libraries are discussed. In addition, a design flow that incorporates the tools in a comprehensive framework is presented. A sample syllabus and a suggested teaching methodology are also given.