Power wall has become one of the main bottlenecks of future VLSI designs. A recently proposed junctionless twin-gate Vertical Slit Field Effect Transistor (VeSFET) is a low power and thermal friendly device, with highly regular layout,... more
Power wall has become one of the main bottlenecks of future VLSI designs. A recently proposed junctionless twin-gate Vertical Slit Field Effect Transistor (VeSFET) is a low power and thermal friendly device, with highly regular layout, and two-side accessibility. These properties are critical for advanced 2D/3D technologies. SRAMs are fundamental blocks of VLSI systems, which are usually used for technology evaluation. This paper provides a VeSFET SRAM performance assessment modeled by CACTI, a cache modeling tool. The results show that VeSFET SRAM design is speed competitive to CMOS SRAM with about 40% of dynamic read energy consumption and 35% of total power consumption for read access rate 100MHz.
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In this paper, we propose a skew-programmable clock-routing architecture. The skews can be adjusted using programmable delay elements (PDEs) which we insert into the clock trees. We develop efficient, shortest-path-based algorithms for... more
In this paper, we propose a skew-programmable clock-routing architecture. The skews can be adjusted using programmable delay elements (PDEs) which we insert into the clock trees. We develop efficient, shortest-path-based algorithms for programming PDEs to optimize timing. Unlike previous methods for FPGA skew optimization which require large power and routing penalty, our method can achieve large timing improvement with small overhead. Typically, if timing requirements are tight, placers make efforts to satisfy them, often at a cost of compromising routability, total wire length, and power. In this work, we propose novel clock-skew-aware placement algorithms which allow us to relax the timing constraints during placement. Timing can be later optimized as a post process. Even though we demonstrate the efficiency of our approach using FPGAs, the new skew optimization method and the new placement algorithm are quite general and can be applied to any general, topology-constrained skew optimization problem. Experimental results indicate that using the new clock-architecture we can obtain a 22% timing improvement for post-layout skew optimization and an additional 21% improvement from our skew-aware placement algorithm. In one fabric, the cost of added logic is 2.19% as measured by dynamic power dissipation, and 0.85% in terms of area overhead.
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Integrated CPU-GPU architectures with a fully addressable shared memory completely eliminate any CPU-GPU data transfer overhead. Since such architectures are relatively new, it is unclear what level of interaction between the CPU and GPU... more
Integrated CPU-GPU architectures with a fully addressable shared memory completely eliminate any CPU-GPU data transfer overhead. Since such architectures are relatively new, it is unclear what level of interaction between the CPU and GPU attains the best energy efficiency. Too coarse grained or larger kernels with fairly low CPU - GPU interaction could cause poor utilization of the shared resources while too fine grained kernels could cause frequent interrupts of GPU computation and performance degradation. Also larger kernels require larger shared resources causing increase in area and parasitics which affect the latency sensitive CPU cores. In this paper, we show the effect of granularity on the overall system's energy efficiency using a synthetic workload. We describe how our framework models a truly unified shared memory in integrated architectures with frequent CPU - GPU communication.
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In this paper, we study the main interconnect aging processes: electromigration, thermomigration and stress migration and propose comprehensive yet compact models for transient and steady states based on hydrostatic stress evolution. Our... more
In this paper, we study the main interconnect aging processes: electromigration, thermomigration and stress migration and propose comprehensive yet compact models for transient and steady states based on hydrostatic stress evolution. Our model can be expressed in terms of voltages only which abstracts away the hydrostatic stress. The model also explains some experimental observations, introduces temperature-dependent Blech’s length criterion and a new time-to-failure formula replacing Black’s empirical model. A tool is developed based on the proposed model which assesses reliability of multi-segment complex interconnect networks. Experimental results obtained on IBM benchmarks validate the model.
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Modern semiconductor industry faces skyrocketing design and manufacturing cost as technology advances. Vertical Slit Field Effect Transistor (VeSFET) based ICs have super regular layouts which may significantly reduce manufacturing cost.... more
Modern semiconductor industry faces skyrocketing design and manufacturing cost as technology advances. Vertical Slit Field Effect Transistor (VeSFET) based ICs have super regular layouts which may significantly reduce manufacturing cost. VeSFETs can be packed densely in an array fashion thus VeSFET-based ICs may achieve smaller footprints than their CMOS counterparts. VeSFET-based ICs also have great energy efficiency, and are good candidate for 3-D integration. In this dissertation, we study VeSFET ICs mapped to various array topologies (canvases), and characterize their area, performance, power, and thermal behaviors. VeSFET-based circuits are implemented by customizing interconnects on pre-manufactured canvases. In this dissertation, we particularly focus on a class of canvases referred to as chain canvases (CCs). CMOS-oriented design automation tools can be easily adapted for CC-based VeSFET designs. VeSFET ICs based on CCs demonstrate very good performance and low power. Detailed routing for super dense VeSFET layouts can be very challenging because highly congested pins are hard to access. We propose a two-sided routing strategy for VeSFET chips. We show that such routing not only provides much better routability, but also achieves better performance and lower power than one-sided routing. Thermal management constitutes a huge challenge for CMOS or FinFET-based circuits, especially when chips go 3-D. VeSFET provides an alternative thermal-friendly design choice. In this dissertation, we show that temperature increase due to self-heating is very small for VeSFET transistors. At chip level, VeSFET-based 2-D and 3-D chips not only have much lower power density, but also better vertical thermal conductivity than their CMOS counterparts. Finally, we explore VeSFET-based subthreshold circuits for ultra-low power applications.
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The rapid growth of system-on-chip designs makes it a necessity for physical design tools to efficiently handle the coexistence of large intellectual property (IP) blocks and small standard cells in a single design. In this work, we... more
The rapid growth of system-on-chip designs makes it a necessity for physical design tools to efficiently handle the coexistence of large intellectual property (IP) blocks and small standard cells in a single design. In this work, we present an efficient expansion-based placer to address standard-cell placement problem in the presence of blockages induced by pre-placed IP blocks. Expansion refers to the process during which cells are gradually distributed over a specified region. We implement expansion in a new placer by enhancing a quadratic placement technique based on fixed-point addition originally presented by B. Hu and M. Marek-Sadowska (2003), where fixed points were defined as dimensionless pseudo cells, and were deliberately introduced into the circuit to pull cells from one location to another. The new placer not only produces very competitive placement results over multiple sets of public-domain benchmarks with conventional rectangle-like chip boundary, but also efficiently handles the existence of blockages. Especially, we develop three expansion strategies and use them under different blockage settings.
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In this paper, the atomic flux divergence (AFD) based flow for AC and pulsed DC signal line electromigration (EM) reliability estimation is proposed. The flow is implemented as a 3-stage filter based on the average (AVG) and... more
In this paper, the atomic flux divergence (AFD) based flow for AC and pulsed DC signal line electromigration (EM) reliability estimation is proposed. The flow is implemented as a 3-stage filter based on the average (AVG) and root-mean-square (RMS) current densities. A relationship between AVG and/or RMS current densities, maximum AFD, and EM lifetime is established and validated. To avoid the necessity of solving finite element equations, SPICE-based simulation scheme is proposed for fast AFD calculation. Fitting functions to evaluate signal line EM with AC and pulsed DC patterns are proposed. To prove fidelity, healing factors for AC EM obtained from our method are verified against measured results. Results of the traditional and proposed methods are compared.
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We propose and experimentally validate an AFD (atomic flux divergence)-based MTTF (mean time to failure) model for wires with EM. We analyze traditional MTTF models and compare them to the proposed model. We use the AFD-based compensation... more
We propose and experimentally validate an AFD (atomic flux divergence)-based MTTF (mean time to failure) model for wires with EM. We analyze traditional MTTF models and compare them to the proposed model. We use the AFD-based compensation model to quantitatively capture the reservoir effect and provide a relationship between the reservoir's volume and EM lifetime enhancement.
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In this paper, we develop an AC electromigration (EM) model for signal lines manufactured with copper dual damascene process. For the first time, the healing factor of AC EM is quantitatively modeled. To measure EM reliability of... more
In this paper, we develop an AC electromigration (EM) model for signal lines manufactured with copper dual damascene process. For the first time, the healing factor of AC EM is quantitatively modeled. To measure EM reliability of interconnects considering timing margins we introduce AC EM functional lifetime. We also develop an atomic flux divergence (AFD)-based void growth model to explain the resistance curves of measured results and calculate the functional EM lifetime of AC signal lines without extracting parameters from experiments. We demonstrate fidelity of the proposed model with measured results for both the healing factor and the rate of resistance change.
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AbstractIn this paper, we present a novel, high throughput field-programmable gate array (FPGA) architecture, PITIA, which combines the high-performance of application specific integrated circuits (ASICs) and the flexibility afforded by... more
AbstractIn this paper, we present a novel, high throughput field-programmable gate array (FPGA) architecture, PITIA, which combines the high-performance of application specific integrated circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. The new ...
Research Interests: Engineering, Computer Science, Computer Architecture, Distributed Computing, Computer Hardware, and 15 moreVery Large Scale Integration, Power Consumption, Throughput, Network Performance, Cmos, Field Programmable Gate Array, High performance, Very high throughput, Reconfigurability, Embedded System, Electrical And Electronic Engineering, Electronic Circuit, Application Specific Integrated Circuit (ASIC), FPGA Architecture, and Datapath
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Research Interests: Engineering, Computer Science, Architecture, Signal Processing, Routing, and 13 moreDesign Space Exploration, Cache, Design optimization, Voltage, Network Topology, Physical Design, Logic Design, Large Scale, Embedded System, Circuit Topology, Mesh Topology, Integrated Circuit Design, and Constraint optimization
In this paper, we address the problem of estimating clock-skew bounds in presence of power supply and process variations. We present a novel technique based on sequence of linear programs to compute the upper and lower bounds of clock... more
In this paper, we address the problem of estimating clock-skew bounds in presence of power supply and process variations. We present a novel technique based on sequence of linear programs to compute the upper and lower bounds of clock skew. We apply our method to pairs of sinks between which logic paths in the circuit exist. When spatial correlations of process variations are known, our method provides more accurate results which reflect the real design. We use accurate models and time-domain analysis ts calculate the clock network delay and delay sensitivity. The experimental results demonstrate that our technique is capable of providing very accurate skew bounds estimation (within 10% error as compared to Monte-Carlo method) in acceptable run-times.
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With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that these errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay... more
With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that these errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay fault diagnosis problem and propose a novel, simulation-based approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower- than-nominal clock frequencies.
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ABSTRACT In this paper, we study the inter-cell routing of circuits implemented with VeSFET transistors. VeSFET-based cells have footprint significantly smaller than their CMOS counterparts and their layouts affect the inter-cell... more
ABSTRACT In this paper, we study the inter-cell routing of circuits implemented with VeSFET transistors. VeSFET-based cells have footprint significantly smaller than their CMOS counterparts and their layouts affect the inter-cell routability. We observe that cell footprint scaling leads to wire lengths reduction only when a sufficient number of inter-cell metal layers is available. Otherwise, the inter-cell white space needed for routing obliterates the potential benefits of footprint scaling. VeSFET-based circuits may benefit from routing on both sides of the transistor layer. Index Terms—VeSFET; regular fabric; advanced technology; routing; design for manufacturability.
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ABSTRACT Vertical Slit Field Effect Transistors (VeSFETs) are novel twin-gate and junction-less devices with nearly ideal sub-threshold swing and manufactured using SOI infrastructure. In this paper, we analyze VeSFETs as potential... more
ABSTRACT Vertical Slit Field Effect Transistors (VeSFETs) are novel twin-gate and junction-less devices with nearly ideal sub-threshold swing and manufactured using SOI infrastructure. In this paper, we analyze VeSFETs as potential components of ultra-low power circuits. We compare circuits built with VeSFETs, FinFETs, and bulk-MOSFETs, all in 65nm technology node. Our experiments demonstrate that VeSFET has the smallest intrinsic capacitance and the lowest minimum energy among the studied devices. The Tied-Gate (TG) VeSFET-based circuit operating at the minimum energy point achieves a lower energy and a higher frequency than its Independent-Gate (IG) VeSFET-based counterpart. IG VeSFET achieves lower energy for circuits working at extremely low and relatively wide frequency range.
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ABSTRACT In many designs, the worst-case delay of a critical path may be activated infrequently. Traditional optimization approaches assume the worst-case conditions, which could lead to an inefficient resource usage. It is possible to... more
ABSTRACT In many designs, the worst-case delay of a critical path may be activated infrequently. Traditional optimization approaches assume the worst-case conditions, which could lead to an inefficient resource usage. It is possible to improve the throughput of such designs by introducing variable latency. One existing realization of the variable-latency design style is based on telescopic units. The design of the hold logic in telescopic units influences the circuit's throughput. In this paper, we show that the traditionally designed hold logic may be inaccurate. We use the short path activation conditions to obtain more accurate hold logic and improve the efficiency of telescopic units. To reduce the overhead for large circuits, we propose an efficient heuristic methodology of constructing non-exact hold logic. We also discuss how to choose the telescopic unit's timing constraint. On average, our approach achieves the performance gain of 21.67% compared to 13.99%, reported in the previous work.
Research Interests: Computer Science, Distributed Computing, Timing Analysis, Computer Hardware, Optical Design, and 11 moreCritical path of history, Heuristic, Digital Circuit Synthesis, Logic Design, Logic Synthesis, Critical Path Method, Electrical And Electronic Engineering, Performance Optimization, Critical Path, Time constraint, and Circuit synthesis
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... Optimization for Power Gated ICs Aida Todri UCSB, ECE Department atodri@ece.ucsb.edu ... The problem is particularly acute for mobile applications, but also becomes critical for other devices as leakage power cuts into their already... more
... Optimization for Power Gated ICs Aida Todri UCSB, ECE Department atodri@ece.ucsb.edu ... The problem is particularly acute for mobile applications, but also becomes critical for other devices as leakage power cuts into their already tight power bud-gets. ...
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Research Interests: Engineering, Computer Science, Logic, Semiconductor Manufacturing, Reliability Engineering, and 15 moreFailure Analysis, Electromigration, Very Large Scale Integration, Degradation, Lithography, Restructuring, Quadrupole, PSM, OPC, Logic Gate, Phase Shifting, Electrostatic Discharge, Minimization, Dielectric Breakdown, and Hot Carriers
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... The problem is particularly acute for mobile applications, but also becomes critical for other devices as leakage power cuts into their already tight power budgets. ... Multiple Power Gating Configurations Aida Todri UCSB, ECE... more
... The problem is particularly acute for mobile applications, but also becomes critical for other devices as leakage power cuts into their already tight power budgets. ... Multiple Power Gating Configurations Aida Todri UCSB, ECE Department atodri@ece.ucsb.edu ...