Logic Synthesis

Abstract: Specification of a concurrent system using CAOS (Concurrent Action Oriented Specifications)(CAOS) as illustrated by Bluespec Inc.'s Bluespec System Verilog provides a high abstraction level, effective concurrency management through atomicity, and powerful compilation to efficient RTL hardware. In this paper, we present two algorithms that make CAOS to RTL synthesis power-aware and produce RTL that can be synthesized into hardware competitive in terms of power/area/slack trade-off against the well-known ...

In this paper, the problem of constructing an efficient quantum circuit for the implementation of an arbitrary quantum computation is addressed. To this end, a basic block based on the cosine-sine decomposition method is suggested which contains $l$ qubits. In addition, a previously proposed quantum-logic synthesis method based on quantum Shannon decomposition is recursively applied to reach unitary gates over $l$ qubits. Then, the basic block is used and some optimizations are applied to remove redundant gates. It is shown that the exact value of $l$ affects the number of one-qubit and CNOT gates in the proposed method. In comparison to the previous synthesis methods, the value of $l$ is examined consequently to improve either the number of CNOT gates or the total number of gates. The proposed approach is further analyzed by considering the nearest neighbor limitation. According to our evaluation, the number of CNOT gates is increased by at most a factor of $\frac{5}{3}$ if the nea...

Data structures for Boolean functions build an essential component of design automation tools, especially in the area of logic synthesis. The state of the art data structure is the ordered binary decision diagram (OBDD), which results from general binary decision diagrams (BDDs), also called branching programs, by ordering restrictions. In the context of EXOR-based logic synthesis another type of decision diagram (DD), called (ordered) functional decision diagram ((O)FDD) becomes increasingly important. We study the relation between (ordered, free) BDDs and FDDs. Both, BDDs and FDDs, result from DDs by defining the represented function in different ways. If the underlying DD is complete, the relation between both types of interpretation can be described by a Boolean transformation τ. This allows us to relate the FDD-size of f and the BDD-size of τ(f) also in the case that the corresponding DDs are free or ordered, but not (necessarily) complete. We use this property to derive several results on the computational power of OFDDs and OBDDs. Symmetric functions are shown to have efficient representations as OBDDs and OFDDs as well. Classes of functions are given that have exponentially more concise OFDDs than OBDDs, and vice versa. Finally, we determine the complexity of some standard operations if OFDDs are used for the representation of Boolean functions.

Because the qubit probabilities must be preserved at the output of the quantum gate, it is noted that all matrices representing them are unitary, ie U*U=I. An important unitary matrix property is that of full rank. This property implies that quantum gate matrix rows and columns are ...

In this paper, we discuss the problem of optimizing a multi-level logic combinational Boolean network. Our techniques apply a sequence of local perturbations and modifications of the network which are guided by the automatic test pattern generation ATPG based reasoning. In particular, we propose several new ways in which one or more redundant gates or wires can be added to

Digital synthesis tools such as logic synthesis and semicustom layout have dramatically changed both the frontend (specification to netlist) and backend (netlist to mask) steps of the digital IC de- sign process. In this tutorial, we look at the last decade's worth of progress on analog circuit synthesis and layout tools. We focus on the frontend and backend of analog

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentioned vectors (registered vectors) has been developed. In this method logic functions are implemented using both embedded memory blocks

Intellectual property (IP) blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time to market which results in increased profits. Alliances of companies have ...

Supmech, which is noncommutative Hamiltonian mechanics \linebreak (NHM) (developed in paper I) with two extra ingredients : positive observable valued measures (PObVMs) [which serve to connect state-induced expectation values and classical probabilities] and the `CC condition' [which stipulates that the sets of observables and pure states be mutually separating] is proposed as a universal mechanics potentially covering all physical phenomena. It facilitates development of an autonomous formalism for quantum mechanics. Quantum systems, defined algebraically as supmech Hamiltonian systems with non-supercommutative system algebras, are shown to inevitably have Hilbert space based realizations (so as to accommodate rigged Hilbert space based Dirac bra-ket formalism), generally admitting commutative superselection rules. Traditional features of quantum mechanics of finite particle systems appear naturally. A treatment of localizability much simpler and more general than the traditional one is given. Treating massive particles as localizable elementary quantum systems, the Schr$\ddot{o}$dinger wave functions with traditional Born interpretation appear as natural objects for the description of their pure states and the Schr$\ddot{o}$dinger equation for them is obtained without ever using a classical Hamiltonian or Lagrangian. A provisional set of axioms for the supmech program is given.

This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1].

This paper presents a new and efficient heuristic procedure for determining whether or not a given Boolean function is a threshold function, when the Boolean function is given in the form of a decision diagram. The decision diagram based method is significantly different from earlier methods that are based on solving linear inequalities in Boolean variables that derived from truth tables. This method's success depends on the ordering of the variables in the binary decision diagram (BDD). An alternative data structure, and one that is more compact than a BDD, called a max literal factor tree (MLFT) is introduced. An MLFT is a particular type of factoring tree and was found to be more efficient than a BDD for identifying threshold functions. The threshold identification procedure is applied to the MCNC benchmark circuits to synthesize threshold gate networks.

We propose a new power consumption model that accounts for the power consumption at the internal nodes of a CMOS gate. Next, we address the problem of minimizing the average power consumption during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the first step, we generate a NAND decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum. In the second step, we perform a power efficient technology mapping that finds a minimal power mapping for given timing constraints (subject to the unknown load problem)