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Perturb and simplify: multilevel Boolean network optimizer

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
By Malgorzata Marek-sadowska
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ICCAD94, Pages 2-5 Perturb and Simplify: Multi-level Boolean Network Optimizer Shih-Chieh Chang and Malgorzata Marek-Sadowska Electrical and Computer Engineering Department, University of California Santa Barbara, CA 93106 In this paper, we discuss the problem of optimizing a multi-level logic combinational Boolean network. Our techniques apply a sequence of local perturbations and modifications of the network which are guided by the automatic test pattern generation ATPG based reasoning. In particular, we propose several new ways in which one or more redundant gates or wires can be added to a network. We show how to identify gates which are good candidates for local functionality change. Furthermore, we discuss the problem of adding and removing two wires, none of which alone is redundant, but when jointly added/removed they do not affect functionality of the network. We also address the problem of efficient redundancy computation which allows to eliminate many unnecessary redundancy tests. We have performed experiments on MCNC benchmarks and compared the results to those of misII[4] and RAMBO[6]. Experimental results are very encouraging. References [1] K.A. Bartlett et al, “Multilevel Logic Minimizing Using Implicit Don’t cares,” IEEE Trans. on CAD-7(6), pp. 723-740(June 1988). [2] C. L. Berman and L. H. Trevillyan. “Global Flow Optimization in Automatic Logic Design,” IEEE Trans. CAD 10, pp. 557-564(May 1991). [3] D. Bostick et al, “The Boulder Optimal Logic Design System,” Proc. ICCAD, pp. 62-65, 1987. [4] R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, “MIS: Multi-level Interactive Logic Optimization System,” IEEE Trans. on CAD, CAD-6(6), pp. 1062-1081(Nov. 1989). [5] Shih-Chieh Chang and Malgorzata Marek-Sadowska, “Layout Driven Logic Synthesis for FPGA,” Proc. Design Automation Conference. pp [6] K.T. Cheng and L.A. Entrena, “Multi-Level Logic Optimization by Redundancy Addition and Removal,” in Proc. European Conference On Design Automation, pp. 373-377, Feb. 1993. [7] M.Damiani, J.C.Y.Yang and G.De Micheli, “Optimization of Combinational Logic Circuits Based on Compatible Gates”, Proc. DAC’93, pp.631-636, June 1993. [8] L.A. Entrena and K. T. Cheng, “Sequential Logic Optimization By Redundancy Addition and Removal”, Proc. International Conference on Computer Aided Design, Nov. 1993. [9] E. Detjens, G. Gannot, R. Rudell, A. L. Sangiovanni-Vincentelli and A. Wang, “Technology Mapping in MIS,” Proc. ICCAD, pp. 116-119, 1987. [10] T.Kirkand and M.R. Mercer, “A Topological Search Algorithm For ATPG,” Proc. 24th Design Automation Conf., pp. 502-508, June 1987. [11] C.E.Leiserson, F.M.Rose, and J.B.Saxe, “Optimizing synchronous circuit by retiming”, in Proc. Third Caltech Conf. on VLSI, 1983. [12] S. Muroga et al, “The Transduction Method-Design of Logic Networks Based on Permissible Functions,” IEEEE Transaction. on Computer C38(10). pp. 1404-1423 (Oct. 1989). [13] M.Schulz and E.Auth, “Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques,” Proc. Fault Tolerant Computing Symposium, pp. 30-34 June 1988.
ICCAD94, Pages 6-13 Multi-Level Logic Optimization by Implication Analysis Wolfgang Kunz Max-Planck-Society, Fault-Tolerant Computing Group at the University of Potsdam, 14415 Potsdam, Germany email: wkunz@rz.uni-potsdam.de Prem R. Menon Dept. of Electrical & Comp. Eng., University of Massachusetts at Amherst, Amherst, MA 01003, U.S.A. Abstract This paper proposes a new approach to multilevel logic optimization based on ATPG (Automatic Test Pattern Generation). Previous ATPG-based methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. We show that the ATPG-based method presented here allows (in principle) the transformation of a given combinational network C into an arbitrary, structurally different but functionally equivalent combinational network C’. Furthermore, powerful heuristics are presented in order to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good” candidates for the minimization of the circuit. In particular, it is shown that Recursive Learning can derive “good” Boolean divisors justifying the effort to attempt a Boolean division. For 9 out of 10 ISCAS-85 benchmark circuits our tool HANNIBAL obtains smaller circuits than the well-known synthesis system SIS. References [1] Abramovici M., Breuer M., Friedman A.: “Digital Systems Testing and Testable Design”, Computer Science Press, 1990. [2] Berman L., Trevillyan L.: “Global Flow Optimization in Automatic Logic Design”, IEEE Transactions on Computer-Aided Design, vol. 10, No. 5, May 1991. [3] Brand D.: “Redundancy and Don’t Cares in Logic Synthesis”, IEEE Trans. on Computers, vol. C-32, pp. 947- 952, Oct. 1983. [4] Brand D.: “Verification of Large Synthesized Designs”, Proc. Int. Conf. on Computer-Aided Circuit Design, Santa Clara, Nov. 1993, pp. 534-537. [5] Brown F.: “Boolean Reasoning”, Kluwer Academic Publishers, Boston, MA 1990. [6] Brayton R. K., Hachtel G. D., McMullen C. T., Sangiovanni-Vincentelli A. L.: “Logic Minimization Algorithms for VLSI Synthesis”, Kluwer Academic Publishers, Massachusetts, 1984. [7] Brayton R. K., Rudell R., Sangiovanni-Vincentelli A., Wang A. R.: “MIS: Multi-level Interactive Logic Optimization System”, IEEE Trans. on CAD, CAD-6(6), pp. 1062-1081, Nov. 1987. [8] Cheng K.T., April 1994, private communication [9] Entrena L. A., Cheng K.T: “Sequential Logic Optimization by Redundancy Addition and Removal”, Proc. Intl. Conf. on Computer-Aided Design, Nov. 1993, pp. 310-315. [10] Fujiwara H., Shimono T.: “On the Acceleration of Test Generation Algorithms”, in Proc. 13th Int. Symp. on Fault Tolerant Computing, 1983, pp. 98-105. [11] Hachtel G. et al.: “Performance Enhancements in BOLD using Implications,” Proc. Intl. Conf. on Computer- Aided Design, pp. 94-97, Nov. 1988. [12] Hotz G.: “Einführung in die Informatik”, Teubner Verlag, Stuttgart 1990.
ICCAD94, Pages 2-5 Perturb and Simplify: Multi-level Boolean Network Optimizer Shih-Chieh Chang and Malgorzata Marek-Sadowska Electrical and Computer Engineering Department, University of California Santa Barbara, CA 93106 In this paper, we discuss the problem of optimizing a multi-level logic combinational Boolean network. Our techniques apply a sequence of local perturbations and modifications of the network which are guided by the automatic test pattern generation ATPG based reasoning. In particular, we propose several new ways in which one or more redundant gates or wires can be added to a network. We show how to identify gates which are good candidates for local functionality change. Furthermore, we discuss the problem of adding and removing two wires, none of which alone is redundant, but when jointly added/removed they do not affect functionality of the network. We also address the problem of efficient redundancy computation which allows to eliminate many unnecessary redundancy tests. We have performed experiments on MCNC benchmarks and compared the results to those of misII[4] and RAMBO[6]. Experimental results are very encouraging. References [1] K.A. Bartlett et al, “Multilevel Logic Minimizing Using Implicit Don’t cares,” IEEE Trans. on CAD-7(6), pp. 723-740(June 1988). [2] C. L. Berman and L. H. Trevillyan. “Global Flow Optimization in Automatic Logic Design,” IEEE Trans. CAD 10, pp. 557-564(May 1991). [3] D. Bostick et al, “The Boulder Optimal Logic Design System,” Proc. ICCAD, pp. 62-65, 1987. [4] R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, “MIS: Multi-level Interactive Logic Optimization System,” IEEE Trans. on CAD, CAD-6(6), pp. 1062-1081(Nov. 1989). [5] Shih-Chieh Chang and Malgorzata Marek-Sadowska, “Layout Driven Logic Synthesis for FPGA,” Proc. Design Automation Conference. pp [6] K.T. Cheng and L.A. Entrena, “Multi-Level Logic Optimization by Redundancy Addition and Removal,” in Proc. European Conference On Design Automation, pp. 373-377, Feb. 1993. [7] M.Damiani, J.C.Y.Yang and G.De Micheli, “Optimization of Combinational Logic Circuits Based on Compatible Gates”, Proc. DAC’93, pp.631-636, June 1993. [8] L.A. Entrena and K. T. Cheng, “Sequential Logic Optimization By Redundancy Addition and Removal”, Proc. International Conference on Computer Aided Design, Nov. 1993. [9] E. Detjens, G. Gannot, R. Rudell, A. L. Sangiovanni-Vincentelli and A. Wang, “Technology Mapping in MIS,” Proc. ICCAD, pp. 116-119, 1987. [10] T.Kirkand and M.R. Mercer, “A Topological Search Algorithm For ATPG,” Proc. 24th Design Automation Conf., pp. 502-508, June 1987. [11] C.E.Leiserson, F.M.Rose, and J.B.Saxe, “Optimizing synchronous circuit by retiming”, in Proc. Third Caltech Conf. on VLSI, 1983. [12] S. Muroga et al, “The Transduction Method-Design of Logic Networks Based on Permissible Functions,” IEEEE Transaction. on Computer C38(10). pp. 1404-1423 (Oct. 1989). [13] M.Schulz and E.Auth, “Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques,” Proc. Fault Tolerant Computing Symposium, pp. 30-34 June 1988. ICCAD94, Pages 6-13 Multi-Level Logic Optimization by Implication Analysis Wolfgang Kunz Max-Planck-Society, Fault-Tolerant Computing Group at the University of Potsdam, 14415 Potsdam, Germany email: wkunz@rz.uni-potsdam.de Prem R. Menon Dept. of Electrical & Comp. Eng., University of Massachusetts at Amherst, Amherst, MA 01003, U.S.A. Abstract This paper proposes a new approach to multilevel logic optimization based on ATPG (Automatic Test Pattern Generation). Previous ATPG-based methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. We show that the ATPG-based method presented here allows (in principle) the transformation of a given combinational network C into an arbitrary, structurally different but functionally equivalent combinational network C’. Furthermore, powerful heuristics are presented in order to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good” candidates for the minimization of the circuit. In particular, it is shown that Recursive Learning can derive “good” Boolean divisors justifying the effort to attempt a Boolean division. For 9 out of 10 ISCAS-85 benchmark circuits our tool HANNIBAL obtains smaller circuits than the well-known synthesis system SIS. References [1] Abramovici M., Breuer M., Friedman A.: “Digital Systems Testing and Testable Design”, Computer Science Press, 1990. [2] Berman L., Trevillyan L.: “Global Flow Optimization in Automatic Logic Design”, IEEE Transactions on Computer-Aided Design, vol. 10, No. 5, May 1991. [3] Brand D.: “Redundancy and Don’t Cares in Logic Synthesis”, IEEE Trans. on Computers, vol. C-32, pp. 947952, Oct. 1983. [4] Brand D.: “Verification of Large Synthesized Designs”, Proc. Int. Conf. on Computer-Aided Circuit Design, Santa Clara, Nov. 1993, pp. 534-537. [5] Brown F.: “Boolean Reasoning”, Kluwer Academic Publishers, Boston, MA 1990. [6] Brayton R. K., Hachtel G. D., McMullen C. T., Sangiovanni-Vincentelli A. L.: “Logic Minimization Algorithms for VLSI Synthesis”, Kluwer Academic Publishers, Massachusetts, 1984. [7] Brayton R. K., Rudell R., Sangiovanni-Vincentelli A., Wang A. R.: “MIS: Multi-level Interactive Logic Optimization System”, IEEE Trans. on CAD, CAD-6(6), pp. 1062-1081, Nov. 1987. [8] Cheng K.T., April 1994, private communication [9] Entrena L. A., Cheng K.T: “Sequential Logic Optimization by Redundancy Addition and Removal”, Proc. Intl. Conf. on Computer-Aided Design, Nov. 1993, pp. 310-315. [10] Fujiwara H., Shimono T.: “On the Acceleration of Test Generation Algorithms”, in Proc. 13th Int. Symp. on Fault Tolerant Computing, 1983, pp. 98-105. [11] Hachtel G. et al.: “Performance Enhancements in BOLD using Implications,” Proc. Intl. Conf. on ComputerAided Design, pp. 94-97, Nov. 1988. [12] Hotz G.: “Einführung in die Informatik”, Teubner Verlag, Stuttgart 1990. [13] Kunz W., Pradhan D.K.: “Recursive Learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits”, Proceedings Intl. Test Conference, 1992, pp.816-825. [14] Kunz W., Pradhan D.K.: “Recursive Learning: A New Implication Technique for Efficient Solutions to CAD Problems: Test, Verification and Optimization”, accepted for publication in IEEE Transactions of Computer-Aided Design (probably Sept. 1994). [15] Kunz W.: “HANNIBAL: An Efficient Tool for Logic Verification Based on Recursive Learning”, Proc. Intl. Conference on Computer-Aided Design, Santa Clara, Nov. 1993, pp. 538-543. [16] Kunz W., Menon P.: “Multi-Level Logic Optimization by Implication Analysis” Technical Report, Max-Planck Institut für Informatik, MPI -I-94-602, April 1994. [17] Lee H.K., Ha D.S.: “An Efficient Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation”, Proc. Intl. Test Conference, pp. 946-953, Sept, 1991. [18] Muroga S. et al.: “The Transduction Method - Design of Logic Networks Based on Permissible Functions”, IEEE Trans. on Computers, Oct. 1989, pp. 1404-1424. [19] Rajski J., Cox H.: “A Method to Calculate NecessaryAssignments in Algorithmic Test Pattern Generation”, Proc., Int. Test Conf., 1990, pp. 25-34. [20] Rajski J., Vasudevamurthy J.: “Testability Preserving Transformations in Multi-Level Logic Synthesis”, Proc. Intl. Test Conference, 1990, pp. 265-273. [21] Rohfleisch B., Brglez F.: “Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping” , Proc. EDAC/ETC/EUROASIC 1994, pp. 87 - 93. [22] Roth J.P.: “Diagnosis of Automata Failures: A Calculus and a Method”, IBM Journal of Research and Development, Vol. 10, No. 4, July 1966, pp. 278-291. [23] Savoj H., Brayton, R.K., Touati H.: “Extracting Local Don’t Cares for Network Optimization”, Proc. Intl. Conf. on Computer-Aided Design, Nov. 1991 [24] Schulz M., Trischler E., Sarfert T.: “SOCRATES: A highly efficient automatic test pattern generation system”, IEEE Transactions on Computer-Aided Design, vol. 10. no.4, April 1991. ICCAD94, Pages 14-18 Incremental Synthesis Daniel Brand, Anthony Drumm, Sandip Kundu, Prakash Narain IBM Research Division, IBM AS/400 Division IBM Research Division IBM Microelectronics Yorktown Heights, NY Rochester, MN Yorktown Heights, NY Endicott, NY Abstract A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only. References [1] D. Brand, "The Taming of Synthesis", International Workshop on Logic Synthesis, RTP, May 1991. [2] D. Brand, "Verification of Large Synthesized Designs", Proc. of ICCAD, November 1993, pp. 534-537. [3] F. Brglez, P.Pownall, R. Humm, "Accelerated ATPG and Fault Grading via Testability Analysis", IEEE International Symposium on Systems and Circuits, June 1985, pp. 695-698. [4] P.Y. Chung, I.N. Hajj, "ACCORD Automatic Catching and CORrection of Logic Design Errors in Combinational Circuits", International Test Conference, September 1992. [5] M. Fujita, T. Kakuda, Y. Matsunaga, "Redesign and Automatic Error Correction of Combinational Circuits", Logic and Architecture Synthesis, ed. G. Saucier, North-Holland: Elsvier Science Publishers B.V., pp. 253-262. [6] M. Fujita, Y. Matsunaga, K.C. Chen, "On Application of Boolean Unification to Combinational Logic Synthesis", Proc. of ICCAD, November 1991, pp. 510-513. [7] J.C. Madre, O. Coudert, J.P. Billon, "Automating the Diagnosis and the Rectification of Design Errors with PRIAM", Proc. of ICCAD, November 1989, pp. 30-33. [8] I. Pomeranz, S.M. Reddy, "On Diagnosis and Correction of Design Errors", Proc. of ICCAD, November 1993, pp. 500-507. [9] T.Shinsha, T. Kubo, Y. Sakataya, J. Koshishita, K. Ishihara, "Incremental Logic Synthesis Through Gate Logic Structure Identification", Proc. of DAC, June 1986, pp. 391-397. [10] Y. Watanabe, R.K. Brayton, "Incremental Synthesis for Engineering Changes", Proc. of ICCAD, November 1991, pp. 40-43. ICCAD94, Pages 20-26 Definition and Solution of the Memory Packing Problem for Field-Programmable Systems David Karchmer and Jonathan Rose Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario. Canada M5S 1A4 Abstract This paper defines a new optimization problem that arises in the use of a Field-Programmable System (FPS). An FPS consists of a set of Field-Programmable Gate Arrays and memories, and is used both for emulation of ASICs and computation. In both cases the application circuits will include a set of memories which may not match the number and aspect ratio of the physical memories available on the FPS. This can often require that the physical memories be timemultiplexed to implement the required memories, in a circuit we call a memory organizer. We give a precise definition of the packing optimization problem and present an algorithm for its solution. The algorithm has been implemented in a CAD tool that automatically produces a memory organizer circuit ready for synthesis by a commercial FPGA tool set. References [1] J. Arnold, D. Buell, and E. Davis, “Splash 2," in 4th. Annual ACM Symposium on Parallel Algorithms and Architectures, pp. 316-322, 1992. [2] P. Bertin, D. Roncin, and J. Vuillemin, “Programmable Active Memories: A Performance Assessment," in Research on Integrated Systems: Proceedings of the 1993 Symposium, MIT Press, 1993. [3] S. Walters, “Computer-aided prototyping for ASIC-Based systems," IEEE Design and Test of Computers, pp. 410, June 1991. [4] R. Tessier, J. Babb, M. Dahl, S. Hanono, and A. Agarwal, “The virtual wires emulation system: A gate-efficient asic prototyping environment," in FPGA 94, February 1994. [5] D. Galloway, D. Karchmer, P. Chow, D. Lewis, and J. Rose, “The Transmogri_er: The University of Toronto Field-Programmable System," Tech. Rep. 306, CSRI, University of Toronto, 1994. [6] D. Karchmer, “A Field-Programmable System with Reconfigurable Memory," Master's thesis, University of Toronto, June 1994. [7] Xilinx Inc., San Jose, CA, XACT Development System, October 1992. [8] Aptix Corporation, San Jose, CA, Aptix System Data Book, November 1993. [9] T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. John Wiley & Sons, 1990. [10] M. Garey and R. Graham, “Worst-case analysis of memory allocation algorithms," in 4th. Annual ACM Symposium on Theory of Computing, 1972. ICCAD94, Pages 27-30 Integrating Program Transformations in the Memory-Based Synthesis of Image and Video Algorithms David J. Kolson, Alexandru Nicolau, Nikil Dutt Department of Information and Computer Science, University of California, Irvine, Irvine, CA 92717-3425 Abstract In this paper we discuss the interaction and integration of two important program transformations in high-level synthesis--Tree Height Reduction and Redundant Memory-access Elimination. Intuitively, these program transformations do not interfere with one another as they optimize different operations in the program graph and different resources in the synthesized system. However, we demonstrate that integration of the two tasks is necessary to better utilize available resources. Our approach involves the use of a “meta-transformation" to guide transformation application as possibilities arise. Results observed on several image and video benchmarks demonstrate that transformation integration increases performance through better resource utilization. References [1] J. L. Baer and D. P. Bovet. Compilation of Arithmetic Expressions for Parallel Computations. Proc. of IFIP Congress, pages 34-46, 1968. [2] D. G.. Bradlee, S. J. Eggers, and R. R. Henry. Integrating Register Allocation and Instruction Scheduling for RISCs. ASPLOS, 26(4), April 1991. [3] R. P. Brent. The Parallel Evaluation of General Arithmetic Expression. Journal of the ACM, 21(2), 1974. [4] D. Callahan, J. Cocke, and K. Kennedy. Estimating Interlock and Improving Balance for Pipelined Architectures. ICPP, 1987. [5] J. W. Davidson and S. Jinturkar. Memory Access Coalescing: A Technique for Eliminating Redundant Memory Accesses. PLDI, 29(6), June 1994. [6] E. Duesterwald, R. Gupta, and M. Soffa. A Practical Data Flow Framework for Array Reference Analysis and its Use in Optimizations. PLDI, 28(6), June 1993. [7] D. Gajski, N. Dutt, A. Wu, and S. Lin. High Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers. Norwell, MA., 1992. [8] Z. Iqbal, M. Potkonjak, S. Dey, and A. Parker. Critical Path Minimization Using Retiming and Algebraic SpeedUp. 30th DAC, 1993. [9] D. J. Kolson, A. Nicolau, and N. Dutt. Minimization of Memory Traffic in High-Level Synthesis. 31st DAC, June 1994. [10] J. S. Lim. Two-Dimensional Signal and Image Processing. Prentice Hall Signal Processing Series, 1990. [11] D. A. Lobo and B. M. Pangrle. Redundant Operator Creation - An Optimized Scheduling Technique. 28th DAC, 1991. [12] Y. Muraoka. Parallelism Exposure and Exploitation in Programs. PhD thesis, Univ. of Ill. Urbana-Champagne, 1971. [13] A. Nicolau and R. Potasman. Incremental Tree Height Reduction for High-Level Synthesis. 28th DAC, 1991. [14] S. Novack and A. Nicolau. Mutation Scheduling: A Unified Approach to Compiling for Fine-Grain Parallelism. Proc. 7th Int'l Wksp on Lang. and Comp. for Par. Computing, 1994. [15] S. S. Pinter. Register Allocation with Instruction Scheduling: A New Approach. PLDI, 1993. [16] P. Pöchmüller, M. Glesner, and F. Longsen. High-Level Synthesis Transformations for Programmable Architectures. EuroDAC '93, 1993. [17] R. Potasman, J. Lis, A. Nicolau, and D. Gajski. Percolation Based Synthesis. 27th DAC, 1990. [18] W. H. Press, S. A. Teukolsky, W. T.Vetterling, and B. P. Flannery. Numerical Recipes in C: The Art of Scientific Computing. Cambridge University Press, second edition, 1992. [19] H. Trickey. Flamel: A High-Level Hardware Compiler. IEEE Trans. on CAD, 6(2), March 1991. [20] J. Vanhoof, K. Van Rompaey, I. Bolsens, G. Goossens, and H. De Man. High Level Synthesis for Real Time Digital Signal Processing. Kluwer Academic Publishers. Norwell, MA., 1993. [21] D. Whitfield and M. L. Soffa. Investigating Properties of Code Transformations. ICPP, 1993. ICCAD94, Pages 31-34 Dataflow-driven Memory Allocation for Multi-dimensional Signal Processing Systems Florin Balasa, Francky Catthoor,Hugo De Man, IMEC, Kapeldreef 75, B-3001 Leuven, Belgium Abstract Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing systems. In this paper, a novel background memory allocation and assignment technique is presented. It is intended for a behavioural algorithm specification, where the procedural ordering of the memory related operations is not yet fully fixed. Instead of the more restricted classical scheduling-based explorations, starting from procedurally interpreted specifications in terms of loops, a novel optimization approach - driven by data-flow analysis - is proposed. Employing the estimated silicon area as a steering cost, this allocation/assignment technique yields one or (optionally) several distributed (multi-port) memory architecture(s) with fully-determined characteristics, complying with a given clock cycle budget for read/write operations. Moreover, our approach can accurately deal with complex multi-dimensional signals by means of a polyhedral data-flow analysis operating with groups of scalars. References [1] I.Ahmad, C.Y.R.Chen, “Post-processor for data path synthesis using multiport memories," Proc. ICCAD'91, pp.276-279, Santa Clara CA, Nov. 1991. [2] F.Balasa, F.Catthoor, H.De Man, “Exact Evaluation of Memory Area for M-D Processing Systems," Proc. ICCAD'93, pp.669-672, Santa Clara CA, Nov. 1993. [3] G.Dantzig, B.Eaves, “Fourier-Motzkin Elimination and Its Dual," J. Combinatorial Theory, pp.288-297, 1973. [4] F.Franssen, L.Nachtergaele, H.Samsom, F.Catthoor, H.De Man, “Control ow optimization for fast system simulation and storage minimization", Proc. 5th EDAC'94, pp.20-24, Paris, France, Mar. 1994. [5] G.Goossens, J.Rabaey, J.Vandewalle, H.De Man, “An efficient microcode compiler for application-specific DSP processors," IEEE Trans. CAD, pp.925-937, Sep. 1990. [6] P.Lippens et al., “Allocation of multiport memories for hierarchical data streams," Proc. ICCAD'93, pp. 728-735, Santa Clara CA, Nov. 1993. [7] J.M.Mulder, N.T.Quach, M.J.Flynn, “An Area Model for On-Chip Memories and its Application," IEEE J. Solid-state Circ., Vol.SC-26, pp.98-105, Feb. 1991. [8] L.Ramachandran, D.Gajski, V.Chaiyakul, “An algorithm for array variable clustering," Proc. 5th EDAC'94, pp.262-266, Paris, France, Feb. 1994. [9] L.Stok, J.Jess, “Foreground memory management in data path synthesis," Int. J. on Circ. Theory and Appl., Vol.20, pp.235-255, 1992. [10] J.Vanhoof, K.Van Rompaey, I.Bolsens, G.Goossens, H.De Man, “High-level synthesis for real-time digital signal processing," Kluwer Acad. Publ., 1993. ICCAD94, Pages 36-39 Test Generation for Bridging Faults in CMOS Ics Based on Current Monitoring versus Signal Propagation U. Gläser, H. T. Vierhaus, M. Kley, A. Wiederhold German National Research Center for Computer Science (GMD) Abstract Bridge-type defects play a dominant role in state-of-the-art CMOS technologies. This paper describes a combined functional and overcurrent-based test generation approach for CMOS circuits, which is optionally based on layout information. Comparative results for benchmark circuits are given to demonstrate the feasibility of voltage-based versus IDDQ-based testing. References [1] F. J. Ferguson and P. J. Larrabee, "Test Pattern Generation for Realistic Bridge Faults in CMOS Circuits", Proc. IEEE Int. Test Conf. 1991, pp. 492-499 [2] S. W. Bollinger and S. F. Midkiff, "On Test Generation for IDDQ Testing of Bridging Faults in CMOS Circuits", Proc. IEEE Int. Test Conf. 1991, pp. 598-607 [3] E. Isern and J. Figueras, "Test Generation with High Coverage for Quiescent Current Test of Bridging Faults in Combinational Circuits", Proc. IEEE Int. Test Conf. 1993, pp. 73-82 [4] H. T. Vierhaus, W. Meyer, U. Gläser, "CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects", Proc. IEEE Int. Test Conf. 1993, Baltimore [5] W. Maly, P. Nigh, "Built-In Current Testing, a Feasibility Study", Proc. IEEE ICCAD´88, pp. 340-343 [6] U. Gläser, U. Hübner, H. T. Vierhaus, "Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects", Proc. Int. Test Conf. 1992, pp. 21-29 [7] G. Spiegel, "Optimized Test Cost using Fault Probabilities", Proc. 3rd European Test Conf., ETC 93, Rotterdam, pp. 188-193, 1993 [8] V. Henkel and U. Golze, "RISCE- A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification", Proc. 25th ACM/IEEE Design Autom. Conf, 1988, pp. 465-470 [9] F. Brglez, H. Fujiwara, " A Neutral List of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN" , Proc. 1985 Int. Symp. Circ. and Systems, pp. 671-674, 1985 ICCAD94, Pages 40-43 Iterative [Simulation-Based Genetics + Deterministic Techniques] =Complete ATPG Daniel G. Saab Coordinated Science Laboratory, University of Illinois, Urbana, IL 618011 Youssef G. Saab Computer Science Department, University of Missouri, Columbia, MO 65211 Jacob A. Abraham Computer Engineering Research Center, University of Texas at Austin, Austin, TX 78758 Abstract Simulation-based test vector generators require much less computer time than deterministic ATPG but they generate longer test sequences and sometimes achieve lower fault coverage. This is due to the divergence in the search process. In this paper, we propose a correction technique for simulation-based ATPG. The technique is based on identifying the diverging state and on computing a fault cluster (faults close to each other). A set of candidate faults from the cluster is targeted with a deterministic ATPG and the resulting test sequence is used to restart the search process of the simulation-based technique. This above process is repeated until all faults are detected or proven to be redundant/untestable. The program implementing this approach has been used to generate tests with very high fault coverage, and runs about 10 times faster than traditional deterministic techniques with very good test quality in terms of test length and fault coverage. References [1] Miron Abramovici, Melvin A. Breuer, and Arthur D. Friedman, Digital System Testing and Testable Design. NewYork: Computer Science Press, 1990. [2] O. H. Ibarrra and S. Sahni, "Polynomially complete fault detection problems," IEEE Trans. Comput., vol. C-24, pp. 242-249, March 1975. [3] M. A. Iyer and M. Abramovici, "Low-Cost Redundancy Identification for Combinational Circuits," Proc. 7th Int. Conf. on VLSI Design India, pp. 315-318, 994. [4] M. H. Schulz, E. Trischler, and T. M. Sarfert, "SOCRATES: A highly efficient automatic test pattern generation system," IEEE Trans. Computer-Aided Design, vol. CAD-7, pp. 126-137, Jan. 1988. [5] H. Fujiwara and T. Shimono, "On the Acceleration of Test Generation Algorithms," IEEE Trans. Computers, pp. 1137-1144, Dec. 1983. [6] J. A. Waicukauski, P. A. Shupe, D. J. Giramma, and A. Matin, "ATPG for Ultra-Large Structrued Designs," Proceedings of IEEE International Test Conference, pp. 44-51,1990. [7] A. Ghosh, S. Devadas , and A. R. Newton, "Sequential Test Generation at the Register-Trandfer and Logic Levels," Design Automation Conference, pp. 580-586,1990. [8] H-K. T. Ma, S. Devadas, A. R. Newton, and A. SangiovaniVicentelli, "Test Generation for Sequential Circuits," IEEE, Transactions on Computer Aided-Design., vol. CAD-7, pp. 1081-1093, Oct. 1988. [9] T. M. Niermann and J. H. Patel, "HITEC: A Test Generation Package for Sequential Circuits," European Design Automation Conference, pp. 214-218,1991. [10] W.-T. Cheng, "The BACK Algorithm for Sequential Test Generation," International Conference on Computer Aided Design, pp. 214-218,1991. [11] S. Patil and P. Banerjee, "A Parallel Branch and Bound Algorithm for Sequential Test Generation ," IEEE Transactions on Computer Aided-Design., vol. CAD-9, pp. 313-322, March, 1990. [12] S. Seshu and D. N. Freeman, "The diagnosis of asynchronous sequential switching systems," IRE Transactions on Electronic Computing, vol. EC-11, pp. 459-465, August 1962 [13] M. A. Breuer, "A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits," IEEE Transactions on Computers, vol. C-20, pp. 459-465., Nov. 1971. [14] T. Ono and M. Yoshida, "A test Generation Method for Sequential Circuits Based on Maximum Utilization of Intemal States," ITC91. [15] K. Hatayama and K. Hikone, "Sequential Test Generation Based on Real-Valued Logic Simulation," ITC92. [16] K. T. Cheng and V. D. Agrawal, Unified Methods for VLSI Simulation and Test Generation. Boston, MA: Kluwer Academic Publishers, 1989. [17] D. E. Goldberg. Genetic Algorithms in Search, Optimization and Machine Learning. Massachusetts: Addison-Wesley, 1989. [18] Daniel G. Saab, Youssef G. Saab, and Jacob Abraham, "CRIS : A Test Cultivation Program for Sequential VLSI Circuits," IEEE International Conference on Computer Computer Aided Design, 1992. [19] E.M. Rudnick, J. G. Holm, D. G. Saab, and J. H. Patel, "Application of Simple Genetic Algorithms to Sequential Circuit Tesd generation," Proc. European Design and Test Conference, 1994. [20] E.M. Rudnick, J. H. Patel, G. S. Greenstein, and T. M. Niermann, "Sequential Circuit Tesd generation in a Genetic Algorithm Framework," Proc. ACM/IEEE Design Automation Conference, 1994. [21] D. G. Saab, Robert B. Mueller-Thuns, David Blaauw, Jacob A. Abraham, and Joseph T. Rahmeh, "Hierarchical Multi-level Fault Simulation of Large Systems," JETTA Journal of Electric Testing: Theory and Applications, vol. 1, pp. 139-149, March, 1990. [22] Kenneth DeJong, "Solving NP-Complete Problems with Genetic Algorithms," International Conference on Genetic Algorithms, 1987. [23] J. P. Cohoon and W. D. Paris, "Genetic Placement," in Proc. of the IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 422-425, November 1986. [24] J. H. Holland, "Adaptation in Natural and Artificial Systems," Ann Arbor: University of Michigan Press, 1975. [25] A.H. Aho, J.E. Hopcroft, and J.D. Ullman, The Design and Analysis of Computer Algorithms. Reading, MA: AddisonWesley,1974. [26] W.T. Cheng, "Split Circuit Model for Test Generation," Proc. 25th IEEE Design Automation Conference, pp. 96-101, June, 1988. [27] F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. of the Int. Test Conf, pp. 785-794,1985. [28] F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," in Proceedings of the 1989 Int. Symp. on Circuits and Systems, Portland, Oregon, May 1989. ICCAD94, Pages 44-47 Analytical Fault Modeling and Static Test Generation for Analog ICs Giri Devarayanadurg and Mani Soma Department of Electrical Engineering, University of Washington, Seattle, WA 98195 Abstract Static tests are key in reducing the current high cost of testing analog and mixed-signal ICs. A new DC test generation technique for detecting catastrophic failures in this class of circuits is presented. To include the effect of tolerance of parameters during testing, the test generation problem is formulated as a minimax optimization problem, and solved iteratively as successive linear programming problems. An analytical fault modeling technique, based on manufacturing defect statistics is used to derive the fault list for the test generation. Using the technique presented here an efficient static test set for analog and mixed-signal ICs can be constructed, reducing both the test time and the packaging cost. References [1] A.Meixner and W.Maly, “Fault Modelling for the Testing of Mixed Integrated Circuits”, Proc. IEEE Intl. Test Conf., pp. 564-572, 1991 [2] M.Soma, “An Experimental Approach to Analog Fault Models”, Proc. IEEE Custom Integrated Circuits Conf., pp.13.6.1-13.6.4, 1991 [3] L.Milor and A.Sangiovanni-Vincentelli, “Optimal Test Set Design for Analog Circuits”, Proc. ICCAD, pp. 294297, 1990. [4] C.Stapper, “Modeling of Integrated Circuit Defect Sensitivities”, IBM J. Res. Develop., Vol. 27, No. 6, Nov. 1983. [5] Shen-Jen Tsai, “Test Vector Generation for Linear Analog Devices”, Proc. IEEE International Test Conference, pp. 592-597, 1990. [6] Naveena Nagi and J.A.Abraham, “Fault-based Automatic Test Generator for Linear Analog Circuits”, Proc. of ICCAD, pp. 88-91, 1993. [7] L.Milor and V.Visvanathan, “Detection of Catastrophic Faults in Analog Integrated Circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-8, no.2, pp. 114-130, Feb.1989. [8] I.Chen and A.J.Strojwas, “Realistic Yield Simulation for VLSIC Structural Failures”, IEEE Trans. on ComputerAided Design, Vol. CAD-6, No.6, Nov. 1987. [9] D.M.H Walker, “Yield Simulation for Integrated Circuits”, Kluwer Academic Publishers, pp. 163, 1987. [10] M.Jarwala and S.J.Tsai, “A Framework for Testability of Mixed Analog/Digital Circuits”, Proc. IEEE Custom Integrated Circuits Conf., pp.13.5.1-13.5.4, 1991 ICCAD94, Pages 50-55 Efficient Network Flow Based Min-Cut Balanced Partitioning Honghua Yang and D. F. Wong Department of Computer Sciences, University of Texas at Austin, Austin, Texas 78712 Abstract We consider the problem of bipartitioning a circuit into two balanced components that minimizes the number of crossing nets. Previously, the Kernighan and Lin type (K&L) heuristics, the simulated annealing approach, and the spectral method were given to solve the problem. However, network ow techniques were overlooked as a viable approach to min-cut balanced bipartition due to its high complexity. In this paper we propose a balanced bipartition heuristic based on repeated max-ow min-cut techniques, and give an efficient implementation that has the same asymptotic time complexity as that of one max-ow computation. We implemented our heuristic algorithm in a package called FBB. The experimental results demonstrate that FBB outperforms the K&L heuristics and the spectral method in terms of the number of crossing nets, and the efficient implementation makes it possible to partition large circuit instances with reasonable runtime. For example, the average elapsed time for bipartitioning a circuit S35932 of almost 20K gates is less than 20 minutes. References [BRSV87] R. K. Brayton, R. Rudell, and A. L. Sangiovanni-Vincentelli. MIS: A Multiple-Level Logic Optimization. IEEE Trans. on CAD, pages 1061-1081, Nov. 1987. [CHK92] J. Cong, L. Hagen, and A. Kahng. Net Partitions Yield Better Module Partitions. In Proc. of the 29th ACM/IEEE Design Automation Conf., pages 47-52, 1992. [DA94] A. Dasdan and C. Aykanat. Improved Multiple-Way Circuit Partitioning Algorithms. In Int'l ACM/SIGDA Workshop on Field Programmable Gate Arrays, Feb. 1994. [Don88] W. E. Donath. Logic Partitioning. Preas and Lorenzetti eds., Benjamin/Cummings, 1988. [Eve79] S. Even. Graph Algorithms. Computer Science Press, 1979. [FF62] J. R. Ford and D. R. Fulkerson. Flows in Networks. Princeton University Press, 1962. [FM82] C. M. Fiduccia and R. M. Mattheyses. A Linear Time Heuristic for Improving Network Partitions. In Proc. of the ACM/IEEE Design Automation Conf., pages 175-181, 1982. [GJ79] M. Garey and D. S. Johnson. Computers and intractability: A Guide to the Theory of NPCompleteness. W. H. Freeman, 1979. [HK91] L. Hagen and A. B. Kahng. Fast Spectral Methods fo Ratio Cut Partitioning and Clustering. In Proc. of the IEEE Int'l Conf. on Computer-Aided Design, pages 10-13, Nov. 1991. [HM85] T. C. Hu and K. Moerder. Multiterminal Flows in a Hypergraph. Hu and Kuh eds., IEEE Press, 1985. [IWW93] E. Ihler, D. Wagner, and F. Wager. Modeling Hypergraphs by Graphs with the Same Min-Cut Properties. In Info. Proc. Letters, 45, pages 171-175, 1993. [KGV83] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by Simulated Annealing. Science, pages 671680, May 1983. [KL70] B. Kernighan and S. Lin. An Efficient Heuristic Procedure for Partitioning of Electrical Circuits. Bell System Technical Journal, pages 291-307, Feb. 1970. [Kri84] B. Krishnamurthy. An Improved Min-Cut Algorithm for Partitioning VLSI networks. IEEE Trans. on Computers, pages 438-446, May 1984. [Law76] E. Lawler. Combinatorial Optimization: Networks and Matroids. Holt, Rinehart& Winston, New York, 1976. [RDF94] B. M. Riess, K. Doll, and M. J. Frank. Partitioning Very Large Circuits Using Analytical Placement Techniques. In Proc. 31th ACM/IEEE Design Automation Conf., pages 646-651, 1994. [San89] L. A. Sanchis. Multiway Network Partitioning. IEEE Trans. on Computers, pages 62-81, Jan. 1989. ICCAD94, Pages 56-62 Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation Jason Cong, Wilburt Labio, and Narayanan Shivakumar UCLA Computer Science Department, University of California, Los Angeles, CA 90024 Abstract In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN). Given a netlist, we first compute a K-way partition of the nets based on the HDN representation, and then transform a K-way net partition into a K-way module partitioning solution. The main contribution of our work is the formulation and solution of the K-way module contention (K-MC) problem, which determines the best assignment of the modules in contention to partitions, while maintaining user-specified area requirements, when we transform the net partition into a module partition. Under a natural definition of binding factor between nets and modules, and preference function between partitions and modules, we show that the K-MC problem can be reduced to a min-cost max-flow problem. We present efficient solutions to the K-MC problem based on network flow computation. Extensive experimental results show that our algorithm consistently outperforms the conventional K-FM partitioning algorithm by a significant margin. References [AlKa93] Alpert, C. J. and A. B. Kahng, ‘‘Geometric Embeddings for Faster (and Better) Multi-Way Netlist Partitioning,’’ Proc. ACM/IEEE Design Automation Conf., pp. 743-748, June 1993. [Bo87] Boppana, R., ‘‘Eigenvalues and Graph Bisection: An Average-Case Analysis,’’ IEEE Symp. on Foundations of Computer Science, pp. 280-285, 1987. [ChSZ93] Chan, P., M. Schlag, and J. Zien, ‘‘Spectral K-Way Ratio-Cut Partitioning and Clustering,’’ Proc. 30th ACM/IEEE Design Automation Conf., June 1993. [CoHK91] Cong, J., L. Hagen, and A. Kahng, ‘‘Random Walks for Circuit Clustering,’’ IEEE 4th Int’l ASIC Conf., pp. P14-2.1, Sept. 1991. [CoHK92] Cong, J., L. Hagen, and A. Kahng, ‘‘Net Partitions Yield Better Module Partitions,’’ IEEE 29th Design Automation Conference, pp. 47-52, June 1992. [CoLB94] Cong, J., Z. Li, and R. Bagrodia, ‘‘Acyclic Multi-Way Partitioning of Boolean Networks,’’ Proc. ACM/IEEE 31st Design Automation Conf., pp. 670-675, June 1994. [CoLS94] Cong, J., W. Labio, and N. Shivakumar, ‘‘Multi-Way VLSI Circuit Partitioning Based on Dual Net Representation,’’ in UCLA Computer Science Department Tech. Report CSD-940029, (Aug. 1994). [CoSm93] Cong, J. and M. Smith, ‘‘A Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Designs,’’ ACM/IEEE Design Automation Conf., pp. 755-760, June 1993. [FiMa82] Fiduccia, C. and R. Mattheyses, ‘‘A Linear Time Heuristic for Improving Network Partitions,’’ ACM/IEEE Design Automation Conf., pp. 175-181, 1982. [FoFu62] Ford, L. R. and D. R. Fulkerson, Flows in Networks, Princeton Univ. Press, Princeton, N.J. (1962). [HaKa91] Hagen, L. and A. B. Kahng, ‘‘Fast spectral methods for ratio cut partitioning and clustering,’’ Proc. ICCAD-91, pp. 10--13, 1991. [HaKa92] Hagen, L. and A. Kahng, ‘‘A New Approach to Effective Circuit Clustering,’’ Int’l Conf. on ComputerAided Design , pp. 422-427, Nov. 1992. [HaKa92b] Hagen, L. and A. B. Kahng, ‘‘New Spectral Methods for Ratio Cut Partitioning and Clustering,’’ IEEE Trans. on CAD, pp. 1074-1085, Sept. 1992. [KeLi70] Kernighan, B. and S. Lin, ‘‘An Efficient Heuristic Procedure for Partitioning of Electrical Circuits,’’ Bell System Technical J., Feb. 1970. [KiGV83] Kirkpatrick, S., C. D. Gelat, and M. P. Vecchi, Jr., ‘‘Optimization by Simulated Annealing,’’ Science, Vol. 220, pp. 671-680, May, 1983. [Kr84] Krishnamurthy, B., ‘‘An Improved Min-Cut Algorithm for Partitioning VLSI Networks,’’ IEEE Trans. on Computers, Vol. 33, pp. 438-446, 1984. [Sa89] Sanchis, L., ‘‘Multiple-Way Network Partitioning,’’ IEEE Trans. on Computers, Vol. 38, pp. 62-81, 1989. [YeCL91] Yeh, C. W., C. K. Cheng, and T. T. Lin, ‘‘A General Purpose Multiple-Way Partitioning Algorithm,’’ Proc. 28th ACM/IEEE Design Automation Conf., June 1991. [YeCL92] Yeh, C. W., C. K. Cheng, and T. T. Lin, ‘‘A Probabilistic Multicommodity-Flow Solution to Circuit Clustering Problems,’’ Int’l Conf. on Computer-Aided Design, pp. 428-431, Nov. 1992. ICCAD94, Pages 63-67 A General Framework for Vertex Orderings, With Applications to Netlist Clustering C. J. Alpert and A. B. Kahng UCLA Computer Science Department, Los Angeles, CA 90024-1596 Abstract We present a general framework for the construction of vertex orderings for netlist clustering. Our WINDOW algorithm constructs an ordering by iteratively adding the vertex with highest attraction to the existing ordering. Variant choices for the attraction function allow our framework to subsume many graph traversals and clustering objectives from the literature. The DP-RP method of [3] is then applied to optimally split the ordering into a k-way clustering. Our approach is adaptable to user-specified cluster size constraints. Experimental results for clustering and multi-way partitioning are encouraging. References [1] C. J. Alpert and A. B. Kahng, “A General Framework for Vertex Orderings, With Applications to Netlist Clustering," UCLA tech. report #940018, April 1994. [2] C. J. Alpert and A. B. Kahng, “GeometricEmbeddings for Faster and Better Multi-way Netlist Partitioning," Proc. ACM/IEEE Design Automation Conf. 1993, pp. 743-748. [3] C. J. Alpert and A. B. Kahng, “Multi-way Partitioning Via Spacefilling Curves and Dynamic Programming," Proc. ACM/IEEE Design Automation Conf., 1994, pp. 652-657. [4] T. N. Bui, “Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms", in Proc. ACM/IEEE Design Automation Conf., 1989, pp. 775-778. [5] P. K. Chan, M. D. F. Schlag and J. Zien, “SpectralK-Way Ratio Cut Partitioning and Clustering", Proc. Symp. on Integrated Systems, Seattle, March 1993. [6] J. Cong and M. Smith “A Parallel Bottom-up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design" Proc. ACM/IEEE Design Automation Conf. 1993, pp. 755-760. [7] J. Cong, L. Hagen and A. B. Kahng, “Random Walks for Circuit Clustering", Proc. 4th IEEE Intl. ASIC Conf., Rochester, September 1991, pp. 14.2.1 - 14.2.4. [8] C.M Fiduccia and R.M. Mattheyses, “A Linear Time Heuristic for Improving Network Partitions", Proc. ACM/IEEE Design Automation Conf., June 1982, pp. 175-181. [9] L. Hagen and A. B. Kahng, “A New Approach to Effective Circuit Clustering", Proc. IEEE Intl. Conf. on Computer-Aided Design, Santa Clara, Nov. 1992, pp. 422-427. [10] L. Hagen and A. B. Kahng, “New Spectral Methods for Ratio Cut Partitioning and Clustering", IEEE Trans. on CAD 11(9), Sept. 1992, pp. 1074-1085. [11] K.M. Hall, “An r-dimensional Quadratic Placement Algorithm", Manag. Sci., 17(1970), pp.219-229. [12] H. Nagamochi and T. Ibaraki, “Computing Edge-Connectivity in Multigraphs and Capacitated Graphs", Siam J. of Disc. Math. 5(1), Feb. 1992, pp. 54-66. [13] S. Pissanetsky, Sparse Matrix Technology, Academic Press Inc., 1984. [14] B. M. Riess, K. Doll, and F. M. Johannes, “Partitioning Very Large Circuits Using Analytical Placement Techniques", Proc. ACM/IEEE Design Automation Conf., 1994, pp. 646-651. [15] W. Sun and C. Sechen, “Efficient and Effective Placements for Very Large Circuits" Proc. IEEE Intl. Conf. on Computer-Aided Design, Santa Clara, Nov. 1993, pp. 170-177. ICCAD94, Pages 70-73 Re-Encoding Sequential Circuits to Reduce Power Dissipation Gary D. Hachtel1, Mariano Hermida2, Abelardo Pardo1, Massimo Poncino3, Fabio Somenzi1 1 University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO 80309 2 Universidad Politecnica De Madrid, Facultad Informatica, Madrid, Spain 3 Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, ITALY 10129. Abstract We present a fully implicit encoding algorithm for minimization of average power dissipation in sequential circuits, based on the reduction of the average number of bit changes per state transition. We have studied two novel schemes for this purpose, one based on recursive weighted non-bipartite matching, and one on recursive mincut bi-partitioning. We employ ADDs (Algebraic Decision Diagrams) to computate the transition probabilities, to measure potential area saving, and in the encoding algorithms themselves. Our experiments show the effectiveness of our method in reducing power dissipation for large sequential designs. References [1] R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi. Algebraic decision diagrams and their applications. In Proceedings of the International Conference on Computer-Aided Design, pages 188-191, Santa Clara, CA, November 1993. [2] S. Devadas, H.-K. T. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli. MUSTANG: State assignment of finite state machines for optimal multi-level logic implementations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-7:1290-1300, December 1988. [3] T. A. Dolotta and E. J. McCluskey. The coding of internal states of sequential machines. IEEE Transactions on Electronic Computers, EC-13:549-562, October 1964. [4] X. Du, G. D. Hachtel, and P. H. Moceyunas. MUSE: A MUltilevel Symbolic Encoding algorithm for state assignment. In Proceedings of the Hawaii International Conference on Systems Science, pages 367-376, January 1990. [5] J. Edmonds. Paths, trees and flowers. Canadian Journal of Mathematics, 17:449-467, 1965. [6] A. Ghosh, S. Devadas, K. Keutzer, and J. White. Estimation of average switching activity in combinational and sequential circuits. In Proceedings of the Design Automation Conference, pages 253-259, Anaheim, CA, June 1992. [7] G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi. Probabilistic analysis of large finite state machines. In Proceedings of the Design Automation Conference, San Diego, CA, June 1994. [8] G. D. Hachtel and F. Somenzi. A symbolic algorithm for maximum flow in 0-1 networks. In Proceedings of the International Conference on Computer-Aided Design, pages 403-406, Santa Clara, CA, November 1993. [9] F. N. Najm. Transition density, a stochastic measure of activity in digital circuits. In Proceedings of the Design Automation Conference, pages 644- 649, San Francisco, CA, June 1991. [10] K. Roy and S. Prasad. SYCLOP: Synthesis of CMOS logic for low power applications. In Proceedings of the International Conference on Computer Design, pages 464-467, Cambridge, MA, October 1992. ICCAD94, Pages 74-81 Precomputation-Based Sequential Logic Optimization for Low Power Mazhar Alidina, José Monteiro, Srinivas Devadas Department of EECS, MIT, Cambridge, MA Abhijit Ghosh MERL, Sunnyvale, CA Marios Papaefthymiou Department of EE, Yale University, CT Abstract We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. We present an automatic method of synthesizing pre-computation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Upto 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay. References [1] M. Alidina. Precomputation-Based Sequential Logic Optimization for LowPower. Master's thesis, Massachusetts Institute of Technology, May 1994. [2] P. Ashar, S. Devadas, and K. Keutzer. Path-Delay-Fault Testability Properties of Multiplexor-Based Networks. INTEGRATION, the VLSI Journal, 15(1):1-23, July 1993. [3] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. MIS: A Multiple-Level Logic Optimization System. In IEEE Transactions on Computer-Aided Design, volume CAD-6, pages 1062-1081, November 1987. [4] R. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, C35(8):677-691, August 1986. [5] A. Chandrakasan, T. Sheng, and R. W. Brodersen. Low Power CMOS Digital Design. In Journal of Solid State Circuits, pages 473-484, April 1992. [6] S. Devadas, A. Ghosh, and K. Keutzer. Logic Synthesis. McGraw Hill, New York, NY, 1994. [7] A. Ghosh, S. Devadas, K. Keutzer, and J. White. Estimation of Average Switching Activity in Combinational and Sequential Circuits. In Proceedings of the 29th Design Automation Conference, pages 253-259, June 1992. [8] J. Monteiro, S. Devadas, and A. Ghosh. Retiming Sequential Circuits for Low Power. In Proceedings of the Int'l Conference on Computer-Aided Design, pages 398-402, November 1993. [9] J. Monteiro, S. Devadas, and B. Lin. A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. In Proceedings of the 31st Design Automation Conference, pages 12-17, June 1994. [10] F. Najm. Transition Density, A Stochastic Measure of Activity in Digital Circuits. In Proceedings of the 28th Design Automation Conference, pages 644- 649, June 1991. [11] K. Roy and S. Prasad. SYCLOP: Synthesis of CMOS Logic for Low Power Applications. In Proceedings of the Int'l Conference on Computer Design: VLSI in Computers and Processors, pages 464-467, October 1992. [12] A. Shen, S. Devadas, A. Ghosh, and K. Keutzer. On Average Power Dissipation and Random Pattern Testability of Combinational Logic Circuits. In Proceedings of the Int'l Conference on Computer-Aided Design, pages 402-407, November 1992. [13] C-Y. Tsui, M. Pedram, and A. Despain. Exact and Approximate Methods for Switching Activity Estimation in Sequential Logic Circuits. In Proceedings of the 31st Design Automation Conference, pages 18-23, June 1994. ICCAD94, Pages 82-87 Low Power State Assignment Targeting Two- and Multi-level Logic Implementations Chi-Yang Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain Department of Electrical Engineering – Systems, University of Southern California, Los Angeles, CA 90089 Abstract The problem of minimizing power consumption during the state encoding of a finite state machine is considered. A new power cost model for state encoding is proposed and encodig techniques that minimize this power cost for two- and multi-level logic implementations are described. These techniques are compared with those which minimize area or the switching activity at the present state bits. Experimental results show significant improvements. References [ 1 ] S. Devadas, H-K. T. Ma, A. R Newton, and A. Sangiovanni-Vincentelli. MUSTANG: State aesignment of finite state machines targeting multi-level logic implementations. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 7, pages 1290-1300, December 1988. [2] B. Lin and A. R. Newton. Synthesis of multiple-level logic from symbolic high-level description languages. In IFIP International Conference on Very Large Scale Integration, pages 187-196, August 1989. [3] G. DeMicheli. Symbolic design of combinational and sequential logic circuits implemented by two-level macros. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 5, pages 597-616, September 1986. [4] G. DeMicheli, R K. Brayton, and A. Sangiovanni-Vincentelli. Optimal state assignment of finite state machines. I n IEEE Transactions on Compuuter-Aided Design of Integrated Circuits and Systems, volume 4, pages 269-285, July 1985. [5] E. Olson and S. M. Kang. Low power state assignment for finite state machines search. In International Workshop on Low Power Design, pages 63-68, April 1994. [6] A. Papoulis. Probability, Random Variables and Stochastic Processes. McGraw-Hill, 1984. [7] K. Roy and S. Prasad. Syclop: Synthesis of CMOS logic for low power application. In Proceedings of the International Conference on Computer Design, pages 464-467, October 1992. [8] R. Rudell. Logic Synthesis for VLSI Design. PhD thesis, University of California, Berkeley, 1989. [9] C-Y. T s u i , M. Pedram, and A. M. Despain. Exact and approximate methods for calculating signal and transition probabilities in fsms. In Proceedings of the 31th Design Automation Conference, pages 18-23, June 1994. [10] T. Villa and A. Sangiovanni-Vincentelli. NOVA: State assignment of finite state machines for optimal two-level logic implementations. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 9, pages 905-924, September 1990. [11] S. Yang and M. Ciesielski. On the relationship between input encoding and logic minimization. In Proceedings of the Twenty Third Hawaii International Conference on the System Sciences, volume I, pages 377-386, January 1990 ICCAD94, Pages 90-95 Algorithm Selection: A Quantitative Computation-Intensive Optimization Approach Miodrag Potkonjak C&C Research Laboratories NEC USA Princeton, NJ 08540 Jan Rabaey Dept. of EECS University of California at Berkeley Berkeley, CA 94720 Abstract Given a set of specifications for a targeted application, algorithm selection refers to choosing the most suitable algorithm for a given goal, among several functionally equivalent algorithms. We demonstrate an extraordinary potential of algorithm selection for achieving high throughput, low cost, and low power implementations. We introduce an efficient technique for low-bound evaluation of the throughput and cost during algorithm selection and propose a relaxation-based heuristic for throughput optimization. We also present an algorithm for cost optimization using algorithm selection. The effectiveness of methodology and algorithms is illustrated using examples. References: [1] D.P. Bertsekas, J.N. Tsitsiklis: “Parallel and Distributed Computation: Numerical Methods”, Prentice Hall, Englewood Cliffs, NJ, 1989. [2] R.E. Blahut: “Fast Algorithms for Digital Signal Processing”, Addison-Wesley, 1985. [3] P. Chou, R. Ortega, G. Borrielo: “Synthesis of Mixed Hardware-Software Interfaces in Microcontroller-Based Systems”, Proc. of IEEE ICCAD-92, pp. 488-495, 1992. [4] J. Darlington: “An experimental program transformation and synthesis system”, Artificial Intelligence, Vol. 16, No. 1, pp. 1-46, 1981. [5] R.K. Gupta, C.N. Coehlo, G. De Micheli: “Program Implementation Schemes for Hardware-Software System”, IEEE Computer, Vol. 27, No. 1, pp. 48-55, 1994 [6] A. Kalavade, E.A. Lee: “A Hardware-Software Codesign Methodology for DSP Applications”, IEEE Design & Test of Computers, Vol. 10, No. 3, pp. 16-28, 1993. [7] M. Potkonjak, J.Rabaey “A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs”, 26th IEEE/ACM Design Automation Conference, pp. 7-12, 1989. [8] M. Potkonjak, J.Rabaey: “Algorithm Selection: A quantitative computation-intensive optimization approach”, Technical Report, 1994. [9] J. Rabaey, C. Chu, P. Hoang, M. Potkonjak: “Fast Prototyping of Datapath-Intensive Architectures”, IEEE Design and Test of Computers, Vol. 8, No. 2, pp. 40-51, June 1991. [10] J.M. Rabaey, M. Potkonjak: “Estimating Implementation Bounds for Real Time DSP Application Specific Circuits”, IEEE Trans. on CAD of IC, Vol. 13, No. 6, pp. 669-683, 1994. [11] K.R. Rao, P. Yip: “Discrete Cosine Transform”, Academic Press, Inc., San Diego, CA 1990. [12] M.B. Srivastava, R. Brodersen: “Rapid-Prototyping of Hardware and Software in a Unified Framework”, Proc. of IEEE ICCAD-92, pp. 152-155, 1992. [13] W. Wolf: “Hardware-Software Co-Design of Embedded Systems”, Proc. of the IEEE, Vol. 82, No. 7, page 967989, 1994. [14] W. Ye, R. Ernst, T. Benner, J. Henkel: “Fast Timing Analysis for Hardware-Software Co-Synthesis”, 1993 IEEE International Conference on Computer Design, pp. 452-457, 1994. ICCAD94, Pages 96-100 Adaptation of Partitioning and High-Level Synthesis in Hardware/Software Co–Synthesis Jörg Henkel, Rolf Ernst, Ullrich Holtmann, Thomas Benner Institut für Datenverarbeitungsanlagen, Technische Universität Braunschweig, Hans–Sommer–Str. 66, D–38106 Braunschweig, GERMANY Henkel@ida.ing.tu–bs.de Abstract Previously, we had presented the system COSYMA for hardware/software co-synthesis of small embedded controllers [ErHeBe93]. Target system of COSYMA is a core processor with application specific co–processors. The system speedup for standard programs compared to a single 33MHz RISC processor solution with fast, single cycle access RAM was typically less than 2 due to restrictions in high-level co–processor synthesis, and incorrectly estimated back end tool performance, such as hardware synthesis, compiler optimization and communication optimization. Meanwhile, a high-level synthesis tool for highperformance co–processors in cosynthesis has been developed. This paper explains the requirements and the main features of the high-level synthesis system and its integration into COSYMA. The results show a speedup of 10 in most cases. Compared to the speedup, the co–processor size is very small. References [ErHeBe93] R. Ernst, J. Henkel, Th. Benner, Hardware-Software Cosynthesis for Microcontrollers, IEEE Design & Test of Computers, pp. 64–75, Dec. 1993. [GuCoMi92] R.K. Gupta, C.N. Coelho, G.D. Micheli, Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components, Proc. of DAC’92, pp. 225–230, 1992. [GuMi92] R.K. Gupta, G.D. Micheli, System-level Synthesis using Re-programmable Components, Proc. of EDAC’92, pp. 2–7, 1992. [Ho93] U. Holtmann, High–Level Synthese mit BSS für den Einsatz im Hardware/Software Codesign (High–Level Synthesis with BSS for Usage in Hardware/Software Codesign), Internal Report 931126-1, Institut f. Entwurf Integrierter Schaltungen, Technical University of Braunschweig, Germany, 1993. [HoEr93a] U. Holtmann, R. Ernst, Experiments with Low-Level Speculative Computation Based on Multiple Branch Prediction, IEEE Trans on VLSI, Vol. 1, No. 3, Sep. 1993. [KuMi91] D.C. Ku, D. De Micheli, Constrained resource sharing and conflict resolution in Hebe, Elsevier, INTEGRATION, the VLSI journal 12, pp. 131–165, 1991. [OG89] R. Otten, P. van Ginneken, The Annealing Algorithm, Kluwer, 1989. [YErBeHe93] W. Ye, R. Ernst, Th. Benner, J. Henkel, Fast Timing Analysis for Hardware-Software Co-Synthesis, Proc. of ICCD 1993, IEEE Society Press, pp. 452–457, 1993. ICCAD94, Pages 101-108 Synthesis of Concurrent System Interface Modules with Automatic Protocol Conversion Generation Bill Lin, Steven Vercauteren IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, Email:fbilllin,vercautg@imec.be Abstract We describe a new high-level compiler called Integral for designing system interfacemodules. The input is a high-level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computations, abstract communication, and low-level behavior. For abstract communication between two communicating modules that obey different I/O protocols, the necessary protocol conversion behaviors are automatically synthesized using a Petri net theoretic approach. We present a synthesis trajectory that can synthesize the necessary hardware resources, control circuitry, and protocol conversion behaviors for implementing system interface modules. References [1] V. Akella and G. Gopalakrishnan. Shilpa: a high-level synthesis system for self-timed circuits. In InternationalConference onComputer-AidedDesign,November 1992. [2] T. Amon, H. Hulgaard, S. Burns, and G. Borriello. An algorithmfor exact bounds on the time separation of events in concurrent systems. In IEEE International Conference on Computer Design, October 1993. [3] P.A. Beerel and T. Meng. Automatic gate-level synthesis of speed-independent circuits. In InternationalConference onComputer-AidedDesign,November 1992. [4] G. Borriello. A new interface specification methodology and its application to transducer synthesis. Ph.D thesis, University of California, Berkeley, May, 1988. [5] E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In International Conference on Computer-Aided Design, November 1989. [6] T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. Technical ReportMITLCS-TR-393, 1987. [7] G. de Jong and B. Lin. A communicating Petri net model for the design of concurrent asynchronous modules. In ACM/IEEEDesign AutomationConference, June 1994. [8] D. Doukas and A. S. LaPaugh. Clover : A timing constraints verification system. In 28th ACM/IEEE Design Automation Conference, June 1991. [9] C. A. R. Hoare. Communicating sequential processes. Communications of the ACM, pages 666–677,August 1978. [10] A. Kondratyev,M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independendent circuits. In ACM/IEEE Design Automation Conference, June 1994. [11] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronous circuits. In ACM/IEEE Design Automation Conference, June 1991. [12] Ch. Ykman Couvreur, P. Vanbekbergen, and B. Lin. Assassin: An Asynchronous I/OInterface Synthesis System. Tutorial and referencemanual. IMECLab.,October 1993. [13] Alain J. Martin. Compiling communicating processes into delay-insensitiveVLSI circuits. Distributed Computing, 1:226–234, 1986. [14] K. McMillan and D.L. Dill. Algorithms for interface timing verification. In IEEE InternationalConference on Computer Design, October 1992. [15] J.L. Peterson. Petri Net Theory and the Modelling of Systems. Prentice-Hall Inc., EnglewoodCliffs, NJ, 1981. [16] J. S. Sun and R. W. Brodersen. Design of system-level interfaces. In Proceedings of the InternationalConference on Computer-Aided Design, November, 1992. [17] I. E. Sutherland. Micropipelines. Communications of the ACM. The 1988 ACM Turing Award Lecture., June 1989. [18] P. Vanbekbergen, B. Lin, G. Goossens, and H. De Man. A generalized state assignment theory for transformations on signal transition graphs. In International Conference on Computer-Aided Design, November 1992. [19] P. Vanbekbergen, G. Goossens, and H. De Man. Specification and analysis of timing constraints in signal transition graphs. In European Design Automation Conference,March 1992. [20] K. van Berkel. Handshake circuits: an intermediary between communicating processes and VLSI. Ph.D thesis, Philips Research Laboratories, Eindhoven, The Netherlands, 1992. [21] VITA. VMEbus specification manual. PRINTEX Publishing, 1985. ICCAD94, Pages 110-116 An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures Sybille Hellebrand, Hans-Joachim Wunderlich Institute of Computer Structures, University of Siegen, Germany Abstract The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some serious drawbacks concerning the fault coverage, the system speed and the area overhead. A synthesis technique is presented which uses the additional test register also to implement the system function by supporting self-testable pipeline-like controller structures. It will be shown, that if the need of two different registers in the final structure is already taken into account during synthesis, then the over-all number of flipflops can be reduced, and the fault coverage and system speed can be enhanced. The presented algorithm constructs realizations of a given finite state machine specification which can be trivially implemented by a self-testable structure. The efficiency of the procedure is ensured by a very precise characterization of the space of suitable realizations, which avoids the computational overhead of previously published algorithms References 1 V. D. Agrawal, C. R. Kime, K. K. Saluja: A Tutorial on Built-In Self-Test, Part 1: Principles, IEEE Design & Test of Computers, Vol. 10, No. 1, March 1993, pp. 73-82 2 P. Ashar, S. Devadas: Irredundant Interacting Sequential Machines Via Optimal Logic Synthesis, IEEE Trans. on CAD, Vol. 10, No. 3, March 1991, pp. 311-325 3 P. Ashar, S. Devadas, A. R. Newton: A Unified Approach to the Decomposition and Re-decomposition of Sequential Machines, Proc 27th ACM/IEEE Int. Design Automation Conf., 1990, pp. 601-606 4 Z. Barzilai, D. Coppersmith, A. L. Rosenberg: Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing, IEEE Trans. on Computers, Vol. c-32, No. 2, February 1983, pp. 190 -194 5 R. K. Brayton, G. D. Hachtel, C. T. McMullen: Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Boston, The Hague, Dordrecht, Lancaster, 1984. 6 R. K. Brayton et al.: MIS: A Multiple-Level Logic Optimization System, IEEE Trans. on CAD, Vol. CAD-6, No.6, 1987, pp. 1062-1081 7 V. D. Agrawal, K.-T. Cheng: Finite State Machine Synthesis with Embedded Test Function, Journal of Electronic Testing Theory and Applications, Vol. 1, No. 3, October 1990, pp. 221-228 8 K.-T. Cheng, V. D. Agrawal: State Assignment for Testable Design, Int. Journal of Computer Aided VLSI Design, Vol. 3., March 1991 9 W. Daehn, J. Mucha: Hardware Test Pattern Generation for Built-In Test, Proc. IEEE Int. Test Conf., Philadelphia, 1981, pp. 100 - 113 10 S. Devadas, K. Keutzer. A Unified Approach to the Synthesis of Fully Testable Sequential Machines, IEEE Trans. on CAD, Vol. 10, No. 1. January 1991, pp. 39-50 11 S. Devadas et al.: MUSTANG: State Assignment of Finite State Machines Targeting Mulitlevel Logic Implementations, IEEE Trans. on CAD, Vol, 7, No. 12, Dec. 1988, pp. 1290-1300 12 B. Eschermann, H.-J. Wunderlich: Parallel Self-Test and the Synthesis of Control Units, Proc. 2nd European Test Conf., Munich, 1991 13 B. Eschermann, H-J. Wunderlich: Optimized Synthesis Techniques for Testable Sequential Circuits, IEEE Trans. on CAD, Vol. 11, No. 3, March 1992, pp. 301-312. 14 R. Gage: Structured CBIST in ASICS; Proc. IEEE Int. Test Conf., Baltimore, Maryland, 1993, pp. 332-338 15 Martin Geiger, Thomas Müller-Wipperfürth: FSM Decomposition Revisited: Algebraic Structure Theory Applied to MCNC Benchmark FSMs, Proc. 28th ACM/IEEE Design Automation Conf., San Francisco, 1991, pp. 182-185 16 J. Harttmanis, R E. Stearns: Algebraic Structure Theory of Sequential Machines, Prentice Hall, Englewood Cliffs, 1966 17 S. Hellebrand, H.-J. Wunderlich, O. Haberl: Generating Pseudo-Exhaustive Vectors for External Testing; Proc. IEEE Int. Test. Conf, Washington, D. C. 1990, pp. 670-679 18 S. Hellebrand, H.-J. Wunderlich: S y n t h e s i s o f Self-Testable Controllers, in: Proc. EDAC/ETC/EuroAsic '94, Paris, Feb. 1994, pp. 380-585 19 K. Kim, D. Ha, J. Tront: On Using Signature Registers as Pseudorandom Pattern Generators in Built-in Self Testing, IEEE Trans. on CAD, Vol. 7. 1988, pp. 91920 B. Koenemann, J. Mucha, G. Zwiehoff: Built-in Logic Block Observation Techniques, Proc. IEEE Int. T e s t Conf., Cherry Hill, N. J.,1979, pp. 37 - 4l 21 K. McElvain: IWLS'93 Benchmark Set: Version 4.0, distributed as part of the IWLS'93 benchmark distribution 22 I. Pomeranz, S. M. Reddy: Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity, Proc. IEEE 23rd Int. Symp. on Fault-Tolerant Computing, FTCS-23, Toulouse, June 1993, pp. 492-501 23 G. Saucier, M. C. De Paulet, P. Sicard: ASYL: A RuleBased System for Controller Synthesis, IEEE Trans. on CAD, Vol. CAD-6, No. 6, Nov. 1987, pp. 1088-1097 24 T. Villa, A. Sangiovanni-Vincentelli: NOVA: State Assignment of Finite State Machines for Optimal TwoLevel Logic Implementations, Proc. 26th ACM/IEEE Design Automation Conf., Las Vegas, 1989. pp. 327-332 25 P. Weiner, E. J. Smith: Optimization of Reduced Dependencies for Synchronous Sequential Machines, IEEE Trans. on Electronic Computers, Vol. EC-16, No. 6, Dec. 1967, pp. 835-847 26 H.-J. Wunderlich: Self Test Using Unequiprobable Random Patterns, Proc. IEEE 17th Int. Symp. on FaultTolerant Computing, FTCS-17, Pittsburgh, 1987, pp. 258-263 ICCAD94, Pages 117-124 Test Pattern Generation Based On Arithmetic Operations Sanjay Gupta, Janusz Rajski and Jerzy Tyszer Microelectronics and Computer Systems Lab, McGill University, Montreal, Canada H3A 2A7 Abstract Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose a novel method for implementing test pattern generators based on adders widely available in data-path architectures and digital signal processing circuits. Test patterns are generated by continuously accumulating a constant value and their quality is evaluated in terms of the pseudo-exhaustive state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and area overhead. References [1] P.H. Bardell, W.H. McAnney, and J. Savir. Built-in Test for VLSI: Pseudorandom Techniques. John Wiley & Sons, 1987. [2] B. Koenemann, J. Mucha, and G. Zwiehoff. Built-in test for complex integrated circuits. IEEE J. Solid State Circuits, SC-15:315-318, June 1980. [3] J. Rajski and J. Tyszer. Accumulator-based compaction of test responses. IEEE Tr. Comp., 42(6):643- 450, June 1993. [4] P.D. Hortensius et al. Cellular-automata-based pseudo-random number generators for built-in self test. IEEE Tr. CAD, 7(8):842-859, Aug. 1989. [5] D.E. Knuth. The Art of Computer Programming, volume 2. Addison-Wesley, 2nd edition, 1981. [6] D.T. Tang and L.S. Woo. Exhaustive test pattern generation with constant weight vectors. IEEE Tr. Comp., 32(12):1145-1150, Dec. 1983. [7] E.J. McCluskey. Verification testing - a pseudoexhaustive test technique. IEEE Tr. Comp., 33(6):541-546, June 1984. [8] J. Rajski and J. Tyszer. Recursive pseudo-exhaustive test pattern generation. IEEE Tr. Comp., 42(12):15171521, Dec. 1993. [9] S. Gupta, J. Rajski, and J. Tyszer. Arithmetic generators of pseudo-exhaustive test patterns. Submitted to IEEE Tr. Comp. ICCAD94, Pages 125-128 Random Pattern Testable Logic Synthesis Chen-Huan Chiang and Sandeep K. Gupta University of Southern California, Los Angeles, CA 90089-2562 Abstract Previous procedures for synthesis of testable logic guarantee that all faults in the synthesized circuits are detectable. However, the detectability of many faults in these circuits can be very low leading to poor random pattern testability. A new procedure to perform logic synthesis that synthesizes random pattern testable multilevel circuits is proposed. Experimental results show that the circuits synthesized by the proposed procedure tstfx are significantly more random pattern testable and smaller than those synthesized using its counterpart fast extract (fx) in SIS. The proposed synthesis procedure designs circuits that require only simple random pattern generators in built-in self-test, thereby obviating the need for complex BIST circuitry. References [1] M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. Computer Science Press, New York, N.Y., 1990. [2] P. H. Bardell, W. H. McAnney, and J. Savir. Built-In Test for VLSI: Pseudorandom Techniques. John Wiley & Sons, 1987. [3] K. A. Bartlett, R. K. Brayton, G. D. Hachtel, R. M. Jacoby, C. R. Morrison, R. Rudell, A. SangiovanniVincentelli, and A. R. Wang. Multi-Level Logic Minimization using Implicit Don't Cares. IEEE Trans. on CAD, 7(6):732-740, June 1988. [4] D. Brand. Redundancy and Don't Cares in Logic Synthesis. IEEE Trans. on Computer, C-32(10):947-952, October 1983. [5] R. K. Brayton, G. D. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Boston, MA, 1984. [6] R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang. MIS: A Mutiple-Level Logic Optimization System. IEEE Trans. on CAD, CAD-6(6):1063-1080, November 1987. [7] R. Dandapani and S. Reddy. On the Design of Logic Networks with Redundancy and Testability Considerations. IEEE Trans. on Computer, C-23(11):1139-1149, November 1974. [8] K. De and P. Banerjee. Logic Partition and Resynthesis for Testability. In Proceedings IEEE International Test Conference, pages 906-915, 1991. [9] S. K. Gupta and C.-H. Chiang. Random Pattern Testable Logic Synthesis. Technical Report CENG 94-08, University of Southern California, 1994. [10] G. Hachtel, R. Jacoby, K. Keutzer, and C. Morrison. On Properties of Algebraic Transformations and the Multifault Testability of Multilevel Logic. In Proceedings IEEE International Conference on Computer-Aided Design, pages 422-425, 1989. [11] A. Krasniewski. Can Redundancy Enhance Testability. In Proceedings IEEE International Test Conference, pages 483-491, 1991. [12] A. Krasniewski and A. Albicki. Random Testability of Redundant Circuit. In Proceedings IEEE International Conference on Computer Design, pages 424-427, 1991. [13] A. Majumdar and S. Sastry. On the Distribution of Fault Coverage and Test Length in Random Testing of Combinational Circuit. In Proceedings IEEE-ACM Design Automation Conference, pages 341-346, 1992. [14] J. Rajski and J. Vasudevamurthy. The Testability-Preserving Concurrent Decomposition and Factorization of Boolean Expressions. IEEE Trans. on CAD, 11(6):778-793, June 1992. [15] J. Savir and P. H. Bardell. On Random Pattern Test Length. IEEE Trans. on Computer, C-33(6):467-474, June 1984. [16] H. Savoj. Don't Cares in Multi-Level Network Optimization. PhD thesis, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 1992. [17] N. A. Touba and E. J. McCluskey. Automated Logic Synthesis of Random Pattern Testable Circuits. In Proceedings IEEE International Test Conference, 1994. [18] K. D. Wagner, C. K. Chin, and E. J. McCluskey. Pseudorandom Testing. IEEE Trans. on Computer, C36(3):332-343, March 1987. ICCAD94, Pages 130-136 Compression-Relaxation: A New Approach to Performance Driven Placement for Regular Architectures Anmol Mathur, C. L. Liu Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801 Abstract We present a new iterative algorithm for performance driven placement applicable to regular architectures such as FPGAs. Our algorithm has two phases in each iteration: a compression phase and a relaxation phase. We employ a novel compression strategy based on the longest path tree of a cone for improving the timing performance of a given placement. Compression might cause a feasible placement to become infeasible. The concept of a slack neighborhood graph is introduced and is used in the relaxation phase to transform an infeasible placement to a feasible one using a mincost flow formulation. Our analytical results regarding the bounds on delay increase during relaxation are validated by the rapid convergence of our algorithm on benchmark circuits. We obtain placements that have 13% less critical path delay (on the average) than those generated by the Xilinx automatic place and route tool (apr) on technology mapped MCNC benchmark circuits with significantly less CPU time than apr. References [1] T. Gao, P. M. Vaidya, C. L. Liu, A New Performance Driven Placement Algorithm, Proc. ICCAD, 1991, pp. 4447. [2] T. Gao, P. M. Vaidya, C. L. Liu, A Performance Driven Macro-Cell Placement Algorithm, Proc. 29th DAC, 1992, pp. 147-152. [3] S. Goto, An Efficient Algorithm for the Two-Dimensional Placement Problem in Electrical Circuit Layout, IEEE Trans. Circuits Syst., Vol. CAS-28, Jan. 1981, pp. 12-18. [4] M. A. B. Jackson, E. S. Kuh, Performance-Driven Placement of Cell Based ICs, Proc. 26th DAC, 1989, pp. 370375. [5] S. Kirkpatrick, C. D. Gelatt, Jr., M. P. Vecchi, Optimization by Simulated Annealing, Science, 13 May 1983, Vol. 220, No. 4598. [6] M. Marek-Sadowska, S. P. Lin, Timing-Driven Placement, Proc. ICCAD, 1989, pp. 94-97. [7] A. Mathur, C. L. Liu, Compression-Relaxation: A New Approach to Performance Driven Placement for Regular Architectures, Manuscript, 1994. [8] R. Nair, C. L. Berman, P. S. Hauge, E. J. Yoffa, Generation of Performance Constraints for Layout, IEEE Trans. CAD, Vol. 8, Aug. 1989, pp. 860-874. [9] A. Srinivasan, K. Chaudhary, E. S. Kuh, RITUAL : A Performance Driven Placement Algorithm for Small Cell ICs, Proc. ICCAD, 1991, pp. 48-51. [10] R. E. Tarjan, Data Structures and Network Algorithms, Chap. 8, SIAM, 1983. ICCAD94, Pages 137-144 A Loosely Coupled Parallel Algorithm for Standard Cell Placement Wern-Jieh Sun and Carl Sechen Department of Electrical Engineering, University of Washington, Seattle, Washington 98195 Abstract We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of our algorithm is targeted toward networks of UNIX workstations. This is the very first reported parallel algorithm for standard cell placement which yields as good or better placement results than its serial version. In addition, it is the first parallel placement algorithm reported which offers nearly linear speedup, in terms of the number of processors (workstations) used, over the serial version. Despite using the rather slow local area network as the only means of interprocessor communication, the processor utilization is quite high, up to 98% for 2 processors and 90% for 6 processors. The new parallel algorithm has yielded the best overall results ever reported for the set of MCNC standard cell benchmark circuits. Reference [1] P. Banerjee and M. Jones, “A Parallel Simulated Annealing for Standard Cell Placement on a Hypercube Computer.” Proc. Intl. Conf. on Computer-Aided Design (1986): 34-37. [2] A. Casotto, F. Romeo, and A. Sangiovanni-Vincentelli, “A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells.” Proc. Intl. Conf. on Computer-Aided Design (1986): 30-33. [3] A. Casotto, F. Romeo, and A. Sangiovanni-Vincentelli, “A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells.” IEEE Trans. on CAD, Volume 6, No. 5, pp 838-847, Sep 1987. [4] A. Casotto, A. Sangiovanni-Vincentelli, “Placement of Standard Cells Using Simulated Annealing on the Connection Machine.” Proc. Intl. Conf. on Computer-Aided Design (1987): 350-353. [5] K. Doll, F. M. Johannes, and G. Sigl, “Accurate Net Models for Placement Improvement by Network Flow Methods.” Proc. Intl. Conf. on Computer-Aided Design, 1992, pp. 594-597. [6] K. Doll, F. M. Johannes, and G. Sigl, “Domino: Deterministic Placement Improvement with Hill-climbing Capabilities.” Proc. VLSI, 1991, pp. 3b.1.1-3b.1.10. [7] R. Jayaraman and F. Darema, “Error Tolerance in Parallel Simulated Annealing Techniques.” Proc. Intl. Conf. on Computer Design (1988): 545-548. [8] M. Jones and P. Banerjee, “Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube.” Proc. 24th Design Automation Conf. (1987): 807-813. [9] S. Kim, “Improved Algorithms for Cell Placement and their Parallel Implementations,” Tech. Rep. #CRHC-9318, UILU-ENG-93-2231, University of Illinois, Urbana, IL, July 1993. [10] S. Kim, J. Chandy, B. Ramkumar, S. Parkes and P. Banerjee, “Proper- PLACE: A Portable, Parallel Algorithm for Standard Cell Placement,” Proc. 8th Int. Parallel Processing Symp., Cancun, Mexico, April 1994. [11] J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, “GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization.” IEEE Trans. on CAD, Volume 10, No. 3, 1991, pp 356-365. [12] R. Kling and P. Banerjee, “Concurrent ESP: A Placement Algorithm for Execution on Distributed Processors.” Proc. Intl. Conf. on Computer-Aided Design (1987): 354-357. [13] K. Kozminski, “Benchmarks for Layout Synthesis.” Proc. 28th Design Automation Conf., 1991, pp. 265-270. [14] S. Kravitz and R. Rutenbar, “Placement by Simulated Annealing on a Multiprocessor.” IEEE Trans. on CAD, Volume 6, No. 4, pp 534-549, Jul 1987. [15] J. Lam, J. M. Delosme, and C. Sechen, “Performance of a New Annealing Schedule.” Proc. 25th Design Automation Conf. (1988): 306-311. [16] D. Mitra, R. Romeo, and A. Sangiovanni-Vincentelli, “Convergence and Finite-Time Behavior of Simulated Annealing.” Advances in Applied Probability, Vol. 18. No. 3, pp. 747-771, 1986. [17] S. Mohan, and P. Mazumder, “Wolverines: Standard Cell Placement on a Network of Workstations.” IEEE Trans. on CAD, Volume 12, No. 9, pp 1312-26, Sep 1993. [18] J. S. Rose, D. R. Blythe, W. M. Snelgrove, and Z. G. Vranesic, “Fast, High Quality VLSI Placement on an MIMD Multiprocessor.” Proc. Intl. Conf. on Computer-Aided Design (1986): 42-45. [19] J. S. Rose, D. R. Blythe, W. M. Snelgrove, and Z. G. Vranesic, “Parallel Standard Cell Placement Algorithms with Quality Equivalent to Simulated Annealing.” IEEE Trans. on CAD, Volume 7, No. 3, pp 387-396, Mar 1988. [20] R. Rutenbar and S. Kravitz, “Layout by Annealing in a Parallel Environment.” Proc. Intl. Conf. on Computer Design (1986): 434-437. [21] J. S. Sargent and P. Banerjee, “A Parallel Row-Based Algorithm for Standard Cell Placement with Integrated Error Control.” Proc. 26th Design Automation Conf. (1989): 590-593. [22] A. Srinivasan, K. Chaudhary, and E. S. Kuh, “RITUAL: A Performance Driven Placement Algorithm for Small Cell ICs.” Proc. Intl. Conf. on Computer-Aided Design, 1991, pp. 48-51. [23] C. Sechen and A. Sangiovanni-Vincentelli, “The Timberwolf Placement and Routing Package.” IEEE J. of Solid-State Circuits, vol SC-20, no 2, pp 510-522, Apr 1985. [24] C. Sechen and K. W. Lee, “An Improved Simulated Annealing Algorithm for Row-based Placement.” Proc. Intl. Conf. on Computer-Aided Design (1987): 478-481. [25] G. Sigl, K. Doll, and F. M. Johannes, “Analytical Placement: A Linear or a Quadratic Objective Function?” Proc. Design Automation Conference, 1991, pp. 427-432. [26] W. Sun and C. Sechen, “Efficient and Effective Placement for Very Large Circuits.” Proc. Intl. Conf. on Computer-Aided Design (1993): 170-177. [27] W. Sun and C. Sechen, “Efficient and Effective Placement for Very Large Circuits.” submitted to IEEE Trans. on CAD. [28] W. Swartz and C. Sechen, “New Algorithms for the Placement and Routing of Macro Cells,” Proc. Int. Conf. on Computer-Aided Design, 1990, pp. 336- 339. [29] W. Swartz, “Automatic Layout of Analog and Digital Mixed Macro/Standard Cell Integrated Circuits.”, Ph. D. Thesis, Yale University, 1993. [30] Chi-Pong Wong and Rolf-Dieter Fiebrich, “Simulated Annealing-Based Circuit Placement Algorithm on the Connection Machine System.” Proc. Intl. Conf. on Computer Design (1987): 78-82. ICCAD94, Pages 145-148 Delay and Area Optimization for Compact Placement by Gate Resizing and Relocation Weitong Chuang AT&T Bell Laboratories, 600 Mountain Ave., Murray Hill, NJ 07974 Ibrahim N. Hajj Dept. of Electrical & Computer Eng., and Coordinated Science Lab., University of Illinois Abstract In this paper, we first present an efficient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit lay-out. Since the gate sizing procedure is embedded within the placement adjustment process, interconnect capacitance information is included in the gate size selection process. As a result, the algorithm is able to obtain superior solutions. REFERENCES [1] P. K. Chan, “Algorithms for library-specific sizing of combinational logic," in Proc. ACM/IEEE Design Automation Conf., pp. 353-356, 1990. [2] W. Chuang, Timing and area optimization for VLSI circuit and layout. PhD thesis, University of Illinois at Urbana-Champaign, 1994. [3] S. H. Yen, D. H. Du, and S. Ghanta, “Efficient algorithms for extracting the K most critical paths in timing analysis," in Proc. ACM/IEEE Design Automation Conf., pp. 649-654, 1989. [4] M. A. Jackson and E. S. Kuh, “Performance-driven placement of cell based IC's," in Proc. ACM/IEEE Design Automation Conf., pp. 370-375, 1989. [5] W. E. Donath, et al, “Timing driven placement using complete path delay," in Proc. ACM/IEEE Design Automation Conf., pp. 84-89, 1990. [6] S. Kim, et al, “APT: An area-performance-testability driven placement algorithm," in Proc. ACM/IEEE Design Automation Conf., pp. 141-146, 1992. [7] S. Lin, M. Marek-Sadowska, and E. S. Kuh, “Delay and area optimization in standard-cell design," in Proc. ACM/IEEE Design Automation Conf., pp. 349-352, 1990. [8] C. Fiduccia and R. Mattheyses, “A linear-time heuristic for improving network partitions," in Proc. ACM/IEEE Design Automation Conf., pp. 175-181, 1982. ICCAD94, Pages 150-155 Edge-Map: Optimal Performance Driven Technology Mapping for Iterative LUT Based FPGA Designs Honghua Yang and D. F. Wong Department of Computer Sciences, University of Texas at Austin, Austin, Texas 78712 Abstract We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection edge has a weight representing the delay of the interconnection. This model is particularly useful when combined with an iterative retechnology mapping process where the actual delays of the placed and routed circuit are fed-back to the technology mapping phase to improve the mapping based on the more realistic delay estimation. Well known technology mappers such as FlowMap and Chortle-d only minimize the number of levels in the technology mapped circuit and hence are not suitable for such an iterative re-technology mapping process. Recently, Mathur and Liu in [ML94] studied the performance driven technology mapping problem using the general delay model and presented an effective heuristic algorithm for the problem. In this paper, we present an efficient technology mapping algorithm that achieves provably optimal delay in the technology mapped circuit using the general delay model. Our algorithm is a non-trivial generalization of FlowMap. A key problem in our algorithm is to compute a K-feasible network cut such that the circuit delay on every cut edge is upper-bounded by a specific value. We implemented our algorithm in a LUT based FPGA technology mapping package called EdgeMap, and tested Edge-Map on a set of benchmark circuits. References [BRSV87] R. K. Brayton, R. Rudell, and A. L. Sangiovanni-Vincentelli. MIS: A Multiple-Level Logic Optimization. IEEE Trans. on CAD, pages 1061-1081, Nov. 1987. [CCD+92] K. C. Chen, J. Cong, Y. Ding, A. B. Kahng, and P. Trajmar. DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Design and Test of Computers, Sept. 1992. [CD92] J. Cong and Y. Ding. An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. In Proc. of the IEEE Int'l Conf. on Computer-Aided Design, pages 48-53, Nov. 1992. [CTC+93] C.-S. Chen, Y.-W. Tsay, T.Hwang C., H.Wu, and Y.-L. Lin. Combining Technology Mapping and Placement for Delay-Optimization in FPGA Designs. In Proc. of the IEEE Int'l Conf. on Computer-Aided Design, Nov. 1993. [FF62] J. R. Ford and D. R. Fulkerson. Flows in Networks. Princeton University Press, 1962. [FRV91] R. J. Francis, J. Rose, and Z. Vranesic. Technology Mapping for Delay Optimization of Lookup TableBased FPGAs. In MCNC Logic Synthesis Workshop, 1991. [ML94] A. Mathur and C. L. Liu. Performance Driven Technology Mapping for Lookup-Table Based FPGAs Using the General Delay Model. In Int'l ACM/SIGDA Workshop on Field Programmable Gate Arrays, Feb. 1994. [MSBSV91] R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli. Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. In Proc. of the IEEE Int'l Conf. on Computer-Aided Design, pages 572-575, 1991. [YW94] H. Yang and D. F. Wong. Area/Pin Constrained Circuit Clustering for Delay Minimization. In Int'l ACM/SIGDA Workshop on Field Programmable Gate Arrays, Feb. 1994. ICCAD94, Pages 156-163 Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki Dept. of Electronics and Communication Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169, Japan Abstract Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no lay-out information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness. References [1] N. B. Bhat and D. D. Hill, “Routable Technology Mapping for FPGA's," Proc. ACM/SIGDA Int.Workshop on FPGAs (FPGA'92), pp. 143-148, Feb. 1992. [2] M. A. Breuer, “Min-Cut Placement," J. Design Automation and Fault Tolerant Computing, Vol. 1, No. 4, pp. 343-362, 1977. [3] S. D. Brown, R. J. Francis, J. Rose and Z. G. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992. [4] C. -S. Chen, Y. -W. Tsay, T. T. Hwang, A. C. H. Wu and Y. -L. Lin, “Combining Technology Mapping and Placement for Delay-Optimization in FPGA Designs," Proc. ICCAD-93, pp. 123-127, 1993. [5] J. Cong, Y. Ding, A. Kahng, P. Trajmar and K. C. Chen, “An Improved Graph-Based FPGA Technology Mapping for Delay Optimization," Proc. 1992 IEEE Int. Conf. on Comput. Design, pp. 154-158, 1992. [6] J. Cong and Y. Ding, “An Optimal Technology Mapping Algorithm of Delay Optimization in Lookup-Table Based FPGA Designs," Proc. ICCAD-92, pp. 48-53, 1992. [7] R. J. Francis, J. Rose and K. Chung, “Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays," Proc. 27th DA Conf., pp. 613-619, 1990. [8] R. J. Francis, J. Rose and Z. Vranesic, “Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs," Proc. 28th DA Conf., pp. 227-233, 1991. [9] R. J. Francis, J. Rose and Z. Vranesic, “Technology Mapping of Lookup Table-Based FPGAs for Performance," Proc. ICCAD-91, pp. 568-571, 1991. [10] H. -C. Hsieh, W. S. Carter, J. Ja, E. Cheung, S. Schreifels, C. Erickson, P. Freidin, L. Tinkey and R. Kanazawa, “Third-Generation Architecture Boosts Speed and Density of Field-Programmable Gate Arrays," Proc. IEEE 1990 Custom Integrated Circuits Conf., pp. 31.2.1-31.2.7, 1990. [11] K. Kawana, H. Keida, M. Sakamoto, K. Shibata and I. Moriyama, “An Efficient Logic Block Interconnect Architecture for User-Reprogrammable Gate Array," Proc. IEEE 1990 Custom Integrated Circuits Conf., pp. 31.3.131.3.4, 1990. [12] S. Kirkpatric, C. D. Gelatt, Jr. and M. P. Vecchi, “Optimization by Simulated Annealing," Science, Vol. 220, No. 4598, pp. 671-680, 1983. [13] U. P. Lauther, “Top Down Hierarchical Global Routing for Channelless Gate Arrays Based on Linear Assignment," Proc. VLSI '87, pp. 109-120, 1987. [14] R. Murgai, Y. Nishizaki, N. Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli, “Logic Synthesis for Programmable Gate Arrays," Proc. 27th DA Conf., pp. 620-625, 1990. [15] R. Murgai, N. Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli, “Improved Logic Synthesis Algorithms for Table Look Up Architectures," Proc. ICCAD-91, pp. 564-567, 1991. [16] R. Murgai, N. Shenoy, R. K. Brayton and A. Sangiovanni-Vincentelli, “Performance Directed Synthesis for Table Look Up Programmable Gate Arrays," Proc. ICCAD-91, pp. 572-575, 1991. [17] M. Schlag, J. Kong and K. Chan, “Routability-Driven Technology Mapping for Look Up Table-Based FPGAs," Proc. 1992 IEEE Int. Conf. on Comput. Design, pp. 86-90, 1992. [18] R. E. Tarjan, Data Structures and Network Algorithms, McGraw Hill, 1983. [19] N. Togawa, M. Sato and T. Ohtsuki, “Simultaneous Placement and Global Routing Algorithm for FPGAs," Proc. ISCAS'94, pp. 483-486, 1994. ICCAD94, Pages 164-168 Universal Logic Gate for FPGA Design Chih-chang Lin, Malgorzata Marek-Sadowska and Duane Gatlin Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 Abstract In this paper the problem of selecting an appropriate programmable cell structure for FPGA architecture design is addressed. The cells studied here can be configured to the desired functionality by applying input permutation, negation, bridging or constant assignment, or output negation. A general methodology to determine logic description of such cells, which are capable of being configured to a given set of functions is described. Experimental results suggest that the new cell behaves as well as the Actel 2 cell in terms of logic power but requires substantially less area and wiring overhead. References [1] C. R. Edwards, “A special class of universal logic gates (ULG) and their evaluation under the Walsh transform," Int. J. Electronics, vol. 44, pp. 49-59, 1978. [2] X. Chen and S. L. Hurst, “The derivation of universal logic modules for n >= 3 by algebraic means," Proc. IEE, part E, Vol. 128, No. 5, pp. 205-211, 1981. [3] H. S. Stone, “Universal logic modules," in Recent Developments in Switching Theory (A. Mukhopadhyay, ed.), ch. VI, pp. 229-254, 1971. [4] O. Coudert, C. Berthet and J. C. Madre, “Verification of sequential machines based on symbolic execution," Proc. of the Workshop on Automatic Verification Methods for Finite State Systems, 1989. [5] K. Karplus, “Using if-then-else DAGs to do technology mapping for field-programmable gate arrays," Report UCSC-CRL-90-43, University of California, Santa Cruz, 1990. [6] K. Karplus, “Amap: a technology mapper for selector-based field-programmable gate arrays," ACM/IEEE Design Automation Conference, pp. 244-247, 1991. [7] R. Murgai et al., “An improved synthesis algorithm for multiplexor-based PGAs," ACM/IEEE Design Automation Conference, pp. 380-386, 1992. ICCAD94, Pages 170-174 Condition Graphs for High-Quality Behavioral Synthesis Hsiao-ping Juan, Viraphol Chaiyakul and Daniel D. Gajski Department of Information and Computer Science, University of California, Irvine, CA 92717-3425 Abstract Identifying mutual exclusiveness between operators during behavioral synthesis is important in order to reduce the required number of control steps or hardware resources. To improve the quality of the synthesis result, we propose a representation, the Condition Graph, and an algorithm for identification of mutually exclusive operators. Previous research efforts have concentrated on identifying mutual exclusiveness by examining language constructs such as IFTHEN-ELSE statements. Thus, their results heavily depend on the description styles. The proposed approach can produce results independent of description styles and identify more mutually exclusive operators than any previous approaches. The Condition Graph and the proposed algorithm can be used in any scheduling or binding algorithms. Experimental results on several benchmarks have shown the efficiency of the proposed representation and algorithm. References [1] R.A. Bergamaschi, “The Effects of False Paths in High-Level Synthesis," Proc. ICCAD 91, 1991. [2] R. Camposano, “Path-Based Scheduling for Synthesis," IEEE Trans. CAD, Vol.10, no.1, Jan. 1991. [3] V. Chaiyakul, D.D. Gajski and L. Ramachandran, “High-level Transformations for Minimizing Syntactic Variances," Proc. 30th DAC, 1993. [4] D.D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992. [5] Benchmarks for the Sixth International Workshop on High-Level Synthesis, 1992. [6] H.P. Juan, V. Chaiyakul, and D.D. Gajski, “Condition Graphs for High-Quality Behavioral Synthesis," Technical Report #94-32, Dept. of ICS, UC Irvine., 1994. [7] T. Kim, J.W.S. Liu, and C.L. Liu, “A Scheduling Algorithm For Conditional Resource Sharing," Proc. ICCAD 91, 1991. [8] K. Wakabayashi and T. Yoshimura, “Global Scheduling Independent of Control Dependencies Based on Condition Vectors," Proc. 29th DAC, 1992. ICCAD94, Pages 175-181 Dynamic Scheduling and Synchronization Synthesis of Concurrent Digital Systems under System-Level Constraints Claudionor N. Coelho Jr, Giovanni De Micheli Center for Integrated Systems, Stanford, CA 94305 coelho@pegasus.stanford.edu Abstract We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synchronizations and constraints. The proposed synthesis technique considers the degrees of freedom introduced by the concurrent models and by the environment in order to satisfy the design constraints. Synthesis is divided in two phases. In the first phase, the original specification is translated into an algebraic system, for which complex control-flow constraints and quantifiers of the design are determined. This algebraic system is then analyzed and the design space of the specification is represented by a finite-state machine, from which a set of Boolean formulas is generated and manipulated in order to obtain a solution. This method contrasts with usual high-level synthesis methods in that it can handle arbitrarily complex control-flow structures, concurrency and synchronization by allowing the scheduling of the operations to change dynamically over time. References [1] J. C. M. Baeten. Process Algebra. Cambridge University Press, 1990. [2] Benchmarks of the 1992 high-level synthesis workshop. [3] D. Filo, D. C. Ku, C. N. Coelho Jr., and G. De Micheli. Interface optimization for concurrent systems under timing constraints. IEEE Transactions on VLSI Systems, 1(3):268–281, September 1993. [4] L. Hafer and A. Parker. Automated synthesis of digital hardware. IEEE Transactions on CAD/ICAS, c-31(2), February 1982. [5] Y.-H. Hung and A. C. Parker. High-level synthesis with pin constraints for multiple-chip designs. In Proceedings of the Design Automation Conference, pages 231–234, June 1992. [6] C.-T. Hwang, J.-H. Lee, and Y-C Hsu. A formal approach to the scheduling problem in high-level synthesis. IEEE Transactions on CAD/ICAS, 10(4):464–475, April 1991. [7] C. N. Coelho Jr., D. Ku, and G. De Micheli. An algebra for modeling concurrent digital circuits. In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1993. [8] C. N. Coelho Jr. and G. De Micheli. Analysis and synthesis of concurrent digital circuits using control-flow expressions. Technical report, Stanford University, 1994. [9] T. Kim, J. W. S. Liu, and C. L. Liu. A scheduling algorithm for conditional resource sharing. In Proceedings of the International Conference on Computer-Aided Design, pages 84–87, Santa Clara, November 1991. [10] R. Lipsett, C. Schaefer, and C. Ussery. VHDL: Hardware Description and Design. Kluwer Academic Publishers, 1989. [11] P. Marwedel. Matching system and component behaviour in mimola synthesis tool. In Proceedings of the European Design Automation Conference, pages 146–156, March 1990. [12] PCI Local Bus Specification Revision 2.0. [13] I. Radivojević and F. Brewer. Symbolic techniques for optimal scheduling. In Proceedings of the Synthesis and Simulation Meeting and International Interchange – SASIMI, pages 145 – 154, Nara, Japan, October 1993. [14] J.-K. Rho, G. D. Hachtel, F. Somenzi, and R. M. Jacoby. Exact and heuristic algorithms for the minimization of incompletely specified state machines. IEEE Transactions on CAD/ICAS, 13(2):167–177, February 1994. [15] K. Wakabayashi and H. Tanaka. Global scheduling independent of control dependencies based on condition vectors. In Proceedings of the Design Automation Conference, pages 112–115, June 1992. ICCAD94, Pages 182-187 Comprehensive Lower Bound Estimation from Behavioral Descriptions Seong Y. Ohm1, Fadi J. Kurdahi1, and Nikil Dutt2 1 Department of Electrical & Computer Engineering Department of Information & Computer Science University of California, Irvine, CA 92717 2 Abstract In this paper, we present a comprehensive technique for lower bound estimation (LBE) of resources from behavioral descriptions. Previous work has focused on LBE techniques that use very simple costmodels which primarily focus on the functional unit resources. Our cost model accounts for storage resources in addition to functional resources. Our timing model uses a finer granularity that permits the modeling of functional unit, register and interconnect delays. We tested our LBE technique for both functional unit and storage requirements on several high-level synthesis benchmarks and observed near-optimal results. References [1] C. Ramachandran, F. J. Kurdahi, D. Gajski, V. Chaiyakul, and A.Wu, “Accurate LayoutArea andDelayModeling for System Level Design,” Proc. ICCAD ’92, Nov. 1992. [2] N. Dutt and C. Ramachandran, “Benchmarks for the 1992 High Level Synthesis Workshop,” Technical Report, ICS Department, UC Irvine, 1992. [3] R. Jain, A. C. Parker, and N. Park, “Predicting System-Level Area and Delay for Pipelined and Non-pipelined Designs,” IEEE Trans. CAD, vol 11. no. 8, pp. 955-965, August 1992. [4] M. Rim and R. Jain, “Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique,” Proc. ICCD ’92, pp. 290-294, Oct. 1992. [5] Y. Hu, A. Ghouse, and B. S. Carlson, “Lower Bounds on the Iteration Time and the Number of Resources for Functional PipelinedData FlowGraphs,”Proc. ICCD’93, pp. 21-24, 1993. [6] A. H. Timmer, M. J. M. Heijligers, and J. A. G. Jess, “Fast System-Level Area-Delay Curve Prediction,” Proc. 1st APCHDL, pp. 198-207, 1993. [7] A. Sharma and R. Jain, “Estimating Architectural Resources and Performance for High-Level Synthesis Applications,” IEEE Trans. VLSI Systems, vol 1. no. 2, pp. 175-190, June 1993. [8] Samit Chaudhuri and Robert A. Walker, “Computing Lower Bounds on Functional Units before Scheduling,” Proc. 7th International Symposium on High-Level Synthesis, pp. 36-41, May 1994. [9] SeongY. Ohm and Chu S. Jhon, “A Branch and Bound Method for the Optimal Scheduling,” Proc. CICC ’92, May 1992. [10] C. H. Gebotys and M. I. Elmasry, “Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis,” Proc. 28th DAC, pp. 2-7, June 1991. [11] Kayhan Küçükçakar, “System-Level Synthesis Techniques with Emphasis on Partitioning andDesign planning,”PhD Thesis, EE-systems Dept., USC. Sept. 91. [12] P. Gupta and A. C. Parker, “SMASH:A Program for Scheduling Memory-Intensive Application-Specific Hardware,” Proc. 7th InternationalWorkshop on HLS, pp. 54-59, May 1994. [13] Seong Y. Ohm, Fadi J. Kurdahi, and Nikil Dutt, “A Unified Method for the Lower Bound Estimation on Resources,” Technical Report, ECE Department, UC Irvine, 1994. [14] A. H. Timmer and J. A. G. Jess, “Execution Interval Analysis under Resource Constraints,” Proc. ICCAD ’93, pp. 454-459, Nov. 1993. [15] M. Rim, R. Jain and R. D. Leone, “Optimal Allocation and Binding in High-Level Synthesis,” Proc. 29th DAC, pp. 120-123, June 1992. [16] P. G. Paulin and J. P. Knight, “Scheduling and Binding Algorithms for High-Level Synthesis,” Proc. 26th DAC, pp. 1-6, June 1989. [17] A. Sharma and R. Jain, “InSyn: Integrated Scheduling for DSP Applications,” Proc. 30th DAC, pp. 349-354, June 1993. ICCAD94, Pages 190-194 Fast and Accurate Timing Simulation with Regionwise Quadratic Models of MOS I-V Characteristics A. Dharchoudhury and S. M. Kang Dept. of Electrical & Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801 K. H. Kim and S. H. Lee CAE Department, Samsung Electronics Co., Seoul, S. Korea Abstract This paper presents a technique called regionwise quadratic (RWQ) modeling that allows highly accurate MOS models, as well as measured I-V data, to be used in fast timing simulation. This technique significantly increases the accuracy of fast timing simulation while maintaining efficiency by permitting analytical solutions of node equations. A fast timing simulator using these RWQ models has been implemented. Several examples of RWQ modeling are provided, and comparisons of simulation results with SPICE3 are shown to demonstrate accuracy and efficiency. Speedups of two to three orders of magnitude for circuits containing up to 2000 transistors are observed. References [1] D. Overhauser, Fast Timing Simulation of MOS VLSI Circuits. PhD thesis, University of Illinois at UrbanaChampaign, 1989. [2] Y.-H. Shih, Y. Leblebici, and S. M. Kang, “ILLIADS: A fast timing and reliability simulator for digital MOS circuits," IEEE Trans. Computer-Aided Design, vol. 12(9), pp. 1387-1402, Sept. 1993. [3] Y. H. Shih and S. M. Kang, “Analytic transient solution of general MOS circuit primitives," IEEE Trans. Computer-Aided Design, vol. 11(6), pp. 719-731, June 1992. [4] Y. H. Chang and A. T. Yang, “Analytic macromodeling and simulation of strongly coupled mixed analog-digital circuits," Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 244-247, Nov. 1992. [5] W. T. Cheng and S. Davidson, “Sequential circuit test generator (STG) benchmark results," Proc. IEEE Int. Symp. on Circuits and Systems, pp. 1938-1941, May 1989. ICCAD94, Pages 195-199 VLSI Timing Simulation with Selective Dynamic Regionization Meng-Lin Yu, Bryan D. Ackland AT&T Bell Laboratories, Holmdel, NJ 07733 Abstract Accurate timing simulations are crucial to the design of MOS VLSI circuits, but can take prohibitively large amounts of time. This paper describes dynamic regionization techniques applied to an event based simulator for MOS timing simulation that have proven to be more efficient and as accurate as the static regionization method. The MOS network is first statically partitioned into groups of strongly coupled nodes called regions. Big regions are then incrementally and dynamically partitioned into and replaced by subregions. Subregions are treated just like normal regions in the event based simulation process. This simulator has been used to verify the timing and functionality of several large VLSI chips. Performance is 3 to 7 times faster than a static regionization method. References [1] Chawla, B., Gummel, H. and Kozak, P. "MOTIS – an MOS timing simulator", IEEE Trans. Circuits and Systems, Vol 22, pp. 901-909, 1975. [2] Fan, S. et al. "MOTIS-C: A New Circuit Simulator for MOS LSI.", ISCAS, pp. 700-703, 1977. [3] Ackland, B. and Weste, N. "Functional Verification in an Interactive Symbolic IC Design Environment", 2nd. Caltech Conf. on VLSI, Jan. 1981, pp. 285-298. [4] Saleh, R., Kleckner, J. and Newton, R. "Iterated Timing Analysis in Splice1", ICCAD'83 Digest, pp. 139-140, Sept. 1983. [5] Chen, C. and Subramaniam, P. "The Second Generation MOTIS Timing Simulator -- An Efficient and Accurate Approach for General MOS Circuits", ISCAS, pp. 538-542, 1984. [6] Lelarasmee, E. and Sangiovanni-Vincentelli, A. "RELAX: A New Circuit Simulator for Large Scale Mos Integrated Circuits", Proc. 19th DAC, pp. 682-690, 1982. [7] Vidigal, L., Nassif, S. and Director, S., "CINNAMON: Coupled Integration and Nodal Analysis of MOS Networks", Proc. 23rd DAC, pp. 179-185, 1986. [8] Odyrna, P. and Nassif, S. "The ADEPT Timing Simulator Algorithm", VLSI SYSTEMS DESIGN, pp. 24-34, March 1986. Bauer R. et al., "XPSim: A MOS VLSI Simulator", ICCAD'88, pp. 66-69, Aug. 1988. [9] Carelli, J. "An Improved Transistor Model for EMU and an Associated Parameter Extraction Tool: EMUFIT", 52156-851213-01TM. [10] Ackland. B. and Clark, R. "Event-EMU: An Event Driven Timing Simulator for MOS VLSI Circuits", ICCAD'89 Proceedings, pp. 80-83, Nov. 1989. ICCAD94, Pages 200-203 A New Efficient Approach to Statistical Delay Modeling of CMOS Digital Combinational Circuits Syed A. Aftab Motorola Strategic Systems Tech., 2100 E. Elliot Rd, MD EL612, Tempe, AZ 85284 M. A. Styblinski Dept.of Electrical Engineering, Texas A&M University, College Station, TX 77843 Abstract This paper presents one of the first attempts to statistically characterize signal delays of basic CMOS digital combinational circuits using the transistor level approach. Hybrid analytical/iterative delay expressions in terms of the transistor geometries and technological process variations are created for basic building blocks. Local delays of blocks along specific signal paths are combined together for the analysis of complex combinational VLSI circuits. The speed of analysis is increased by 2 to 4 orders of magnitude relative to SPICE, with about 5-10% accuracy. The proposed approach shows good accuracy in modeling the influence of the “noise" parameters on circuit delay relative to direct SPICE-based Monte Carlo analysis. Examples of statistical delay characterization are shown. The important impact of the proposed approach is that statistical evaluation and optimization of delays in much larger VLSI circuits will become possible. References [1] R.E. Bryant, “MOSSIM: A switch-level simulator for MOS LSI". In Proc. 18th Design Automation Conf., 1981. pp. 786-790. [2] A.C. Deng and Y.C. Shiau, “Generic linear RC delay modeling for digital CMOS circuits". IEEE Trans. on CAD, 9(4):367-376, November 1990. [3] C. J. Terman, “RSIM - A logic-level timing simulator". In IEEE Proc., New York, Nov., 1983. Conf. on Computer Design. [4] K.M. Opalska, M.A. Styblinski, X. Sun and L.J. Opalski, “An efficient symbolic approach to time delay optimization of CMOS circuits". In IEEE Proc, Singapore, May 1991. ISCAS'91. [5] J.F.Tuan, Mixed-mode Analog/Digital Simulator of MOS Circuits. PhD thesis, Texas A&M University, December 1990. [6] M. Shoji, CMOS Digital Circuit Technology. Prentice Hall, Englewood Cliffs, New Jersey, 1988. [7] T.N. Trick, V.B. Rao, D.V. Overhauser and I.N. Haji, Switch-Level Timing Simulation of MOS VLSI Circuits. Kluwer Academic Publishers, Boston-Dordrecht-London, 1989. [8] T. Sakurai and A.R. Newton, “Delay analysis of series-connected MOSFET circuits". IEEE Journal of SolidState Circuits, 26(2):122-131, February 1991. [9] L. J. Opalski, K. Opalski and M. A. Styblinski, “Symbolic modeling of VLSI CMOS circuits for statistical optimization". Technical Report LIDS # 92-7, Texas A&M University, September 1992. [10] R. M. Biernacki and M. A. Styblinski, “Efficient performance function interpolation scheme and its application to statistical circuit design". International Journal of Circuit Theory and Applications, 19:403-422, 1991. [11] J. Chen and M. A. Styblinski, “A systematic approach to statistical modeling and it's applications to CMOS circuits". In IEEE Proc., Chicago, Il., May, 1993. ISCAS'93. [12] S. A. Aftab and M. A. Styblinski, “A new analytical/iterative approach to statistical delay characterization of CMOS digital combinational circuits". Int'l Journal of Circuit Theory and Applications. Accepted for publication. [13] K.M. Opalska, “Symbolic delay formula generation program for CMOS circuits - User's guide". LIDS Technical Report 10-91, Dept. of Elect. Eng., Texas A&M University, May 1991. ICCAD94, Pages 206-212 Simultaneous Driver and Wire Sizing for Performance and Power Optimization Jason Cong and Cheng-Kok Koh Department of Computer Science, University of California, Los Angeles, CA 90024 Abstract In this paper,we study the simultaneous driver andwire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipation minimization. We present general formulations of the SDWS problem under these two objectives based on the distributed Elmore delay model with consideration of both capacitive power dissipation and short-circuit power dissipation. We show several interesting properties of the optimal SDWS solutions under the two objectives, including an important result (Theorem 3) which reveals the relationship between driver sizing and optimal wire sizing. These results lead to polynomial time algorithms for computing the lower and upper bounds of optimal SDWS solutions under the two objectives, and efficient algorithms for computing optimal SDWS solutions under the two objectives. We have implemented these algorithms and compared them with existing design methods for driver sizing only or independent driver and wire sizing. Accurate SPICE simulation shows that our methods reduce the delay by up to 11%–47% and power dissipation by 26%–63% compared with existing design methods. References [1] C. J. Alpert, T. C. Hu, J. H. Huang, andA. B. Kahng, “A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-Driven Routing”, Proc. IEEE Int’l Symp. on Circuits and Systems, May 1993, pp. 1869-1872. [2] H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, 1990. [3] K. D. Boese, A. B. Kahng, and G. Robins, “High-Performance Routing Trees With Identified Critical Sinks”, Proc. ACM/IEEE Design Automation Conf., 1993, pp. 182-187. [4] J. B. Burr, J. R. Burnham, and A. M. Peterson, “System-wide Energy Optimization in theMCMEnvironment”, Proc. IEEE MCM Conf., 1991, pp. 66-83. [5] J. P. Cohoon and L. J. Randall, “Critical Net Routing”, Proc. IEEE Int’l. Conf. on Computer Design, 1991, pp. 174-177. [6] J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong, “Provably Good Performance-Driven Global Routing”, IEEE Trans. on CAD, 11(6), June 1992, pp. 739-752. [7] J. Cong, C.-K. Koh, and K. S. Leung, “Wiresizing with Driver Sizing for Performance and Power Optimization”, Proc. 1994 Int’lWorkshop on Lower Power Design, 1994, pp. 81–86. [8] J. Cong andC.-K. Koh, “SimultaneousDriver andWire Sizing for Performance and Power Optimization”, UCLA Computer Science Department Tech. Report CSD-940020, Los Angeles, CA 90024, May 1994. [9] J. Cong, K. S. Leung, and D. Zhou, “Performance-Driven Interconnect Design Based onDistributed RC DelayModel”,Proc. ACM/IEEE Design Automation Conf., 1993, pp. 606-611. [10] J. Cong and K. S. Leung, “Optimal Wiresizing Under the Distributed Elmore Delay Model”, Proc. IEEE Int’l. Conf. on Computer-Aided Design, 1993, pp. 634-639 (full version accepted for publication in IEEE Trans. on CAD and available as UCLA Computer Science Department Tech. Report CSD-930012, Los Angeles, CA 90024, April 1993). [11] W. C. Elmore, “The Transient Response ofDamped LinearNetwork with Particular Regard toWideband Amplifier”, J. Applied Physics, 19(1948), pp. 55-63. [12] X. Hong, T. Xue, E. S. Kuh, C. K. Cheng, and J. Huang, “Performance-Driven Steiner Tree Algorithms For Global Routing”, Proc. ACM/IEEE Design Automation Conf., 1993, pp. 177-181. [13] MCNC Designers’ Manual, MCNC. [14] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: a Systems Perspective – 2nd ed, Addison-Wesley, 1993. ICCAD94, Pages 213-218 Low-Cost Single-Layer Clock Trees With Exact Zero Elmore Delay Skew Andrew B. Kahng and Chung-Wen Albert Tsao UCLA Computer Science Dept., Los Angeles, CA 90024-1596 USA Abstract We give the first single-layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear-Planar-DME method [11] guarantees a planar solution under the linear delay model. In this paper, we use a Linear-Planar-DME variant connection topology to construct a low-cost zero skew tree (ZST) according to the Elmore delay model. While a linear-delay ZST is trivially converted to an Elmore-delay ZST by “detouring" wires, the key idea is to defer this detouring as much as possible to reduce tree cost. Costs of our planar ZST solutions are comparable to those of the best previous non-planar ZST solutions, and substantially improve over previous planar clock routing methods. References [1] T. Asano, T, Asano, L. Guibas, J. Hershberger, and H. Imai, “Visibility-polygon search and Euclidean shortest paths", Proc. IEEE Symp. on Foundations of Computer Science, 1985, pp. 155-164. [2] K. D. Boese and A. B. Kahng, “Zero-Skew Clock Routing Trees With Minimum Wirelength," Proc. IEEE Intl. Conf. on ASIC, 1992, pp. 1.1.1 - 1.1.5. [3] T.-H. Chao, Y.-C. Hsu and J.-M. Ho, “Zero Skew Clock Net Routing," Proc. ACM/IEEE Design Automation Conf., 1992, pp. 518-523. [4] T.-H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, “Zero Skew Clock Routing With Minimum Wirelength", IEEE Trans. on Circuits and Systems 39(11) (1992), pp. 799-814. [5] J. Cong, A. B. Kahng and G. Robins, “Matching-Based Methods for High-Performance Clock Routing", IEEE Trans. on CAD 12(8), August 1993, pp. 1157-1169. [6] W. M. Dai, R. Kong, J. Jue, and M. Sato, “Rubber band routing and dynamic data representation", Proc. IEEE Intl. Conf. on Computer-Aided Design, 1990, pp. 52-55. [7] M. Edahiro, “Minimum Skew and Minimum Path Length Routing in VLSI Layout Design", NEC Research and Development 32(4), October 1991, pp. 569-575. [8] M. Edahiro, “Clustering-Based Optimization Algorithm in Zero-Skew Routings", Proc. ACM/IEEE Design Automation Conf., June 1993, pp. 612-616. [9] W. C. Elmore, “The Transient Response of Damped Linear Networks With Particular Regard to Wide-Band Amplifiers," J. Applied Physics 19(1) (1948), pp. 55-63. [10] M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock Routing for High Performance ICs," Proc. ACM/IEEE Design Automation Conf., 1990, pp. 573-579. [11] A. B. Kahng and C.-W. A. Tsao. “Planar-DME: Improved Planar Zero-Skew Clock Routing With Minimum Path-length Delay," Proc. ACM/IEEE European Design Automation Conf., September 1994. [12] A. B. Kahng, J. Cong, and G. Robins, “High-Performance Clock Routing Based on Recursive Geometric Matching," Proc. ACM/IEEE Design Automation Conf., 1991, pp. 322-327. [13] W. Khan, X. He, L. Bangaru and N. Sherwani, “Combat: Zero Skew Minimal Delay Planar Clock Routing for High Performance Systems", Western Michigan Univ. Computer Science Technical Report TR/93-08, April 15, 1993 [14] R. S. Tsay, “Exact Zero Skew", Proc. IEEE Intl. Conference on Computer-Aided Design, 1991, pp. 336-339. [15] E. Welzl, “Constructing the Visibility Graph for n Line Segments in O(n2) Time", Information Processing Letters 20 (1985), pp. 167-171. [16] Q. Zhu and W. W.-M. Dai, “Perfect-Balance Planar Clock Routing With Minimal Path-Length", Proc. IEEE Intl. Conf. on Computer-Aided Design, Nov. 1992, pp. 473-476. ICCAD94, Pages 219-223 Clock Period Constrained Minimal Buffer Insertion in Clock Trees Gustavo E. Téllez and Majid Sarrafzadeh Department of Electrical Engineering,and Computer Science, Northwestern University, Evanston, IL 60208 email: gus@cad2.eecs.nwu.edu Abstract In this paper we investigate the problem of computing a lower bound on the number of buffers required when given a maximum clock frequency and a predefined clock tree. Using generalized properties of published CMOS timing models, we formulate a novel non-linear and a simplified linear buffer insertion problem. We solve the later optimally with an O(n) algorithm. The basic formulation and algorithm are extended to include a skew upper bound constraint. Using these algorithms we propose further algorithmic extensions that allow area and phase delay tradeoffs. Our results are verified using SPICE3e2 simulations with MCNC MOSIS 2.0µ models and parameters. Experiments show our buffer insertion algorithms can be used effectively for highspeed clock designs. References [Bak90] H. B. Bakoglu. “Circuits, Interconnections, and Packaging for VLSI", pages 81-112. Addison-Wesley Publishing Co., 1990. [CC93] N.-C. Chou and C.-K. Cheng. “Wire Length and Delay Minimization in General Clock Net Routing ". In International Conference on Computer-Aided Design, pages 552-555. IEEE, November 1993. [Fri93] E. G. Friedman. “Clock Distribution Design in VLSI Circuits - an Overview". In International Symposium on Circuits and Systems, pages 1475-1478, May 1993. [PMOP93] S. Pullela, N. Menezes, J. Omar, and L. T. Pillage. “Skew and Delay Optimization for Reliable Buffered Clock Trees". In International Conference on Computer-Aided Design, pages 556-562. ACM/IEEE, November 1993. [SK92] Y. H. Shih and S. M. Kang. “Analytic Transient Solution of General MOS Circuit Primitives". IEEE Transactions on Computer Aided Design, 11(6):719-731, 1992. [SW92] N. A. Sherwani and B. Wu. “Effective Buffer Insertion of Clock Tree for High Speed VLSI Circuits". Microelectronics Journal, 23:291-300, July 1992. ICCAD94, Pages 226-233 Effcient Implementation of Retiming Narendra Shenoy, Richard Rudell Synopsys Inc., 700 E. Middlefield Road, Mountain View CA 94043 Abstract Retiming is a technique for optimizing sequential circuits. It repositions the registers in a circuit leaving the combinational cells untouched. The objective of retiming is to find a circuit with the minimum number of registers for a specified clock period. More than ten years have elapsed since Leiserson and Saxe first presented a theoretical formulation to solve this problem for single-clock edge-triggered sequential circuits. Their proposed algorithms have polynomial complexity; however naive implementations of these algorithms exhibit O(n3) time complexity and O(n2) space complexity when applied to digital circuits with n combinational cells. This renders retiming ineffective for circuits with more than 500 combinational cells. This paper addresses the implementation issues required to exploit the sparsity of circuit graphs to allow min-period retiming and constrained min-area retiming to be applied to circuits with as many as 10,000 combinational cells. We believe this is the first paper to address these issues and the first to report retiming results for large circuits. References [1] A. Goldberg, E. Tardos, and R. E. Tarjan. Network flow Algorithms. Technical report, Department of Computer Science, 1989. [2] A. Ishii, C. E. Leiserson, and M. C. Papaefthymiou. Optimizing Two-Phase Level-Clocked Circuitry. In Advanced Research in VLSI, 1992. [3] E. L. Lawler. Combinatorial Optimization: networks and Matroids. Holt, Rinehart and Winston, 1976. [4] C. E. Leiserson and J. B. Saxe. Optimizing Synchronous Systems. In Journal of VLSI and Computer Systems, pages 41-67, 1983. [5] C. E. Leiserson and J. B. Saxe. Retiming Synchronous Circuitry. In Algorithmica, 1991. 6(1). [6] B. Lockyear and C. Ebeling. Optimal Retiming of Multi-Phase Level-Clocked Circuits. In Advanced Research in VLSI, 1992. [7] A. Munzner and G. Hemme. Converting Combinational Circuits into Pipelined Data Path. In Proceedings of the International Conference on Computer-Aided Design, 1991. [8] M. C. Papaefthymiou and K. H. Randall. TIM: Timing Package for Two-phase Level-clocked Circuitry. In Proceedings of the Design Automation Conference. IEEE/ACM, 1993. [9] J. B. Saxe. Decomposable Searching Problems and Circuit Optimizations by retiming: Two Studies in General Transfromations of Computational Structures. PhD thesis, Carnegie-Mellon University, 1985. [10] T. G. Szymanski. Computing Optimal Clock Schedules. In Proceedings of the Design Automation Conference, 1992. ICCAD94, Pages 234-241 Retiming With Non-Zero Clock Skew, Variable Register, and Interconnect Delay Tolga Soyata and Eby G. Friedman Department of Electrical Engineering, University of Rochester, Rochester, NY 14627 Abstract A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delay. These delay components are incorporated into retiming by assigning Register Electrical Characteristics (RECs) to each edge in the graph representation of the synchronous circuit. A matrix (called the Sequential Adjacency Matrix or SAM) is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in standard retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. The algorithm is demonstrated on modified MCNC benchmark circuits and both increased clock frequencies and elimination of all race conditions are observed References [1] C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry," Algorithmica, Vol. 6, pp. 5-35, January 1991. [2] A. T. Ishii, C. E. Leiserson, and M. C. Papaeflhymiou, "Optimizing Two-Phase, Level-Clocked Circuitry," Proceedings of the 1992 Brown/MIT Conference on Advanced Research in VLSI and Parallel Systems, pp. 245--264, March 1992. [3] G. De Micheli, "Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization." IEEE Transactions on Computer-Aided Design, Vol. CAD-10, No. 1, pp. 63--73, Jan 1991. [4] J. P. Fishburn, "Clock Skew Optimization," IEEE Transactions on Computers, Vol. 39, No. 7, pp. 945-951, July 1990. [5] E. G. Friedman. "The Application of Localized Clock Distribution Design to Improving the Performance of Retimed Sequential Circuits," Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, pp. 1217, December 1992. [6] T. Soyata, E. G. Friedman, and J.H. Mulligan, Jr., "Integration of Clock Skew and Register Delays into a Retiming Algorithm," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1483--1486, May 1993. [7] B. Lockyear and C. Ebeling, "The Practical Application of Retiming to the Design of High-Performance Systems," Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 288-295, November 1993. [8] T. Soyata and E. G. Friedman. "Synchronous Performance and Reliability Improvement in Pipelined ASICs," Proceedings of the ASIC Conference, September 1994. [9] S. Simon. E. Bernard, M. Sauer. and J. A. Nossek, "A New Retiming Algorithm for Circuit Design," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 4.35-4.38, May/June 1994. [10] L. Chao and E. H. She, "Retiming and Clock Skew for Synchronous Systems," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.283-1.286, May/June 1994. [11] E. G. Friedman and J. H. Mulligan, "Clock Frequency and Latency in Synchronous Digital Systems," IEEE Transactions on Signal Processing, Vol. 39, No. 4, pp. 930-934, April 1991. [12] E. G. Friedman, "Clock Distribution Design in VLSI Circuits - an Overview," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1475-1478, May 1993. [13] K. A. Sakallah, T. N. Mudge, T. M. Burks, and E. S. Davidson, "Synchronization of Pipelines," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-12, No. 8, pp. 1132-1146 August 1993. [14] S. Malik, E. M. Sentovich, R. K. Brayton, and A. SangiovanniVincentelli, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinatorial Techniques." IEEE Transactions on Computer-Aided Design, Vol. CAD10, No. 1, pp. 74-84, January 1991. [15] E. L. Lawler, Combinatorial Optimization: Networks and Matroids. Holt, Rinehart and Winston, NewYork, 1976. [16] R. Lisanke, "Logic Synthesis and Optimization Benchmarks User Guide: Version 2.0," Tech. Rep., Microelectronics Center of North Carolina, December 1988. [17] S. Yang, ""Logic Synthesis and Optimization Benchmarks User Guide: Version 3.0," Tech. Rep., Microelectronics Center of North Carolina, January 1991. ICCAD94, Pages 242-245 Optimal Latch Mapping and Retiming within a Tree Joel Grodstein, Eric Lehman, Heather Harkness, Herve Touati, and Bill Grundmann Digital Equipment Corporation, Hudson, MA Abstract We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined circuits. If the circuit to be mapped has a tree structure, our algorithm generates an optimal solution compatible with that structure. The algorithm takes into account gate delays and capacitive loads as latches are moved across the logic. It also supports latches with embedded logic: i.e., cells that combine a D latch with a combinational gate at little extra cost in latch delay. References 1. Touati, H., "Performance-Oriented Tech. Mapping," PhD Thesis, UCB/ERL M90/109, U.C. Berkeley 1990. 2. K.Chaudhary et. al., "A Near-Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints," DAC-92. 3. E. Detjens et. al., "Technology Mapping in MIS," 1987 ICCAD, pp. 116-119. 4. R. Rudell, "Logic Synthesis for VLSI Design," Ph.D. thesis, UCB/ERL M89/49, U.C. Berkeley, 1989. 5. Leiserson and Saxe, "Retiming Synchronous Circuitry," Algorithmica, 6(1) 1991. 6. Ishii,et al, "Optimizing Two-Phase, Level-clocked Circuitry," in Adv. Research in VLSI: Proc 1992 Brown/MIT Conference. 7. Locklear,B, et al, "The Practical Application of Retiming to High-Perf. Systems," ICCAD 1993. 8. Sentovich et al "SIS: A System for Sequential Circuit Synthesis," ICCD-92, pp.328. 9. C. Moon et al, "Technology Mapping for Sequential Logic Synthesis," Proc. Intl. Workshop on Logic Synthesis, North Carolina, 1989. ICCAD94, Pages 248-251 Simulation of Digital Circuits in the Presence of Uncertainty Mark Linderman and Miriam Leeser School of Electrical Engineering, Cornell University Ithaca, NY 14853 Abstract Current extended value set dynamic timing analyzers are not sophisticated enough to detect the subtle timing relationships upon which timing-critical systems depend, and exhaustive simulation achieves very accurate results but at tremendous computational cost. MTV is a simulator that strikes a balance between accuracy and efficiency. MTV is more accurate than other extended value set simulators because it respects the ordering of events. It is more efficient than exhaustive simulators because it efficiently simulates overlapping events and requires only a single waveform to represent a signal. Features of MTV include: elimination of common ambiguity, symbolic delays, correlated delays, and sophisticated algorithms to detect ordered events. This paper concludes with simulation results from the ISCAS85 benchmark suite. References [1] Srinivas Devadas, Kurt Keutzer, Sharad Malik, and Albert Wang. Event suppression: Improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. on CAD, June 1994. [2] Dimitris Doukas and Andrea S. LaPaugh. CLOVER: A timing constraints verification system. In Tau, 1990. [3] Michael Franz, T. C.Whang, andWallace Chou. A 240 MHz phase-locked circuit implemented as a standard macro on CMOS SOG gate arrays. In CICC, pages 25.1.1--25.1.4, 1992. [4] Nagisa Ishiura, Yutaka Deguchi, and Shuzo Yajima. Coded time-symbolic simulation using shared binary decision diagrams. In DAC, pages 130--135, 1990. [5] Nagisa Ishiura, Nizuki Takahashi, and Shuzo Yajima. Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits. In DAC, pages 497--502, 1989. [6] Mark H. Linderman. Simulation of Digital circuits in the presence of uncertainty. PhD thesis, Cornell University, 1994. [7] Alan R. Martello, Steven P. Levitan, and Donald M. Chiarulli. Timing verification using HDTV. In DAC, pages 118--123, 1990. [8] Thomas M. McWilliams. Verification of timing constraints on large digital systems. In DAC, pages 139-147, 1980. [9] Kostas Siomalas, Philippe Piche, and Giovanni Mancini. Correlated delays and hazard detection in digital simulation. Bell-Northern Research internal report, 1988. ICCAD94, Pages 252-257 Fast Transient Power and Noise Estimation for VLSI Circuits Wolfgang T. Eisenmann Motorola GmbH Munich, ASIC Design Automation, D-81829 Munich, Germany Helmut E. Graeb Technical University of Munich, Institute of Electronic Design Automation, D-80290 Munich, Germany Abstract Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliability constraints emerging in VLSI circuits. In this paper a new technique to accurately estimate the transient behavior of large CMOS cell-based circuits in a reasonable amount of time is presented. Gate-level simulation and a consistent modeling methodology are employed to compute the time-domain waveforms for signal voltages, supply currents, power consumption and ∆I noise on power lines. This can be done for circuit blocks and complete designs by our new tool POWTIM, which adds SPICE-like capabilities to digital design systems. References [1] A. M. Martinez. Quick Estimation of Transient Currents in CMOS Integrated Circuits. IEEE Journal of SolidState Circuits, 24(2):520-431, Apr 1989. [2] S. Chowdhury and J. S. Barkatullah. Estimation of Maximum Currents in MOS IC Logic Circuits. IEEE Trans. on CAD, 9(6):642-654, June 1990. [3] A. Nabavi-Lishi and N. Rumin. Delay and Bus Current Evaluation in CMOS Logic Circuits. In IEEE ICCAD, pp. 198-203, Nov 1992. [4] A. Deng, Y. Shiau, and K. Loh. Time Domain Current Waveform Simulation of CMOS Circuits. In IEEE ICCAD, pp. 208-211, Nov 1988. [5] F. Rouatbi and B. Haroun. Power Estimation Tool for Sub-Micron CMOS VLSI Circuits. In IEEE ICCAD, pp. 204-209, Nov 1992. [6] J. H. Wang, J. T. Fan, and W. S. Feng. A Novel Current Model For CMOS Gates. In ISCAS, pp. 2132-2135, May 1992. [7] F. Najm, R. Burch, and P. Yang. Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits. IEEE Trans. on CAD, 9(4):439-450, Apr 1990. [8] C. Nakata and J. Brook. H4C Series CMOS Gate Arrays Design Reference Guide. Motorola, 1993. [9] N. Hedenstierna and K. O. Jeppson. CMOS Circuit Speed and Buffer Optimization. IEEE Trans. on CAD, 6(2):270-281, Mar 1987. [10] T. Sakurai. CMOS Inverter Delay and Other Formulas Using Alpha-Power Law MOS Model. In IEEE ICCAD, pp. 74-77, Nov 1988. [11] W. Eisenmann and M. Kohl. Power Calculation for CMOS Gate Arrays. In IEEE Int. ASIC Conf., pp. P12-1.1P12-1.5, Sept 1991. [12] W. J. Hsu, B. J. Sheu, S. M. Gowda, and C. G. Hwang. Advanced Integrated-Circuit Reliability Simulation Including Dynamic Stress Effects. IEEE Journal of Solid-State Circuits, 27(3):247-257, Mar 1992. ICCAD94, Pages 258-261 The Inversion Algorithm for Digital Simulation Peter M. Maurer Dept. of Computer Sci&Eng, University of South Florida, Tampa, FL 33620 Abstract The Inversion Algorithm is an event-driven algorithm, whose performance rivals or exceeds that of Levelized Compiled code simulation, even at activity rates of 50% or more. The Inversion Algorithm has several unique features, the most remarkable of which is the size of the run-time code. The basic Algorithm can be implemented using no more than a page of run-time code, although in practice it is more efficient to provide several different variations of the basic algorithm. The run-time code is independent of the circuit under test, so the algorithm can be implemented either as a compiled code or an interpreted simulator with little variation in performance. Because of the small size of the run-time code, the runtime portions of the Inversion Algorithm can be implemented in assembly language for peak efficiency, and still be retargeted for new platforms with little effort. References. 1. M. Lewis, “A Hierarchical Compiled Code Event-Driven Logic Simulator,” IEEE Transactions on Computer Aided Design, Vol 10, No. 6, pp.726-737, June 1991. 2. P. M. Maurer, “The Shadow Algorithm: A Scheduling Technique for Both Compiled and Interpreted Simulation,” IEEE Transactions on Computer Aided Design, in press. 3. Z. Wang and P. M. Maurer, “LECSIM : A Levelized Event Driven Compiled Logic Simulator,” Proceedings of the 27th Design Automation Conference, 1990, pp. 491-496. 4. D. Schuler “Simulation of NAND Logic,” Proceedings of COMPCON 72, Sept. 1972, pp. 243-245. 5. F. Brglez, P. Pownall, R. Hum, “Accelerated ATPG and Fault Grading via Testability Analysis,” Proceedings of the International Conference on Circuits and Systems, 1985, pp. 695-698. ICCAD94, Pages 264-267 Unified Complete MOSFET Model for Analysis of Digital and Analog Circuits M. Miura-Mattausch, U. Feldmann, A. Rahm, M. Bollu, D. Savignac1 Corporate Research and Development, Siemens AG, Munich 1 Semiconductor Division, Siemens AG, Munich Abstract In this paper, we describe the complete MOSFET model developed for circuit simulation. The model describes all transistor characteristics as functions of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. The unified treatment of our model allows all transistor characteristics to be calculated without any nonphysical fitting parameters. Additionally the calculation time is drastically reduced in comparison with a conventional piece-wise model. References [1] Y. P. Tsividis, "Operation and modeling of the MOS transistor," Chap. 7, McGraw-Hill, 1987. [2] H. J. Park, P. K. Ko and C. Hu, "A charge sheet capacitance model of short channel MOSFET's for SPICE," IEEE Trans. CAD, 10, pp376-389, March 1991. [3] H. C. Pao and C. T. Sah, "Effects of diffusion current on characteristics of metal-oxide (insulator) semiconductor transistors," Solid-State Electron., 9, pp927-937, Oct. 1966. [4] J. R. Brews, "A charge-sheet model of the MOSFET," Solid-State Electron., 21, pp345-355, Feb. 1978. [5] M. Miura-Mattausch, A. Rahm, M. Bollu, and U. Feldmann,"A novel consistent MOSFET model for CAD application with reduced calculation time," Proc. ISCAS, pp1.391-1.394 1994. [6] M. Miura-Mattausch and H. Jacobs, "Analytical model for circuit simulation with quarter micron metal oxide semiconductor field effect transistors: sub-threshold characteristics," Jap. J. Appl. Phys., 29, ppL2279-L2282, Dec. 1990. [7] K. K. Thorner, "Relation of drift velocity to low-field mobility and high-field saturation velocity," J. App. Phys., 5, pp2127-2136, April 1980. [8] C. Turchetti and G. Masetti, "A CAD-oriented analytical MOSFET model for high-accuracy applications", IEEE Trans. CAD, 3, pp117-122, April 1984. [9] S. Yu, A. F. Franz, and T. G. Mihran, "A physical parametric transistor model for CMOS circuit simulation", IEEE Trans. CAD, 7, pp1038-1052, Oct. 1988. [10] MEDUSA User's Guide, RWTH Aachen, Germany 1989. ICCAD94, Pages 268-271 A Precorrected-FFT method for Capacitance Extraction of Complicated 3-D Structures J. R. Phillips, J. White Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139. Abstract In this paper we present a new approach to three-dimensional capacitance extraction based on a precorrected FFT scheme. The approach is compared to the now commonly used multipoleaccelerated algorithms for a variety of structures, and the new method is shown to have substantial performance and memory advantages. References [1] R. F. Harrington, Field Computation by Moment Methods. New York: MacMillan, 1968. [2] K. Nabors, S. Kim, and J. White, “Fast capacitance extraction of general three-dimensional structure," IEEE Trans. on Microwave Theory and Techniques, vol. 40, pp. 1496-1507, July 1992. [3] L. Greengard, The Rapid Evaluation of Potential Fields in Particle Systems. Cambridge, Massachusetts: M.I.T. Press, 1988. [4] A. E. Ruehli and P. A. Brennan, “Efficient capacitance calculations for three-dimensional multiconductor systems," IEEE Transactions on Microwave Theory and Techniques, vol. 21, pp. 76-82, February 1973. [5] Y. Saad and M. H. Schultz, “GMRES: A generalized minimal residual algorithm for solving non-symmetric linear systems," SIAM Journal on Scientific and Statistical Computing, vol. 7, pp. 856-869, July 1986. [6] L. Berman, “Grid-multipole calculations," Tech. Rep. RC 19068(83210), IBM Research Report, 1993. [7] A. Brandt, “Multilevel computations of integral transforms and particle interactions with oscillatory kernals," Computer Physics Communications, no. 65, pp. 24-38, 1991. ICCAD94, Pages 272-277 Measurement and Modeling of MOS Transistor Current Mismatch in Analog IC’s Eric Felt, Amit Narayan, Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 Abstract This paper presents a new methodology for measuring MOS transistor currentmismatch and a new transistor currentmismatch model. The new methodology is based on extracting the mismatch information from a fully functional circuit rather than on probing individual devices; this extraction leads to more efficient and more accurate mismatch measurement. The new model characterizes the total mismatch as a sum of two components, one systematic and the other random. For our process, we attribute nearly half of the mismatch to the systematic component, which we model as a linear gradient across the die. Furthermore, we present a new model for the random component of the mismatch which is 60% more accurate, on average, than existing models. References [1] M. J. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching Properties ofMOS Transistors”, IEEE J. of Solid-State Circuits, Vol. 24, No. 5, pp. 1433-1440,Oct. 1989. [2] R.W.Gregor, “On the RelationshipBetweenTopography and TransistorMatching in anAnalogCMOS Technology”,IEEE Transactions on Electron Devices, Vol. 39, No. 2, pp. 275-282, Feb. 1992. [3] Jyn-Bang Shyu, G. C. Temes and Francois Krummenacher, “Random Error Effects in Matched MOS Capacitors and Current Sources,” IEEE J. of Solid-State Circuits, Vol. SC-19, No. 6, pp. 948-955, Dec. 1984. [4] K. R. Lakshmikumar, R. A. Hadaway and M. A. Copeland, “Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design”, IEEE J. of Solid-State Circuits, Vol. SC-21, No. 6, pp. 10571066,Dec. 1986. [5] Christopher Michael and Mohammed Ismail, “Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits”, IEEE J. of Solid-State Circuits, Vol. 27, No. 2, pp. 154-166, Feb. 1992. [6] E. Liu, A. Sangiovanni-Vincentelli, G. Gielen and P. Gray, “A Behavioral Representation for Nyquist RateA/D Converters”, Proc. IEEE ICCAD, pp. 386-389, Nov. 1991. [7] H. Chang, E. Liu, R. Neff, E. Felt, E. Malavasi, E. Charbon, A. Sangiovanni-Vincentelli and P. R. Gray", “TopDown, Constraint-Driven Methodology Based Generation of n-bit Interpolative Current Source D/A Converters”, Proc. IEEE CICC, pp. 369-372, May 1994. [8] G. Troster and P. Tomaszewski, “Mismatch Simulation for Layout Sensitive Parameters of IC Components and Devices”, IEEE Transactions on Computer-Aided Design, Vol. 8, No. 2, pp. 101-107, Feb. 1989. ICCAD94, Pages 280-283 Skew Sensitivity Minimization of Buffered Clock Tree Jae Chung and Chung-Kuan Cheng Department of Computer Science and Engineering, University of California at San Diego, La Jolla, CA 92093-0114 Abstract Given a topology of clock tree and a library of buffers, we propose an efficient skew sensitivity minimization algorithm using dynamic programming approach. Our algorithm finds the optimum buffer sizes, its insertion levels in the clock tree, and optimum wire widths to minimize the skew sensitivity under manufacturing variations. Careful fine tuning by shifting buffer locations at the last stage preserves the minimum skew sensitivity property and reduce the interconnect length. For a given clock tree of n points and a library of s different buffer sizes, the run time of the presented algorithm is O(log3n·s2). Experimental results show a significant reduction of clock skews ranging from 87 times to 144 times compared to the clock skews before applying the proposed algorithm. We also observe a further reduction of the propagation delay of clock signals as a result of applying the proposed skew sensitivity algorithm. References [1] H. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Addison-Wesley, 1990. [2] K. D. Boese and A. B. Kahng, “Zero-Skew Clock Routing Trees with Minimum Wire-length,” Proc. 5th IEEE Intl. Conf on ASIC, NY, pp. 17 - 21, 1992. [3] T.-H. Chao, Y.-C. Hsu, J.-M. Ho, “Zero-Skew Clock Net Routing,” Proc. 29th ACM/IEEE Design Automation Conf., pp. 518-523, 1992. [4] N.-C. Chou, C.-K. Cheng, “Wire Length and Delay Minimization in General Clock Net Routing,” Proc. IEEE Intl. Conf. on Computer-Aided Design, pp. 552-555, 1993. [5] T. Cormen, C. Leiserson, and R. Rivest, Introduction to Algorithms. MIT Press, 1990. [6] M. A. B. Jackson, A. Srinivan, and E. S. Kuh. “Clock Routing for high performance ics.” Proc. Design Automation Conferences, pp. 573-579, 1990 [7] A. Kahng, J. Cong, G. Robins. “High-Performance Clock Routing Based on Recursive Geometric Matching,” Proceedings of Design Automation Conferences, pp. 322-327, 1991 [8] S. Pullela, N. Menezes, J. Omar, L. Pillage, “Skew and Delay Optimization for Reliable Buffered Clock Trees”, Proc. IEEE Intl. Conf. on Computer-Aided Design, pp. 556-562, 1993. [9] S. Pullela, L. Pillage, Personal communication. [10] T. Sakurai, “A Unified Theory for Mixed CMOS/BiCMOS Buffer Optimization,” IEEE Journal of Solid-State Circuits, vol. 27, no. 7, July 1992. [11] R.-S. Tsay, “Exact Zero Skew,” Proc. IEEE Intl. Conf. on Computer Aided Design, pp. 336-339, 1991. ICCAD94, Pages 284-288 Process-Variation-Tolerant Clock Skew Minimization Shen Lin and C. K. Wong IBM T.J. Watson Research Center, Yorktown Heights, NY 10598 Abstract In this paper,we propose a novel hierarchical multiple-merge zero skew clock routing algorithm. The routing results produced by our approach will have zero skew in the nominal case and minimal skew increase in the presence of worst process variations. In order to construct such a clock routing, we formulate the linear placement withmaximumspread problem and provide an O(n min{n, P}logn log P) algorithm for optimally solving this problem, where n is the number of cells to be placed and P is the maximum spread. Experimental results show that our algorithm can indeed reduce the skew in various manufacturing variations effectively. References [1] Ren-Song Tsay, “Exact Zero Skew,” Proc. ICCAD, pp. 336-339, Nov. 1991. [2] Ren-Song Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” IEEE Trans. on Computer Aided Design, pp. 242-249, Feb. 1993. [3] T. Chao, Y. Hsu, J. Ho, K. Boose, and A. Kahng, “Zero Skew Clock Routing with Minimum Wirelength,” IEEE Trans. on Circuit and Systems, pp. 799-814, Nov. 1992. [4] Qing Zhu andWayneDai, “Perfect-balance Planar Clock Routing with Minimal Path-length,” Proc. ICCAD, pp. 473-476,Nov. 1992. [5] A. Kahng, J. Cong, and G. Robins, “High-Performance clock routing based on recursive geometricmatching,” Proc. DAC, pp. 322-327, June 1991. [6] A. L. Fisher and H. T. Kung, “Synchronous large systolic arrays,” Proc. SPIE, pp. 44-52, 1982. [7] S. Dhar, M. A. Franklin and D. F. Wann, “Reduction of clock delays in VLSI structures,” Proc. ICCD, pp. 778783, 1984. [8] M. A. B. Jackson,A. Srinivasan and E. S. Kuh, “Clock routing for high-performance IC’s,” Proc. DAC, pp. 573579, June 1990. [9] Barbara Simons, “A Fast Algorithm for Single Processor Scheduling,” 19-th Annual Symp. on Foundations of Computer Science, pp. 246-252, Oct. 1978. [10] Daniel W. Dobberpuhl, et. al. “A 200-MHz 64-b Dual-Issue CMOS Microprocessor”, IEEE J. of Solid-State Circuits, pp. 1555-1567, Nov. 1992. ICCAD94, Pages 289-292 A Specified Delay Accomplishing Clock Router Using Multiple Layers Mitsuho Seki*, Kenji Inoue*, Kazuo Kato**, Kouki Tsurusaki**, Shin'ichi Fukasawa**, Hitoshi Sasaki*** and Mutsuhito Aizawa*** *Hitachi Research Laboratory, Hitachi Ltd. **Semiconductor Dept., Hitachi Ltd. ***Hitachi Engineering Co. Abstract Clock routing to minimize the clock skew is very necessary to make high performance LSIs. Our clock routing method: (1) realizes the specified delay to each input terminal and provides a zero skew; (2) uses multiple routing layers for pin-to-pin routing; and (3) considers the delay arising from the resistance of a through-hole. Experimental results show that the delay is within 1% error compared to the specified delay and the skew can be controlled within pico second order. References [1] M.A.B. Jackson, et al., "Clock Routing for High-Performance ICs", 27th DAC, pp 573-579,1990 [2] A. Kahng, J. Cong & G. Robins, "High Performance Clock Routing Based on Recursive Geometric Matching", 28th DAC, pp322-327,1991 [3] M. Edahiro, "A Clock Net Reassignment Algorithm Using Voronoi Diagram", ICCAD, pp420-423,1990 [4] Q. Zhu et al, "Perfect-balance Planar Clock Routing with Minimal Path-length", ICCAD, Pp473-476,1992 [5] R.S. Tsay, "Exact Zero Skew", ICCAD, pp336-339,1991 [6] T.H. Chao, Y.C. Hau & J.M. Ho, "Zero Skew Clock Net Routing", 29th DAC, pp518-523,1992 [7] S. Pullela, et al., "Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization", 30th DAC, pp 165170, 1993 [8] W. Khan, et al., "Zero Skew Clock Routing in Multiple-Clock Synchronous Systems", ICCAD, pp464-467,1992 [9] J. Rubinstein, P. Penfield & M.A. Horowitz, "Signal Delay in RC Tree Networks", IEEE Trans. on ComputerAided Design. vol. CAD-2, No.3, pp202-211, July, 1983 [10] W.C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wide-Band Amplifiers", J. of Applied Physics, vol. 19, No. l, pp55-63, January, 1948 [11] I.W. Sandberg & A.N. Willson. "Some Theorems on Properties of DC Equations of Non-Linear Networks", BSTJ, vol.48,pp1-34,1969 [12] H. Kitazawa, "A Line Search Method for High Routing Rate", J. of Information Processing Society of Japan, vol.26, No. 11, pp1366-1373,1983 (in Japanese) [13] S. Kodama & N. Suda, "Matrix Theory for System Control", Measurement Automation Society, The 2nd Edition. 1985. Ohm Press (in Japanese) ICCAD94, Pages 294-299 Switching Activity Analysis Considering Spatiotemporal Correlations Radu Marculescu, Diana Marculescu, Massoud Pedram Department of Electrical Engineering – Systems, University of Southern California, Los Angeles, CA 90089-2562 Abstract This work presents techniques for computing the switching activities of all circuit nodes under pseudorandom or biased input sequences and assuming a zero delay mode of operation. Complex spatiotemporal correlations among the circuit inputs and internal nodes are considered by using a lag-one Markov Chain model. Evaluations of the model and a comparative analysis presented for benchmark circuits demonstrates the accuracy and the practicality of the method. The results presented in this paper are useful in power estimation and low power design. References [1] K. Parker, and E. J. McCluskey, ‘Probabilistic Treatment of General Combinational Networks’, in IEEE Trans.on Computers, vol. C-24, June 1975 [2] L H. Goldstein, ‘Controllability/Observability Analysis of Digital Circuits’, in IEEE Trans.Circuits and Systems, vol.CAS-26, Sept.1979 [3] S. C. Seth, L. Pan, and V.D.Agrawal ‘PREDICT – Probabilistic Estimation of Digital Circuits Testability’, in Proc. 1985 Fault-Tolerant Computing Symposium [4] J. Savir, G. S. Ditlow, and P. H. Bardell, ‘Random Pattern Testability’, in IEEE Trans.on Computers, vol. C-33, Jan.1984 [5] S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Ricco, ‘Testability Measures in Pseudorandom Testing’, in IEEE Trans. on CAD, vol. 11, June 1992 [6] S.Chakravarty, ‘On the Complexity of Using BDDs for the Synthesis and Analysis of Boolean Circuits’, in Proc. of the 27th Annual Allerton Conf. on Comm., Control and Computing, 1989 [7] F. N. Najm, ‘Transition Density, a Stochastic Measure of Activity in Digital Circuits’, in Proc. 1991 Design Automation Conference [8] R. E. Bryant, ‘Symbolic Boolean Manipulation with Ordered Binary-Decision Diagrams’, in ACM Computing Surveys, Vol. 24, No. 3, Sept. 1992 [9] A. Ghosh, S. Devadas, K. Keutzer, and J. White, ‘Estimation of Average Switching Activity in Combinational and Sequential Circuits’, in Proc. 1992 Design Automation Conference [10] C.-Y. Tsui, M. Pedram, and A. M. Despain, ‘Efficient Estimation of Dynamic Power Dissipation with an Application’, in Proc. 1993 Intl. Conference on Computer Aided Design [11] R.Marculescu, D.Marculescu, and M.Pedram, ‘Logic Level Power Estimation Considering Spatiotemporal Correlations’, Technical Report CENG 94-05, April 1994 [12] A. Papoulis, ‘Probability, Random Variables, and Stochastic Processes’, McGraw-Hill Co., 1984 [13] P. H. Bardell, W. H. McAnney, and J. Savir, ‘Built-in Test for VLSI: Pseudorandom Techniques’, J. Wiley & Sons Inc. 1987 [14] E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, and R. K. Brayton and A. Sangiovanni-Vincentelli, ‘Sequential Circuit Design Using Synthesis and Optimization’, in Proc. 1992 ICCD ICCAD94, Pages 300-303 Estimation of Circuit Activity Considering Signal Correlations and Simultaneous Switching Tan-Li Chou Electrical Engineering, Purdue University, West Lafayette, IN Kaushik Roy Electrical Engineering, Purdue University, West Lafayette, IN. Sharat Prasad Integrated Systems Lab., Texas Instruments, Inc., Dallas, TX. Abstract This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth [4]. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented an technique to calculate signal probability and switching activity of the CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered the switching activities of the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results. References [1] K. P. Parker and E. J. McCluskey, “ProbabilisticTreatment of GeneralCombinatorial Networks," IEEE Trans. on Computers., vol. C-24, Jun. 1975, pp. 668-670. [2] F.N. Najm, “Transition Density, A Stochastic Measure of Activity in Digital Circuits," ACM/IEEE Design Automation Conf., 1991, pp. 644-649. [3] K. Roy and S. Prasad, “Circuit Activity Based Logic Synthesis for Low Power Reliable Operations," IEEE Trans. on VLSI Systems, Dec. 1993, pp. 503-513. [4] A.P. Chandrakashan, S. Sheng, and R. Brodersen, “Low Power CMOS Digital Design," IEEE Trans. on SolidState Circuits., vol. 27, No. 4, April, 1992, pp. 473-483. [5] A. Ghosh, S. Devadas, K. Keutzer, and J. White, “Estimation of Average Switching Activity in Combinational and Sequential Circuits," ACM/IEEE Design Automation Conf., 1992, pp. 253-259. [6] J. Monteiro, S. Devadas, B. Lin, C-Y. Tsui, M. Pedram, and A. Despain, “Exact and Approximate Methods of Switching Activity Estimation in Sequential Logic," Intl. Workshop on Low Power Design, Napa Valley, 1994. [7] S. Prasad and K. Roy, “Circuit Optimization for Minimization of Power Consumption under delay Constraint," Intl. Workshop on Low Power Des ign, Napa Valley, 1994. [8] C. Tsui, M. Pedram, and A. Despain, “Technology Decomposition and Mapping Targeting Low Power Dissipation," ACM/IEEE Design Automation Conf., 1993, pp. 68-73. [9] B. Kapoor, “Improving the Accuracy of Circuit Activity Measurement," ACM/IEEE Design Automation Conf., 1994, pp. 734-739. ICCAD94, Pages 304-309 A Cell-Based Power Estimation in CMOS Combinational Circuits Jiing-Yuan Lin, Tai-Chien Liu and Wen-Zen Shen Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, HsinChu 30050, Taiwan R.O.C. Abstract In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrough effect. Based on the model, a Cell-Based Power Estimation (CBPE) method is developed to estimate the power dissipation in CMOS combinational circuits. In our technique, we first construct a modified state transition graph called STGPE to model the power consumption behavior of a logic gate. Then, according to the input signal probabilities and transition densities of the logic gate, we perform an efficient method to estimate the expected activity number of each edge in the STGPE. Finally, the energy consumption of a logic gate is calculated by summing the energy consumptions of each edge in STGPE. For a set of benchmark circuits, experimental results show that the power dissipation estimated by CBPE is on average within 10-percent errors as compared to the exact SPICE simulation while the CPU time is more than two order-ofmagnitudes faster. References [1] A. Ghosh, S. Devadas, K. Keutzer, J. White, "Estimation of Average Switching Activity in Combinational and Sequential Circuits," In ACM/IEEE 29th Design Automation Conference, pp. 253-259, 1992. [2] C. Y. Tsui, M. Pedram, A. M. Despain, "Power Estimation Considering Charging and Discharging of Internal Nodes of CMOS gates," In SASIMI'93, pp. 345-354, 1993. [3] S. Devadas, K. Keutzer, J. White, "Estimation of Power Dissipation in CMOS combinational Circuits," In IEEE Custom Integrated Circuits Conference, pp. 19.7.1-19.7.6, 1990 [4] F. N. Najm, "Transition Density : A New Measure of Activity in Digital Circuits," IEEE Trans. Computer-Aided Design, Vol. 12, No. 2, pp. 310-323, Feb. 1993. [5] C. Y. Tsui, M. Pedram, A. M. Despain, "Efficient Estimation of Dynamic Power Consumption under a Real Delay Model," In IEEE international Conference on Computer Aided Design, pp. 224-228, 1993. [6] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, "MIS: A multiple-level logic optimization system," IEEE Trans. Computer-Aided Design, Vol. CAD-6, pp. 1062-1081, Nov. 1987. [7] A. Papoulis, Probability, Random variables, and Stochastic Process, 2nd Edition. New York: McGraw-Hill, 1984. [8] J. Monteiro, S. Devadas and B. Lin, "A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits," In ACM/IEEE 31st Design Automation Conference, pp. 12-17, 1994. ICCAD94, Pages 312-316 Design Exploration for High-Performance Pipelines Smita Bakshi and Daniel D. Gajski Department of Information and Computer Science, University of California, Irvine, CA, 92717-3425 Abstract Exploration plays an important role in the design of high-performance pipelines. We propose an exploration strategy for varying three design parameters by using a performance-constrained component selection and pipelining algorithm on different “architectures". The architecture is specified manually by using a mix of behavioral and structural constructs, while the component selection and pipelining is performed automatically using our algorithms. Results on two industrial-strength DSP systems, indicate the effectiveness of our strategy in exploring a large design space within a matter of seconds. References [1] N. Park and A. C. Parker, “Sehwa: A software package for synthesis of pipelines from behavioral specifications," IEEE Transactions on Computer Aided Design, vol. 7, pp. 356-370, Mar. 1988. [2] K. S. Hwang, A. E. Casavant, C.-T. Chang, and M. A. d'Abreu, “Scheduling and hardware sharing in pipelined data paths," in Proceedings of the IEEE International Conference on Computer Aided Design, pp. 24-27, 1989. [3] C.-T. Hwang, Y.-C. Hsu, and Y.-L. Lin, “PLS: A scheduler for pipeline synthesis," IEEE Transactions on Computer Aided Design, vol. 12, pp. 1279-1286, Sept. 1993. [4] R. Jain, A. Parker, and N. Park, “MOSP: Module selection for pipelined designs with multi-cycle operations," in Proceedings of the IEEE International Conference on Computer Aided Design, pp. 212-215, 1990. [5] R. Jain, A. Parker, and N. Park, “Predicting area-time tradeoffs for pipelined design," in Proceedings of the 24th Design Automation Conference, pp. 35-41, 1987. [6] M. Balakrishnan and P. Marwedel, “Integrated scheduling and binding: a synthesis approach for design space exploration," in Proceedings of the 26th Design Automation Conference, pp. 68-74, 1989. [7] L. Ramachandran and D. D. Gajski, “An algorithm for component selection in performance optimized scheduling," in Proceedings of the IEEE International Conference on Computer Aided Design, pp. 92-95, 1991. [8] A. H. Timmer, M. J. M. Heijligers, L. Stok, and J. A. G.Jess, “Module selection and scheduling using unrestricted libraries," in Proceedings of the European Design Automation Conference, pp. 547-551, 1993. [9] S. Bakshi and D. D. Gajski, “A component selection algorithm for high-performance pipelines," in Proceedings of EURO-DAC, 1994. [10] P. M. Embree and B. Kimble, C Language Algorithms for Digital Signal Processing. Englewood Cliffs, New Jersey 07632: Prentice Hall, Inc, 1991. [11] S. Bakshi and D. D. Gajski, “Design space exploration for the beamformer system," Tech. Rep. 93-34, Dept. of Information and Computer Science, University of California, Irvine, 1993. [12] J. Kipps, An Approach to Component Generation and Technology Adaptation. PhD thesis, University of California, Irvine, 1991. ICCAD94, Pages 317-321 Simultaneous Functional-Unit Binding and Floorplanning Yung-Ming Fang * and D. F. Wong ** Department of Electrical and Computer Engineering * Department of Computer Science ** University of Texas at Austin, TX 78712 Abstract As device feature size decreases, interconnection delay becomes the dominating factor of system performance. Thus it is important that accurate physical information is used during high level synthesis. In this paper, we consider the problem of simultaneously performing functional-unit binding and oorplanning. Experimental results indicate that our approach to combine binding and oorplanning is superior to the traditional approach of separating the two tasks. References [1] H. B. Bakoglu, “Circuits, Interconnections and Packaging for VLSI," pp. 194-225, 1990. [2] F. Brewer and D. Gajski, “Chippe: A System for Constraint Driven Behavioral Synthesis," IEEE Trans. on CAD, Vol. 9, No. 7, pp. 681-695, 1990. [3] Michael R. Garey and David S. Johnson, “Graph K-Colorability," Computers and Intractability, A Guide to the Theory of NP-Completeness, 1979. [4] M. S. Hecht, “Flow Analysis of Computer Programs," North-Holland, 1977. [5] Hyuk-Jae Jang and Barry M. Pangrle, “A Grid-Based Approach for Connectivity Binding with Geometric Costs," Proc. of ICCAD, pp. 94-99, 1993. [6] David W. Knapp, “Fasolt: A Program for Feedback-Driven Data-Path Optimization," IEEE Trans. on CAD, Vol. 11, No. 6, pp. 677-695, 1992. [7] Michael C. McFarland, “Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions," Proc. of 23rd DAC, pp. 474-480, 1986. [8] Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamary, “Layout-Driven Module Selection for Register-Transfer Synthesis of Sub-micron ASIC's," Proc. of ICCAD, pp. 100-103, 1993. [9] Ashutosh Mujumdar, Minjoong Rim, Rajiv Jain, and Renato De Leone “BITNET: An Algorithm for Solving The Binding Problem," 7th International Conference on VLSI Design, pp. 163-168, 1994. [10] Jen-Pin Weng and Alice C. Parker, “3D Scheduling: High-Level Synthesis with Floorplanning," Proc. of 28th DAC, pp. 668-673, 1991. [11] D. F. Wong and C. L. Liu, “A New Algorithm for Floorplan Design," Proc. of 23rd DAC, pp. 101-107, 1986. [12] Dian Zhou, Franco P. Preparata and S. M. Kang, “Interconnection Delay in Very High-Speed VLSI," IEEE Trans. on Circuits and Systems, Vol 38, No. 7, pp. 779-790, 1991. ICCAD94, Pages 322-329 Module Selection and Data Format Conversion for Cost-Optimal DSP Synthesis Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455 Abstract In high level synthesis each node of a synchronous data-flow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear programming (ILP) models which generate a blocked schedule for a DFG with implicit retiming, pipelining, and unfolding while performing module selection and data format conversion. A blocked schedule is a schedule which overlaps multiple iterations of the DFG to guarantee a minimum number of processors. Component modules are selected from a library of processors to minimize cost. Furthermore, we include data format converters between processors of different data formats. In addition, we minimize the unfolding factor of the blocked schedule. References [1] M. C. McFarland, A. C. Parker, and R. Camposano, “The High-Level Synthesis of Digital Systems,” Proc. of the IEEE, vol. 78, pp. 301–318, Feb. 1990. [2] M. Renfors and Y. Neuvo, “The Maximum Sampling Rate of Digital Filters under Hardware Speed Constraints,” IEEE Trans. Circuits Syst., vol. CAS-28, pp. 196–202, Mar. 1981. [3] K. K. Parhi and D. G. Messerschmitt, “Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding,” IEEE Trans. Computers, vol. C-40, pp. 178–195, Feb. 1991. [4] M. R. Garey and D. S. Johnson, Computers and Intractability: a Guide to the Theory of NP-completeness. San Francisco: W. H. Freeman, 1979. [5] P. G. Paulin and J. P. Knight, “Force-Directed Scheduling for the Behavioral Synthesis of ASIC’s,” IEEE Trans. Computer-Aided Design, vol. CAD-8, pp. 661–679, June 1989. [6] N. Park and A. C. Parker, “Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications,” IEEE Trans. Computer-Aided Design, vol. 7, Mar. 1988. [7] S. M. Heemstra de Groot, S. H. Gerez, and O. E. Herrmann, “Range-Chart-Guided Iterative Data-Flow Graph Scheduling,” IEEE Trans. Circuits Syst.-I: Fund. Theory & Appl., vol. CAS-39, pp. 351–364, May 1992. [8] C.-Y. Wang and K. K. Parhi, “Resource Constrained Loop List Scheduler for DSP Algorithms,” Journal of VLSI Signal Processing, Special issue of VLSI Design Methodologies for Digital Signal Processing Systems, to appear in 1994. [9] C.-T. Hwang, J.-H. Lee, andY.-C. Hsu, “A Formal Approach to the Scheduling Problem in High Level Synthesis,” IEEE Trans. Computer-Aided Design, vol. CAD-10, pp. 464–475, Apr. 1991. [10] C. H. Gebotys, “Synthesis of Throughput-Optimized Multichip Architectures,” in Proc. IEEE Custom Integrated Circuits Conf., San Diego, pp. 5.2.1–5.2.4, May 1993. [11] C. H. Gebotys and R. J. Gebotys, “Optimal Mapping of DSP Applications to Architectures,” in Proc. 26th Hawaii Int. Conf. System Sciences, pp. 116–123, 1993. [12] C. H. Gebotys and M. I. Elmasry, “Global Optimization Approach for Architecture Synthesis,” IEEE Trans. Computer-Aided Design, vol. CAD-12, pp. 1266–1278, Sept. 1993. [13] C.-T. Hwang and Y.-C. Hsu, “Zone Scheduling,” IEEE Trans. Computer-Aided Design, vol. CAD-12, pp. 926– 934, July 1993. [14] A. Bachmann, M. Schöbinger, and L. Thiele, “Synthesis Methods for Domain Specific Multiprocessor Systems including Memory Design,” in VLSI Signal Processing, VI, pp. 417–425, 1993. [15] L. E. Lucke and K. K. Parhi, “Generalized ILP Scheduling and Allocation for High-Level DSP Synthesis,” in Proc. IEEE Custom Integrated Circuits Conf., San Diego, pp. 5.4.1–5.4.4, May 1993. [16] C. E. Leiserson et al., “Optimizing Synchronous Circuitry by Retiming,” in 3rd Caltech Conf. on VLSI, Pasadena, CA, pp. 87–116, Mar. 1983. [17] J. Jump and S. Ahuja, “Effective Pipelining of Digital Systems,” IEEE Trans. Computers, vol. C-27, pp. 855– 865, Sept. 1978. [18] J. M. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, “Fast Prototyping of Datapath-Intensive Architectures,” IEEE Design & Test of Computers, vol. 8, pp. 40–51, June 1991. [19] M. Ishikawa and G. D. Micheli, “A module Selection Algorithm for High-Level Synthesis,” in Proc. of the IEEE Int. Symp. Circuits and Systems, Singapore, pp. 1777–1780, June 1991. [20] A. H. Timmer and J. A. G. Jess, “Execution Interval Analysis under Resource Constraints,” in Proc. of the IEEE Int. Conf. on Computer Aided Design, pp. 454–459, 1993. [21] K. K. Parhi, “A Systematic Approach for Design of Digit-Serial Processing Architectures,” IEEE Trans. Circuits Syst., vol. 38, pp. 358–375, Apr. 1991. [22] L. E. Lucke and K. K. Parhi, “Data-Flow Transformations for Critical Path Reduction in High-Level DSP Synthesis,” IEEE Trans. Computer-Aided Design, vol. CAD-12, pp. 1063–1068, July 1993. [23] E. F. Girczyz, “Loop Winding—A Data Flow Approach to Functional Pipelining,” in Proc. of the IEEE Int. Symp. Circuits and Systems, Philadelphia, pp. 382–385, May 1987. [24] D. A. Schwartz and T. P. Barnwell, III, “Cyclo-static solutions: Optimal multiprocessor realizations of Recursive Algorithms,” VLSI Signal Processing II, 1986. [25] A. Brooke, D. Kendrick, and A. Meeraus, GAMS: A User’s Guide, Release 2.25. South San Francisco, CA: The Scientific Press, 1992. ICCAD94, Pages 332-339 On Testing Delay Faults In Macro-Based Combinational Circuits Irith Pomeranz and Sudhakar M. Reddy  Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA 52242 Abstract We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be used for such circuits, since the implementation of a macro may not have an accurate gate-level counterpart, or the macro implementation may not be known. Two delay fault models are proposed for macrobased circuits. The first model is analogous to the gatelevel gross delay fault model. The second model is analogous to the gate-level path delay fault model. We provide fault simulation procedures, and present experimental results. References [1] K. Keutzer, "DAGON: Technology binding and local optimization by DAG Matching", 24th Design Autom. Conf., 1987, pp. 341-347. [2] U. Schlichtmann, F. Brglez and M. Hermann, "Characterization of Boolean Functions for Rapid Matching in EPGA Technology Mapping", 29th Design Autom. Conf., June 1992, pp. 374-379. [3] S. D. Brown, R. J. Francis, J. Rose and Z. G. Vranesic Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992. [4] Z. Barzilai and B. Rosen, "Comparison of AC Self-Testing Procedures," 1983 Intl. Test Conf., pp. 89-94. [5] J. L. Carter, V. S. Iyengar and B. K. Rosen, "Efficient Test Coverage Determination for Delay Faults", 1987 Intl. Test Conf., Sept. 1987, pp. 418-427. [6] G. L. Smith, "Model for Delay Faults Based Upon Paths," 1985 Intl. Test Conf., pp. 342-349. [7] I. Pomeranz and S. M. Reddy, "An Efficient Non-Enumerative Method to Estimate the Path Delay Fault Coverage in Combinational Circuits", IEEE Trans. on CAD., Feb. 1994, pp. 240-250. [8] C. J. Lin and S. M. Reddy, "On delay fault testing in logic circuits," IEEE Trans. CAD, pp. 694-703, Sept. 1987. [9] W.-N. Li, S. M. Reddy and S. K. Sahni, "On path Selection in Combinational Logic Circuits", IEEE Trans. on CAD, Jan. 1989, pp. 56-63. [10] I. Pomeranz and S. M. Reddy, "Testability Considerations in Technology Mapping", 3rd Asia Test Symp., Nov. 1994. [11] T. W. Williams, B. Underwood and M. R. Mercer, "The Interdependence between Delay-Optimization of Synthesized Networks and Testing", 28th Design Autom. Conf., June 1991, pp. 87-92. [12] M. Abramovici, M. Breuer, A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990. [13] J. Waicukauski, E. Lindbloom, B. Rosen and V. Iyengar, "Transition Fault Simulation," IEEE Design & Test, April 1987, pp. 32-38. [14] M. Yoeli and S. Rinon, "Applications of Ternary Algebra to the Study of Static Hazards", JACM, pp. 84-97, Jan. 1964. [15] E. J. McCluskey, Logic Design Principles with Emphasis on Testable Semicustom Circuits, Prentice-Hall, 1986. ICCAD94, Pages 340-343 RAFT: A Novel Program for Rapid-Fire Test and Diagnosis of Digital Logic for Marginal Delays and Delay Faults Abhijit Chatterjee Georgia Institute of Technology, Atlanta, GA Jacob A. Abraham University of Texas at Austin, Austin, TX. ABSTRACT The problem of delay fault-testing and detection of chips with marginal performance has become even more critical than before due to advancing clock speeds. In this paper, a methodology for detection of marginal digital circuits and diagnosis of gate delay failures is developed. A new test application methodology is proposed in which test vectors may be applied to digital combinational circuits at intervals smaller than the critical path delay of the circuit and signal waveform analysis is used to interpret the test results. The resulting tests are called RApid Fire Tests (for RAFT) and allow classification of circuits from "good" to "bad" along a continuous scale. References 1. W. Maly and P. Nigh, ‘‘Built-in Current Testing - Feasibility Study,’’ International Conference on ComputerAided Design, pp. 340-343 (1988). 2. E. P. Hseih et. al., ‘‘Delay Test Generation,’’ Design Automation Conference, pp. 486-491 (1977). 3. Y. K. Malaiya and R. Narayanswamy, ‘‘Testing for Timing Faults in Synchronous Sequential Integrated Circuits,’’ International Test Conference, pp. 560-571 (1983). 4. G. L. Smith, ‘‘Model for Delay Faults Based Upon Paths,’’ International Test Conference, pp. 342-34 (1985). 5. C. J. Lin and S. M. Reddy, ‘‘On Delay Fault Testing in Logic Circuits,’’ International Conference on ComputerAided Design, pp. 694-703 (1985). 6. S. M. Reddy et. al., ‘‘An Automatic Test Pattern Generator for the Detection of Delay Faults,’’ International Conference on Computer-Aided Design, pp. 284-287 (1987). 7. M. H. Schulz, ‘‘Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults,’’ International Symposium on Fault-Tolerant Computing, pp. 44-51 (1989). 8. J. P. Lesser and J. J. Schedletsky, ‘‘An Experimental Delay Test Generator for LSI Logic,’’ IEEE Transacions on Computers, pp. 235-248 (March 1980). 9. K. Roy and J. A. Abraham, ‘‘Synthesis of Delay Fault Testable Combinational Logic,’’ International Conference on Computer-Aided Design, pp. 418-421 (1989). 10. A. K. Pramanik and S. M. Reddy, ‘‘Synthesis of Combinational Logic for Path Delay Fault Testability,’ International Symposium on Circuits and Systems, pp. 3105-3108 (1990). 11. S. Kundu and S. M. Reddy, ‘‘On the Design of Robust Testable CMOS Combinational Logic Circuits,’’ Interational Symposium on Fault-Tolerant Computing, pp. 220-225 (1988). 12. S. Devadas and K. Keutzer, ‘‘Validatable Nonrobust Delay-Fault Testable Circuits Via Logic Synthesis,’’ International Symposium on Circuits and Systems, pp. 3109-3113 (1988). 13. V. S. Iyengar and G. Vijayan, ‘‘Test Application Timing: The Unexplored Issue in AC Test,’’ International Test Conference, pp. 840-847 (). 14. I. Pomeranz and S. M. Reddy, ‘‘An Efficient Nonenumerative Method to estimate the Path Dealy Fault Coverage in Combinational Circuits,’’ IEEE Transactions on Computer-Aided Design 13, No 2(February 1994). 15. H. Hao and E. J. McCluskey, ‘‘Very-low-voltage Testing for Weak CMOS ICs,’’ International Test Conference, pp. 275-284 (1993). 16. P. Franco and E. J. McCluskey, ‘‘Delay Testing of Digital Circuits By Output Waveform Analysis,’’ International Test Conference, pp. 798-807 (). ICCAD94, Pages 344-348 A Comprehensive Fault Macromodel For Opamps Chen-Yang Pan and Kwang-Ting Cheng Dept. of Electrical & Computer Engineering, University of California, Santa Barbara Sandeep Gupta Dept. of Electrical Engineering – Systems, University of Southern California Abstract In this paper, a comprehensive macromodel for transistor level faults in an operational amplifier is developed. With the observation that faulty behavior at output may result from interfacing error in addition to the faulty component, parameters associated with input and output characteristics are incorporated. Test generation and fault classification are addressed for standalone opamps. A high fault coverage is achieved by a proposed testing strategy. Transistor level short/bridging faults are analyzed and classified into catastrophic faults and parametric faults. Based on the macromodels for parametric faults, fault simulation is performed for an active filter. We found many parametric faults in the active filter cannot be detected by traditional functional testing. A DFT scheme along with a current testing strategy to improve fault coverage is proposed. Reference [1] Anne Mexixner and Wojciech Maly. "Fault modeling for the testing of mixed integrated circuits", ITC 1991, pp.564-572 [2]Naveena Nagi and Jacob A. Abraham. "Hierarchical fault modeling for analog and mixed-signal circuits", VLSI Test Symposium 1992, pp.96-101 [3] Naveena Nagi, Abhijit Chatterjee and Jacob A. Abraham. "DRAFTS: Discretized analog circuit fault simulator", Proc. ACM/IEEE DAC 1993, pp.96-101 [4] Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham. "Fault-based automatic test generator for linear analog circuits", ICCAD 1993, pp. 88-91 [5] Edgar Sanchez-Sinencio and Marian L. Majewski. "A nonlinear macromodel of operational amplifiers in the frequency domain", Transactions on Circuits and Systems, June 1979, pp.395-402, Vol.26, No.6 [6]Graeme R. Boyle et. al. "Macromodeling of integrated circuit operational amplifiers" Journal of Solid State Circuits, Dec 1974, pp.353-367, Vol.9, No.6. [7] Paul R. Gray, Robert G. Meyer, "Analysis and Design of Analog Integrated Circuits", 1993 [8] Alan B. Grebene. "Bipolar and MOS analog integrated circuit design", 1984 [9] Glaudio Turchetti and Guido Masetti. "A macromodel for integrated all-MOS operational amplifiers", Journal of Solid State Circuits, Aug 1983,pp.389-394, Vol.18, No.4 [10]M. Soma, “A Design-for-Test methodology for active analog filter”, ITC 1990, pp. 183-189 ICCAD94, Pages 350-355 Channel-Driven Global Routing with Consistent Placement (extended abstract for ICCAD '94) Shigetoshi Nakatake * and Yoji Kajitani ** *School of Information Science, Japan Advanced Institute of Science and Technology, Tatsunokuchi, Ishikawa 923-12, Japan **Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Meguro-ku, Tokyo 142, Japan Abstract A global router with its consistent placer is proposed which aims to control wire-densities of channels. The routing order of nets and their routes are decided according to the channel which is predicted to have the maximum wire-density. The placer distributes the nets evenly with respect to the virtual length (half perimeter of the bounding box). Interesting features included are the interactive dynamic test to decide the form of predicting functions and the admissible region to consider the routing resources in placement stage. Experiments reveal some interesting phenomena that smaller maximum wire-density is attained in spite of comparable total wiredensity and that smaller maximum wire-length in spite o f larger total wire-length. References [1] A.Hashimoto and J. Stevens, "Wire routing by optimizing channel assignment within large apertures," Proc. 8th Design Automation Conference, Jun 1971, pp.155-163. [2] Kirkpatrick, C. Gelett, and M. Vecchi, "Optimization by Simulated Annealing, Science," vol. 220, no. 4598, pp671-680, May 1983. [3] J.T.Mowchenko and C.S.R.Ma,"A New Global Routing Algorithm for Standard Cell ICs", Proc. of International Symposium on Circuits and Systems, pp.27-30,1987. [4] J. Cong and B. Preas, " A New Algorithm for Standard Cell Global Routing," Proc. IEEE International Conference on Computer Aided Design, pp. 176-179, Nov. 1988. [5] S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, Field-Programmable Gate Arrays, Kluwer Acadmic Publishers, 1992. [6] S. D. Brown, J. Rose, and Z. G. Vranesic, "A Stochastic Model to Predict the Routability of FieldProgrammable Gate Arrays", Proc. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 12, pp 1827-1838,1993. ICCAD94, Pages 356-361 A New Global Routing Algorithm for FPGAs Yao-Wen Chang*, Shashidhar Thakur*, Kai Zhu**, and D.F. Wong* *Department of Computer Sciences, University of Texas at Austin, Austin, Texas 78712-1188 **AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, NJ 07974 Abstract As in traditional ASIC technologies, FPGA routing usually consists of two steps: global routing and detailed routing. Unlike existing FPGA detailed routers, which can take full advantage of the special structures of the programmable routing resources, FPGA global routing algorithms still greatly resemble their counterparts in the traditional ASIC technologies. In particular, the routing congestion information of a switch block essentially is still measured by the numbers of available rows and columns in the switch block. Since the internal architecture of a switch block decides what can route through the block, the traditional measure of routing capacity is no longer accurate. In this paper, we present an accurate measure of switch block routing capacity. Our new measure considers the exact positions of the switches inside a switch block. Experiments with a global router based on these ideas show an average improvement of 38% in the channel width required to route some benchmark circuits using a popular switch block, compared with an algorithm based on the traditional methods for congestion control. References [1] N. Bhat and D. Hill, “Routable Technology Mapping for LUT FPGA's," Proc. Intl. Conf. Computer-Aided Design, pp. 95-98, 1992. [2] S. Brown, J. Ross, and Z.G. Vranesic, “A Detailed Router for Field-Programmable Gate Arrays," IEEE Trans. Computer-Aided Design, vol. 11, pp. 620-627, 1992. [3] W. Carter et al., “A User Programmable Reconfigurable Gate Array," Proc. 1986 Custom Integrated Circuits Conference, May 1986, pp. 233-235, 1986. [4] E. Dijkstra, “A Note on Two Problems in Connexion with Graphs," Numerische Mathematik, 1:269-271, 1959. [5] S. Thakur, D.F. Wong, and S. Muthukrishnan, “Algorithms for FPGA Switch Module Routing," Proc. EuroDAC, to appear, 1994. [6] S. Trimberger, ed., Field-Programmable Gate Array Technology, Kluwer Academic Publishers, 1994. [7] S. Trimberger and M. Chene, “Placement-Based Partitioning for Lookup-Table-Based FPGA's," Proc. Intl. Conf. Computer-Aided Design, pp. 91-94, 1992. [8] Xilinx Inc., The Programmable Logic Data Book, 1994. [9] K. Zhu, D.F. Wong, and Y.-W. Chang, “Switch Module Design with Application to Two-Dimensional Segmentation Design," Proc. Intl. Conf. Computer-Aided Design, pp. 481-486, 1993. ICCAD94, Pages 362-366 On the NP-completeness of Regular 2-D FPGA Routing Architectures and A Novel Solution Yu-Liang Wu1, Douglas Chang2 Department of electrical and Computer Engineering1 Department of Computer Science2 University of California, Santa Barbara, CA 93106 Abstract Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of the routing problem on a regular 2-D FPGA routing architecture can be alleviated by adding routing switches. We show that on this routing architecture, even with a substantial increase in switching flexibility, a polynomial time, predictable routing algorithm is still not likely to exist, and there is no constant ratio bound of the detailed over global routing channel densities. We also show that a perfect routing is unachievable on this architecture even with near complete (maximum) switching flexibility. We also discuss a new, greedy routing architecture, that possesses predictable and other desired routing properties, yet requires fewer routing resources than regular architectures. This theoretical result may suggest an alternative approach in routing architecture designs. References: [1]. "The Programmable Logic Data Book", Xilinx, 1994. [2]. Yu-Liang Wu, and Malgorzata Marek-Sadowska, "Graph Based Analysis of FPGA Routing", Proceedings of EURO-DAC with EURO-VHDL, pp. 104-109, 1993. [3]. Yu-Liang Wu, Shuji Tsukiyama, and Malgorzata Marek-Sadowska, "On Computational Complexity of a Detailed Routing Problem in Two-Dimensional FPGAs", Proceedings of 4th Great Lakes Symposium on VLSI, March 1994. [4]. Vwani P. Roychowdhury, Jonathan W. Greene, and Abbas El Gamal, "Segmented Channel Routing", IEEE Trans. on CAD, Vol. 12, No. 1. pp. 79-95, January 1993. [5]. S. Brown, J. Rose, and Z. G. Vranesic, "A Detailed Router for Field-Programmable Gate Arrays", IEEE Trans. on CAD, Vol. 11, No. 5. pp. 620-628, May 1992. [6]. Stephen Brown, J. Rose, and Zvonko G. Vranesic, "A Stochastic Model to Predict the Routability of FieldProgrammable Gate Arrays", IEEE Trans. on CAD, Vol 12, No. 12, pp. 1827-1838, December 1993. [7]. Yu-Liang Wu, Shuji Tsukiyama, and Malgorzata Marek-Sadowska, "Graph Based Analysis of 2-D FPGA Routing", submitted for publication. [8]. Yu-Liang Wu, and Malgorzata Marek-Sadowska, "An Efficient Router for 2-D Field Programmable Gate Arrays", Proceedings of EDAC, pp. 412-416, 1994. ICCAD94, Pages 368-371 A Symbolic Method to Reduce Power Consumption of Circuits Containing False Paths R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi University of Colorado, Department of Electrical and Computer Engineering, Boulder, CO 80309 Abstract Power dissipation in technology mapped circuits can be reduced by performing gate re-sizing. Recently we have proposed a symbolic procedure which exploits the compactness of the ADD data structure to accurately calculate the arrival times at each node of a circuit for any primary input vector. In this paper we extend our timing analysis tool to the symbolic calculation of required times and slacks, and we use this information to identify gates of the circuit that can be re-sized. The nice feature of our approach is that it takes into account the presence of false paths naturally. As shown by the experimental results, circuits re-synthesized with the technique we present in this paper are guaranteed to be at least as fast as the original implementations, but smaller and substantially less power-consuming. References [1] A. P. Chandrakasan, S. Sheng, R. W. Brodersen, “Low-Power CMOS Digital Design," IEEE Journal of SolidState Circuits, Vol. 27, No. 4, pp. 473-484, April 1992. [2] C. Y. Tsui, M. Pedram, A. M. Despain, “Technology Decomposition and Mapping Targeting Low Power Dissipation," DAC-30: ACM/IEEE Design Automation Conference, pp. 68-73, Dallas, TX, June 1993. [3] V. Tiwari, P. Ashar, S. Malik, “Technology Mapping for Low Power," DAC-30: ACM/IEEE Design Automation Conference, pp. 74-79, Dallas, TX, June 1993. [4] B. Lin, H. de Man, “Low-Power Driven Technology Mapping under Timing Constraints," ICCD'93: IEEE International Conference on Circuits Design, pp. 421-427, Cambridge, MA, October 1993. [5] R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, F. Somenzi, “Timing Analysis of Combinational Circuits using ADDs," EDAC-94: IEEE European Conference on Design Automation, Paris, France, February 1994. [6] R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, F. Somenzi, “Algebraic Decision Diagrams and their Applications," ICCAD-93: ACM/IEEE International Conference on Computer Aided Design, pp. 188-191, Santa Clara, CA, November 1993. [7] S. Yang, “Logic Synthesis and Optimization Benchmarks User Guide Version 3.0," Technical Report, Microelectronics Center of North Carolina, Research Triangle Park, NC, January 1991. [8] F. N. Najm, “Transition Density, a Stochastic Measure of Activity in Digital Circuits," DAC-28: ACM/IEEE Design Automation Conference, pp. 644-649, San Francisco, CA, June 1991. [9] A. Ghosh, S. Devadas, K. Keutzer, J. White, “Estimation of Average Switching Activity in Combinational and Sequential Circuits," DAC-29: ACM/IEEE Design Automation Conference, pp. 253-259, Anaheim, CA, June 1992. [10] E. M. Sentovich, K. J. Singh, C. W. Moon, H. Savoj, R.K. Brayton, A. Sangiovanni-Vincentelli, “Sequential Circuits Design Using Synthesis and Optimization," ICCD-92: IEEE International Conference on Computer Design, pp. 328-333, Cambridge, MA, October 1992. [11] A. Saldanha, R. K. Brayton, A. L. Sangiovanni-Vincentelli, “Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited," DAC-29: ACM/IEEE Design Automation Conference, pp. 245-248, Anaheim, CA, June 1992. ICCAD94, Pages 372-377 Multi-Level Network Optimization for Low Power Sasan Iman, Massoud Pedram Department of Electrical Engineering – Systems, University of Southern California, Los Angeles, CA 90089 Abstract This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each intermediate node in the network such that the power consumption of the node is decreased without increasing the power consumption of the other nodes in the network. A formal analysis of how changes in the switching activity of an intermediate node affect the switching activity of other nodes in the network is given first. Using this analysis, a procedure for calculating the set of compatible power don’t cares for each node in the network is presented. Finally it is shown how these don’t cares are used to optimize the network for low power. These techniques have been implemented and results show an average of 10% improvement in total power consumption of the network compared to the results generated by the conventional network optimization techniques. References [1] K. Bartlett, R. K. Brayton, G. D. Hachtel, R. M. Jacoby, C. R. Morrison, R. L. Rudell, A. SangiovanniVincentelli, and A. R. Wang. Multi-level logic minimization using implicit don’t cares. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 7, pages 723–740, June 1988. [2] J. B. Burr. Stanford ultra low power CMOS. In Proceedings of Hot Chips Symposium V, pages 583–588, June 1993. [3] E. Cerny. An approach to unified methodology of combinational switching circuits. IEEE International Conference on CAD, 27:8, August 1977. [4] A. P. Chandrakasan, S. S. Scheng, and R. W. Broderson. Low power CMOS digital design. IEEE Journal of Solid State Circuits, 27(4):473–483, April 1992. [5] C. Halatsis and N. Gaitanis. Irredundant normal forms and minimal dependence sets of a boolean function. IEEE Transaction on Computers, pages 1064–1068, November 1978. [6] D. Liu and C. Svensson. Trading speed for low power by choice of supply and threshold voltages. IEEE Journal of Solid State Circuits, 28(1):10–17, January 1993. [7] S. Iman, M. Pedram, C. Fabian and J. Cong. Finding uni-directional cuts based on physical partitioning and logic restructuring. In Proc. the 4th ACM/IEEE Physical Design Workshop, April 1993. [8] Abdul A. Malik, Robert K. Brayton, A. Richard Newton, and Alberto L. Sangiovanni-Vincentelli. A modified approach to two-level logic minimization. In Proceedings of the IEEE International Conference on Computer Aided Design, Nov. 1988. [9] F. Najm. Transition density, a stochastic measure of activity in digital circuits. In Proceedings of the 28th Design Automation Conference, pages 644–649, June 1991. [10] H. Savoj. Don’t Cares in Multi-Level Network Optimization. PhD thesis, University of California, Berkeley, 1992. [11] A. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer. On average power dissipation and random pattern testability of CMOS combinational logic networks. In Proceedings of the IEEE International Conference on Computer Aided Design, November 1992. ICCAD94, Pages 378-381 LP based Cell Selection with Constraints of Timing, Area, and Power Consumption Yutaka Tamiya, Yusuke Tamiya Fujitsu Laboratories Ltd. 1015 Kami-kodanaka, Nakahara-ku, Kawasaki, Japan 211 Masahiro Fujita Fujitsu Laboratories of America, Inc., 77 Rio Robles, San Jose, CA 95134-1807 Abstract This paper resents a new LP based optimal cell selection method. Optimal cell selection is useful tool for final tuning of LSI designs. It replaces drivabilities of cells, adjusting timing, area, and power constraints. Using the latest and earliest arrival times, it can handle both setup and hold time constraints. We also make an efficient initial basis, which speeds up a simplex LP solver by 5 times without any relaxations nor approximations. From experimental results it reduces the clock cycle of a manual designed 13k-transistor chip by 17% without any increase of area. References [1] K. Keutzer, "DAGON: Technology Binding and Local Optimization by DAG Matching," 24th DAC, pp. 341347,1987. [2] R. K. Brayton, R. Rudell, A. L. SangiovanniVincentelli, and A. R. Wang, "MIS: A Multiple-Level Logic Optimization," IEEE Trans. CAD, pp. 1062-1081, Nov. 1987. [3] M. R. C. M. Berkelaar, "Area-Power-Delay-Trade-off in Logic Synthesis," Ph.D. Thesis Eindhoven University of Technology, Eindhoven, The Netherlands, 1992. [4] P. Buurman, M. Berkelaar, and J. Jess, "Computing the Entire Active Area versus Delay Trade-off Curve for Gate Sizing with a Piecewise Linear Simulator," Proc. of International Workshop on Logic Synthesis, 8c,1993. [5] N. V. Shenoy, R. K. Brayton, and A. L. Sangiovanni-Vincentelli "Minimum Padding to Satisfy Short Path Constraints," IWLS '93, 4a,1993. [6] K. A. Sakallah, T. N. Mudge and O. A. Olukotun, "check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits," Proc. of ICCAD-93, pp.552-555,1993. [7] L. W. Wang, Y. T. Lai, B. D. Liu, and T. C. Chang, "A Graph-Based Simplex Algorithm for Minimizing the Layout Size and the Delay on Timing Critical Paths," Proc. of ICCAD-93, pp.703-708,1993. ICCAD94, Pages 384-390 Power Analysis of Embedded Software: A First Step towards Software Power Minimization Vivek Tiwari, Sharad Malik, Andrew Wolfe Dept. of Electrical Engineering, Princeton University, Princeton, NJ 08544 Abstract Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specification of these systems. At present, however, power analysis tools can only be applied at the lower levels of the design - the circuit or gate level. It is either impractical or impossible to use the lower level tools to estimate the power cost of the software component of the system. This paper describes the first systematic attempt to model this power cost. A power analysis technique is developed that has been applied to two commercial microprocessors - Intel 486DX2 and Fujitsu SPARClite 934. This technique can be employed to evaluate the power cost of embedded software and also be used to search the design space in software power optimization. References [1] Intel Corp. i486 Microprocessor, Hardware Reference Manual, 1990. [2] Intel Corp. Intel486 Microprocessor Family, Programmer's Reference Manual, 1992. [3] C. L. Su, C. Y. Tsui, and A. M. Despain. Low power architecture design and compilation techniques for highperformance processors. In IEEE COMPCON, Feb. 1994. [4] V. Tiwari, T.C. Lee, M. Fujita, and D. Maheshwari. Power analysis of the SPARClite MB86934. Technical Report FLA-CAD-94-01, Fujitsu Labs of America, August 1994. [5] V. Tiwari, S. Malik, and A. Wolfe. Compilation techniques for low energy: An overview. In Proceedings of the 1994 Symposium on Low Power Electronics, October 1994. [6] V. Tiwari, S. Malik, and A. Wolfe. Power analysis of the Intel 486DX2. Technical Report CE-M94-5, Princeton Univ., Dept. of Elect. Eng., June 1994. ICCAD94, Pages 391-396 Generating Instruction Sets and Microarchitectures from Applications Ing-Jer Huang and Alvin M. Despain Department of Electrical Engineering – Systems, University of Southern California, Los Angeles, CA 90089-2561 ijhuang@usc.edu, despain@usc.edu Abstract The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design, and instruction set mapping for the application. We present a method that unifies these three design problems with a single formulation: a modified scheduling/allocation problem with an integrated instruction formation process. Micro-operations (MOPs) representing the application are scheduled into time steps. Instructions are formed and hardware resources are allocated during the scheduling process. The assembly code for the given application is obtained automatically at the end of the scheduling process. This approach considers MOP parallelism, instruction field encoding, delay load/store/branch, conditional execution of MOPs and the retargetability to various architecture templates. Experiments are presented to show the power and limitation of our approach. Performance improvement over our previous work [4] is significant. Reference [1] J. P. Bennett, A Methodology for Automated Design of Computer Instruction Sets, Ph.D. thesis, Univ. of Cambridge, Computer Laboratory, 1988 [2] Bruce Holmer, Automatic Design of Computer Instruction Sets, Ph.D. thesis, Computer Science Department, Univ. of California, Berkeley, 1993 [3] Alauddin Alomary, et al., “An ASIP Instruction Set Optimization Algorithm with Functional Module Sharing Constraint,” Proc. of the International Conference on Computer-Aided Designs, Nov. 1993 [4] Ing-Jer Huang and Alvin Despain, “Synthesis of Instruction Sets for Pipelined Microprocessors,” Proc. of the 31st Design Automation Conference, June 1994 [5] Ing-Jer Huang, Co-Synthesis of Instruction Sets and Microarchitectures, Ph.D. thesis, Dept. of Electrical Engineering - Systems, Univ. of Southern California, August 1994 [6] Peter M. Kogge, The Architecture of Pipelined Computers, McGraw-Hill Book Company, 1981 [7] Mauricio Breternitz Jr. and John Paul Shen, “Architecture Synthesis of High-Performance Application-Specific Processors”, Proc. Design Automation Conference, 1990 [8] Srinivas Devadas and Richard Newton, “Algorithms for Hardware Allocation in Data Path Synthesis,” IEEE Trans. on Computer-Aided Design, Vol. 8, No. 7, July 1989 [9] Ing-Jer Huang and Alvin Despain, “Hardware/Software Resolution of Pipeline Hazards in Instruction Set Processors,” Proc. of the International Conference on Computer-Aided Designs, Nov. 1993 [10] Richard Cloutier and Donald Thomas, “Synthesis of Pipelined Instruction Set Processors,” Proc. of 30th DAC, 1993 [11] R. Haygood, A Prolog Benchmark Suite for Aquarius, Technical Report, UCB/CSD 89/509, University of California, Berkeley, 1989 [12] Pierre Paulin, Clifford Liem, Trevor May, Shailesh Sutarwala, “DSP Design Tool Requirements for Embedded Systems: A Telecommunications Industrial Perspective,” to appear in Journal of VLSI Signal Processing, 1994 [13] Clifford Liem, Trevor May, Pierre Paulin, “Instruction-Set Matching and Selection for DSP and ASIP Code Generation,” Proc. of EDAC, 1994 [14] Johan Van Praet, Gert Goossens, Dirk Lanneer, Hugo De Man, “Instruction Set Definition and Instruction Selection for ASIPs,” Proc. of Int’l Symposium on High Level Synthesis, May 1994 [15] Bruce Holmer and Barry Pangrle, “Hardware/Software Codesign Using Automated Instruction Set Design & Processor Synthesis,” Proc. of Hardware/Software Codesign Workshop, 1993 [16] Hironobu Kitabatake and Katsuhiko Shirai, “Functional Design of a Special Purpose Processor Based on High Level Specification Description,” IEICE Trans. Fundamentals, Vol. E75-A, No. 10, Oct. 1992 [17] M. Corazao, et al., “Instruction Set Mapping for Performance Optimization,” Proc. of ICCAD, Nov. 1993 [18] Wei-Kai Cheng and Youn-Long Lin, “Code Generation for a DSP Processor,” Proc. of Int’l Symposium on High Level Synthesis, May 1994 [19] Peter Van Roy and Alvin Despain, “HIgh-performance Logic Programming with the Aquarius Prolog Compiler,” Computer, 25(1):54-68, January 1992 ICCAD94, Pages 397-402 Register Assignment through Resource Classification for ASIP Microcode Generation Clifford Liem, Trevor May, Pierre Paulin Bell-Northern Research Ltd., Ottawa, ON, Canada E-mail: cbl@bnr.ca tmay@bnr.ca paulin@bnr.ca Abstract Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design specifications, accomodation of design errors, and product evolution. However, code generation for ASIPs is a complex problem and new techniques are needed for its success. The register assignment task can be a critical phase, since often in ASIPs, the number and functionality of available registers is limited, as the designer has opted for simplicity, speed, and low area. Intelligent use of register files is critical to the program execution time, program memory usage and data memory usage. This paper describes a methodology utilizing register classes as a basis for assignment for a particular style of ASIP architectures. The approach gives preference to special purpose registers which are the scarce resources. This naturally leads to the objectives of high speed and low program memory usage. The approach has been implemented in a system called CodeSyn [1] and used on custom ASIP architectures. References [1] P. Paulin, C. Liem, T. May, S. Sutarwala, “DSP Design Tool Requirements for Embedded Systems: A Telecommunications Industrial Perspective”, to appear in Journal of VLSI Signal Processing (special isssue on synthesis for real-time DSP), Kluwer Academic Publishers, 1994. [2] H. Feuerhahn, “Data-Flow Driven Resource Allocation in a Retargetable Microde Compiler”, 21st Int. Symposium on Microarchitecture, 1988, pp. 105-107. [3] R. Stallman, “Using and Porting GNU CC, version 2.4”, distributed with GNU gcc, Free Software Foundation, June 1993 [4] C. Liem, T. May, P. Paulin, “Instruction-Set Matching and Selection for DSP and ASIP Code Generation”, European Design & Test Conf. Feb 1994, pp. 31-37. [5] S. Sutarwala, P. Paulin, Y. Kumar, “Insulin: An Instruction Set Simulation Environment”, Proc. of CHDL-93, April 1993, pp. 355-362. [6] J. Rabaey, H. DeMan, J. Vanhoof, G. Goossens, and F. Catthoor, “CATHEDRAL-II: a sysnthesis system for multiprocessor DSP systems”, in D. Gajski (ed.), Silicon Compilation, Addison-Wesley, 1988, pp. 311-360. [7] P. Marwedel, “A new synthesis algorithm for the MIMOLA software system”, 23rd Design Automation Conf., June 1986, pp. 271-277. [8] C. Gebotys, M. Elmasry, “Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis”, 28th Design Automation Conf., June 1991, San Francisco, pp. 2-7. [9] K. Kucukcakar, A. Parker, “Data path design tradeoffs using MABAL”, the International Workshop on Highlevel Synthesis, Kennebunkport, ME, October 1989. [10] G.J. Chaitin, “Register Allocation and Spilling via Graph Coloring”, ACM Sigplan Notices, 17, pp. 98-105. [11] L.J. Hendren, G.R. Gao, E.R. Altman, C. Mukerji, “A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs”, Int. Conf. on Compiler Construction, 1992. [12] F.J. Kurdahi, A.C. Parker, “REAL: A Program for Register Allocation”, 24th Design Automation Conf., 1987, pp. 210-215. [13] F. Depuydt, “Register Optimization and Scheduling for Real-Time Digital Signal Processing Architectures”, Ph. D. thesis, Katholieke Universiteit Leuven, Nov. 1993. [14] D. Lanneer, M. Cornero, G. Goossens, H. DeMan, “Data Routing: a Paradigm for Efficient Data-path Synthesis and Code Generation”, Int. High-Level Synthesis Symposium, May 1994, pp. 17-22. [15] F. Franssen, L. Nachtergaele, H. Samsom, F. Catthoor, H. De Man, “Control flow optimizatioin for fast system simulation and storage minimization”, Eur. Design and Test Conf., 1994, pp. 20-24. [16] W. Verhaegh, P. Lippens, E. Aarts, J. Korst, J. van Meerbergen, A. van der Werf, “Modelling Periodicity by PHIDEO Streams”, Int. Workshop on High-Level Synthesis, 1992. ICCAD94, Pages 404-411 Efficient Small-Signal Circuit Analysis and Sensitivity Computations with the PVL Algorithm R. W. Freund, P. Feldmann AT&T Bell Laboratories, Murray Hill, NJ 07974-0636 Abstract We describe the application of the PVL algorithm to the small-signal analysis of circuits, including sensitivity computations. The PVL algorithm is based on the efficient computation of the Padé approximation of the network transfer function via the Lanczos process. The numerical stability of the algorithm permits the accurate computation of the Padé approximation over any given frequency range. We extend the algorithm to compute sensitivities of network transfer functions, their poles, and zeros, with respect to arbitrary circuit parameters, with minimal additional computational cost, and we present numerical examples. References [1] P. Feldmann and R.W. Freund, “Efficient linear circuit analysis by Padé approximation via the Lanczos process," in Proc. Euro-DAC, Sep. 1994. [2] C. Lanczos, “An iteration method for the solution of the eigenvalue problem of linear differential and integral operators," J. Res. Nat. Bur. Standards, vol. 45, pp. 255-282, 1950. [3] A.E. Ruehli, “Equivalent circuit models for three-dimensional multiconductor systems," IEEE Trans. Voltage gain sensitivity (dB) Microwave Theory and Tech., vol. 22, pp. 216-221, Mar. 1974. [4] J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design. New York, N.Y.: Van Nostrand Reinhold, 1983. [5] G.A. Baker, Jr. and P. Graves-Morris, Padé Approximants, Part I: Basic Theory. Reading, MA: Addison-Wesley, 1981. [6] L.T. Pillage and R.A. Rohrer, “Asymptotic wave-form evaluation for timing analysis," IEEE Trans. ComputerAided Design, vol. 9, pp. 352-366, Apr. 1990. [7] V. Raghavan, R.A. Rohrer, L.T. Pillage, J.Y. Lee, J.E. Bracken, and M.M. Alaybeyi, “AWE-inspired," in Proc. IEEE Custom Integrated Circuits Conference, May 1993. [8] W.B. Gragg, “Matrix interpretations and applications of the continued fraction algorithm," Rocky Mountain J. Math., vol. 4, pp. 213-225, 1974. [9] R.W. Freund, M.H. Gutknecht, and N.M. Nachtigal, “An implementation of the look-ahead Lanczos algorithm for non-Hermitian matrices," SIAM J. Sci. Comput., vol. 14, pp. 137-158, Jan. 1993. [10] J.Y. Lee, X. Huang, and R.A. Rohrer, “Pole and zero sensitivity calculation in asymptotic waveform evaluation," IEEE Trans. Computer-Aided Design, vol. 11, pp. 586-597, May, 1992. [11] J. Stoer and R. Bulirsch, Introduction to Numerical Analysis, Second Edition. New York, N.Y.: SpringerVerlag, 1993. [12] T. Kato, A Short Introduction to Perturbation Theory for Linear Operators. New York, N.Y.: Springer-Verlag, 1982. [13] A. Griewank and G.F. Corliss (Eds.), Automatic Differentiation of Algorithms: Theory, Implementation, and Application. Philadelphia, PA: SIAM, 1991. [14] P. Feldmann, R. Melville, and S. Moinian. “Automatic differentiation in circuit simulation and device modeling," in Tech. Dig. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 1992. ICCAD94, Pages 412-417 Capturing Time-of-Flight Delay for Transient Analysis Based on Scattering Parameter Macromodel Haifang Liao and Wayne Wei-Ming Dai Computer Engineering, University of California, Santa Cruz, CA 95064 Abstract The delay associated with transmission line networks consists of the exponentially charging time and a pure propagation delay. This propagation delay, so called time-of-flight delay, is particularly evident in long lines. When the time-of-flight is comparable to the input rise-time, it is difficult to capture the time-of-flight with a finite sum of exponentials. Therefore the time-offlight must be captured explicitly from the transfer function of the circuit. In this paper, we give a precise definition of the time-of-flight together with some basic properties, and present an efficient method to capture the time-of-flight for general interconnect networks. Based on our scattering parameter macromodel, we can easily capture the time-of-flight during the network reduction while using lower order model to evaluate the charging delay. By capturing the timeof-flight delay, the accuracy of system responses can be greatly improved without significantly increasing computing time. References [1] N. Balabanian, T. A. Bickart, Electrical Network Theory, ch. 6, Malabar, Florida: Robert E. Krieger, 1985. [2] J. E. Bracken, V. Raghavan, and R. A. Rohrer, “Simulating Distributed Elements with Asymptotic Waveform Evaluation,” IEEE MTT-S International Microwave Symposium Digest, pp. 1337-1340, 1992. [3] J. E. Bracken, V. Raghavan, and R. A. Rohrer, “Extension of the Asymptotic Waveform Evaluation Technique with the Method of Characteristics,” Technical Digest of the IEEE International Conference on Computer-Aided Design, pp. 71-75, Nov. 1992. [4] F. Y. Chang, “Waveform Relaxation Analysis of Nonuniform Lossy Transmission Lines Characterized with Frequency-Dependent Parameters,” IEEE Trans. on Circuits and Systems, vol. CAS-38, pp. 1484-1500, Dec. 1991. [5] F. Y. Chang, “Transient Simulation of Nonuniform Coupled Lossy Transmission Lines Characterized with Frequency-Dependent Parameters, Part II: Discrete-Time Analysis,” IEEE Trans. on Circuits and Systems, vol. CAS-39, pp. 907-927, Nov. 1992. [6] J. Dobrowolski, Introduction to Computer Methods for Microwave Circuit Analysis and Design, Artech House, 1991. [7] W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifier,” J. Applied Physics, 19(1), 1948. [8] B. Johnson, T. Quarles, A. R. Newton, D. O. Pederson and A. Sangiovanni-Vincentelli, “SPICE3 Version 3e User’s Manual,” University of California, Berkeley, April 1991. [9] S. Y. Kim, N. Gopal and L. T. Pillage, “Finite-Pole Macromodels of Transmission Lines for Circuit Simulation,” Proceedings of the 1993 Custom Integrated Circuits Conference. [10] H. Liao, W. Dai, R. Wang, and F. Y. Chang, “S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function,” Proceedings of the 30th ACM/IEEE Design Automation Conference, pp. 726-731, June 1993. [11] H. Liao and W. Dai, “Transient Analysis of Interconnects with Nonlinear Driver Using Mixed exponential Function Approximation,” Technique report of University of California at Santa Cruz, UCSC-CRL-93-44, Oct. 1993. [12] H. Liao and W. Dai, “Capturing Time-of-Flight Delay for Transient Analysis Based on Scattering Parameter Macromodel,” Technique report of University of California at Santa Cruz, UCSC-CRL-94-11, April. 1994. [13] S. Lin, and E. S. Kuh, “Transient Simulation of Lossy Interconnects Based on the Recursive Convolution Formulation,” IEEE Trans. on Circuits and Systems, vol. CAS-39, pp. 879-892, Nov. 1992. [14] L. T. Pillage, and R. A. Rohrer, “Asymptotic Waveform Evaluation for Timing Analysis,” IEEE Trans. on CAD, vol. CAD-9, April 1990. [15] J. White, L. Pillage, and J. Cohn, “Computer-Aided Analysis and Design of Interconnect” Tutorial of IEEE/ACM International Conference on Computer-Aided Design, Nov. 1993. ICCAD94, Pages 418-425 RC Interconnect Synthesis—A Moment Fitting Approach Noel Menezes, Satyamurthy Pullela, Florentin Dartu, and Lawrence T. Pillage Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas 78712-1084 Abstract Presently, delays due to the physical interconnect between logic gates account for large portions of the overall path delays. For this reason, synthesis of the logic gate fanout structure is of paramount importance during performance optimization. This paper presents a methodology for on-chip RC interconnect synthesis. Moment sensitivities are used to vary the wire widths of the branches in an RC interconnect tree to achieve performance targets. In this paper, signal slopes and delays at critical fanout nodes are the targets, and the impact on total metal area is considered. An procedure for computing the exact moment sensitivities in an RC tree is described. References [1] J. Rubenstein, P. Penfield, Jr., and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Trans. ComputerAided Design, vol. CAD-2, pp. 202-211, July 1983. [2] W. C. Elmore, “The transient response of damped linear networks with particular regard to wide-band amplifiers,” J. Applied Physics, vol. 19, no. 1, pp. 55-63, Jan. 1948. [3] S. W. Director, and R. Rohrer, “The generalized adjoint network and network sensitivities,” IEEE Trans. Circuit Theory, vol. 16, pp. 318 - 323, August 1969. [4] J. Y. Lee, X Huang, and R. Rohrer, “Pole and zero sensitivity calculation in asymptotic waveform evaluation,” IEEE Trans. Computer-Aided Design, vol. 11, no. 5, pp. 586 - 597, May 1992. [5] A. Balivada, D. R. Holberg, and L. T. Pillage, “Calculation and application of time-domain waveform sensitivities in asymptotic waveform evaluation,” Proc. IEEE Custom Integrated Circuits Conference, May 1991. [6] D. W. Marquardt, “An algorithm for least-squares estimation of nonlinear parameters,” J. Soc. Indust. App. Math., vol. 11, no. 2, pp. 431 - 441, June 1963. [7] J. Cong, and K.-S. Leung, “Optimal wiresizing under the distributed Elmore delay model,” Proc. of the Intl. Conf. on Computer-Aided Design, November 1993. [8] J. K. Ousterhout, “A switch-level timing verifier for digital MOS VLSI,” IEEE Trans. Computer-Aided Design, vol. CAD-4, no. 3, pp. 336-349, July 1985. [9] P. R. O’Brien and T. L. Savarino, “Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation,” Proc. IEEE Intl. Conf. Computer-Aided Design, November 1989. [10] C. L. Ratzlaff, N. Gopal, and L. T. Pillage, “RICE: Rapid Interconnect Circuit Evaluator,” Proc. 28th Design Automation Conference, June 1991. [11] L. T. Pillage and R. A. Rohrer, “Asymptotic waveform evaluation for timing analysis,” IEEE Trans. ComputerAided Design, vol. 9, no. 4, pp. 352-366, April 1990. [12] C. L. Ratzlaff, S. Pullela, and L. T. Pillage, “Modeling the RC-interconnect effects in a hierarchical timing analyzer,” IEEE Custom Integrated Circuits Conference, May 1992. [13] N. Gopal and L. T. Pillage, “Evaluation of on-chip interconnect using moment matching,” Proc. of the Intl. Conf. on Computer-Aided Design, November 1991. [14] F. Dartu, N. Menezes, J. Qian, and L. T. Pillage, “A gate-delay model for high-speed CMOS circuits,” Proc. 31st Design Automation Conference, June 1994. [15] S. Pullela, N. Menezes, and L. T. Pillage, “Reliable nonzero skew clock trees using wire-width optimization,” Proc. 30th Design Automation Conference, June 1993. [16] R. S. Tsay, “An exact zero-skew clock routing algorithm,” IEEE Trans. Computer-Aided Design, vol. 12, no. 2, pp. 242-249, February 1993. [17] S. S. Sapatnekar, “RC interconnect optimization under the Elmore delay model,” Proc. 31st Design Automation Conference, June 1994. ICCAD94, Pages 428-431 Adaptive Cut Line Selection in Min-cut Placement for Large Scale Sea-of-gates Arrays K. Takahashi*, K. Nakajima**, M. Terai*, K. Sato* *System LSI Laboratory, Mitsubishi Electric Corp., Itami, Hyogo 664 Japan **Electrical Department, Meryland Univ, College Park, Meryland 20742 Abstract We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms used a fixed cut line sequence that is determined before min-cut partitioning is performed. In our approach, we adaptively select a next partitioning pattern based on the current parameter value; we then perform the corresponding min-cut partitionings and measure a new parameter value. We repeat this process until all cut lines are processed. As a parameter, we introduce a new global objective function based on wire congestions on cut lines. We establish a close relation between this function and cut line sequences. This relation is used to develop an innovative method of adaptively determining a cut line sequence so as to minimize this global function. With this adaptive selection of cut lines along with a new cluster-based mincut partitioning technique, our algorithm can produce, in a short time and at a low cost, final placement results that achieve the 100% completion of wiring on chips of fixed sizes. This has led to its successful production use, having generated more than 400 CMOS sea-of-gates array chips. References [1] M. A. Breuer, “Min-cut placement," Jour. Design and Fault-Tolerant Computing, vol. 1, no. 4, pp. 343-362, Aug. 1977. [2] M. Igusa, M. Beardsiee, and A. Sangiovanni-Vincentelli, “ORCA: A sea-of-gates place and route system," Proc. 26th DAC, June 1989, pp. 122-127. [3] S. Murai, H. Tsuji, M. Kakinuma, K. Sakaguchi, and C. Tanaka, “A hierarchical placement procedure with a simple blocking scheme," Proc. 16th DAC, June 1979, pp. 18-23. [4] C. Ng, S. Ashtaputre, E. Chambers, K. Do, S. Hui, R. Mody, and D. Wong, “A hierarchical oor-planning, placement, and routing tool for sea-of-gates design," Proc. CICC, May 1989, paper no. 3.3. [5] T. -K. Ng, J. Oldfield, and V. Pitchumani, “Improvements of a mincut partition algorithm," Proc. IEEE ICCAD, Nov. 1987, pp. 470-473. [6] T. Payne, R. Wells, and W. Gundel, "A study of automatic placement strategies for very large gate array designs," Proc. IEEE IC-CAD, Nov. 1987, pp. 194-197. [7] H. Shiraishi and F. Hirose, “Efficient placement and routing for master-slice LSI," Proc. 17th DAC, June 1980, pp. 458-464. ICCAD94, Pages 432-435 Folding A Stack Of Equal Width Components Venkat Thanvantri, Sartaj Sahni Department of CIS, University of Florida, Gainesville, FL-32611 Abstract We consider two versions of the problem of folding a stack of equal width components. In both versions, when a stack is folded, a routing penalty is incurred at the fold. In one version, the height of the folded layout is given and we are to minimize width. In the other, the width of the folded layout is given and its height is to be minimized. References [1] G. N. Frederickson, and D. B. Johnson, “Finding kth paths and p-centers by generating and searching good data structures", Journal of Algorithms, 4:61-80, 1983. [2] G. N. Frederickson, and D. B. Johnson, “Generalized selection and ranking: sorted matrices", SIAM Journal on computing, 13:14-30, 1984. [3] G. N. Frederickson, “Optimal algorithms for tree partitioning", Proc. 2nd ACM-SIAM Symposium on Discrete Algorithms, San Francisco, California (Jan. 1991), pp. 168-177 [4] G. N. Frederickson, “Optimal parametric search algorithms in trees I: tree partitioning", Purdue University, Technical Report CSD-TR-1029, 1992. [5] E. Horowitz, and S. Sahni, “Fundamentals of Computer Algorithms", Computer Science Press, Maryland, 1978. [6] L. Larmore, D. Gajski and A. Wu, “Layout Placement for Sliced Architecture", University of California, Irvine, Technical Report, 1990. [7] D. Paik, S. Sahni, “Optimal folding of bit sliced stacks", IEEE Trans. on CAD of Integrated Circuits and Systems, 12, 11, Nov. 1993, 1679-1685. [8] E. Shragowitz, L. Lin, S. Sahni, “Models and algorithms for structured layout", Computer Aided Design, Butterworth & Co, 20, 5, 1988, 263-271. [9] E. Shragowitz, J. Lee, and S. Sahni, “Placer-router for sea-of-gates design style", in Progress in computer aided VLSI design, Ed. G.Zobrist, Ablex Publishing, Vol 2, 1990, 43-92. [10] V. Thanvantri, and S. Sahni, “Folding a stack of equal width components", University of Florida, Technical Report 94-011, 1994. [11] A. Wu, and D. Gajski, “Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists", Proc. of International Conference on Computer Aided Design, November 1990, pp. 144-147. ICCAD94, Pages 436-440 Area Minimization for Hierarchical Floorplans Peichen Pan*, Weiping Shi**, and C. L. Liu* *Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801 **Department of Computer Science, University of North Texas, Denton, TX 76203 Abstract Two results are presented in this paper. First we settle the open problem on the complexity of the area minimization problem for hierarchical oorplans by showing it to be NP-complete. We then present a pseudo-polynomial area minimization algorithm for hierarchical floorplans of order-5. The algorithm is based on a new algorithm for determining the set of nonredundant realizations of a wheel. The new algorithm for wheels has time cost O(k2 log k) and space cost O(k2) if each of the (five) blocks in a wheel has at most k realizations -- a reduction by a factor of k in both costs in comparison with previous algorithms. The area minimization algorithm was implemented. Our experimental results show that the algorithm is indeed very fast. References [1] C.-H. Chen and I.G. Tollis, “Area optimization of spiral oorplans," Technical Report, The University of Texas at Dallas, 1992. [2] K. Chong and S. Sahni, “Optimal realizations of floor-plans," in IEEE Trans. on Computer-Aided Design, vol. CAD-12, no. 6, pp. 793-801, 1993. [3] W.-M. Dai and E.S. Kuh, “Simultaneous oor planning and global routing for hierarchical building block layout," in IEEE Trans. on Computer-Aided Design, vol. CAD-6, no. 5, pp. 828-837, 1987. [4] M. L. Fredman, “How good is the informationtheory bound in sorting?," in Theoretical Computer Science 1, pp. 355-361, 1976. [5] M. R. Garey and D. S. Johnson, Computers and Intractability, A Guide to the Theory of NP-completeness. Freeman, San Francisco, 1979. [6] T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. John Wiley & Sons, New York, 1990. [7] T. Lengauer and R. Muller, “Robust and accurate hierarchical floorplanning with integrated global wiring," in IEEE Trans. on Computer-Aided Design, vol. CAD-12, no. 6, pp. 802-809, 1993. [8] R.H.J.M. Otten, “Automatic floorplan design," in Proc. 19th ACM/IEEE Design Automation Conf., 1982, pp. 261-267. [9] P. Pan and C. L. Liu, “Area minimization for general floor-plans," in Digest Int'l. Conf. on Computer-Aided Design, 1992, pp. 606-609. [10] L. Stockmeyer, “Optimal orientations of cells in slicing floorplan designs," in Info. and Control, vol. 59, pp. 91101, 1983. [11] K. J. Supowit and E. A. Slutz, “Placement algorithms for custom VLSI," in Computer Aided Design, vol. 16, no. 1, pp. 45-50, 1984. [12] Ting-Chi Wang and D.F. Wong, “Optimal floorplan area optimization," in IEEE Trans. on Computer-Aided Design, vol. CAD-11, no. 8, pp. 992-1002, 1992. [13] S. Wimer, I. Koren, and I. Cederbaum, “Optimal aspect ratios of building blocks in VLSI," in IEEE Trans. on Computer-Aided Design, vol. 8, no 2, pp. 139-145, 1989. [14] D.F. Wong and P.S. Sakhamuri, “Efficient floorplan area optimization," in Proc. 26th ACM/IEEE Design Automation Conf., 1989, pp. 586-589. [15] K. H. Yeap and M. Sarrafzadeh, “An integrated algorithm for optimal oorplan sizing and enumeration," in European Design Automation Conf., 1993, pp. 29-33. [16] G. Zimmermann, “A new area and shape function estimation technique for VLSI layouts," in Proc. 25th ACM/IEEE Design Automation Conf., 1988, pp. 60-65. ICCAD94, Pages 442-449 Multi-level Synthesis for Safe Replaceability Carl Pixley, Motorola Inc., MD OE321, 6501 Wm Cannon DriveWest, Austin, TX 78735 Vigyan Singhal, Adnan Aziz, Robert K. Brayton Dept. of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720 Abstract We describe the condition that a sequential digital design is a safe replacement for an existing design without making any assumptions about a known initial state of the design or about its environment. We formulate a safe replacement condition which guarantees that if an original design is replaced by a new design, the interacting environment cannot detect the change by observing the input-output behavior of the new design; conversely, if a replacement design does not satisfy our condition an environment can potentially detect the replacement (in this sense the replacement is potentially unsafe). Our condition allows simplification of the state transition diagram of an original design. We use the safe replacement condition to derive a sequential resynthesis method for area reduction of gate-level designs. We have implemented our resynthesis algorithm and we report experimental results. References [1] B. Lin,H. J. Touati, andA. R. Newton, “Don’t CareMinimization ofMulti-level Sequential Logic Networks,” in Proc. Intl. Conf. on Computer-Aided Design, pp. 414–417,Nov. 1990. [2] C. Berthet, O. Coudert, and J. C. Madre, “New Ideas on Symbolic Manipulation of Finite State Machines,” in Proc. Intl. Conf. on Computer Design, Oct. 1990. [3] H. Cho, G. D. Hachtel, and F. Somenzi, “Redundancy Identification and Removal Based on Implicit State Enumeration,” in Proc. Intl. Conf. on Computer Design, pp. 77–80,Oct. 1991. [4] G. Berry and H. J. Touati, “Optimized Controller Synthesis Using Esterel,” in Workshop Notes of Intl. Workshop on Logic Synthesis, (TahoeCity, CA), May 1993. [5] C. Pixley, “A Theoryand Implementationof SequentialHardwareEquivalence,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 1469–1494,Dec. 1992. [6] K.-T. Cheng, “Redundancy Removal for Sequential Circuits Without Reset States,” IEEE Trans. ComputerAided Design, vol. 12, pp. 13–24, Jan. 1993. [7] S. Malik, E. M. Sentovich, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Retiming and Resynthesis: Optimization of SequentialNetworkswith Combinational Techniques,” IEEE Trans. Computer-AidedDesign, vol. 10, pp. 74–84, Jan. 1991. [8] M. Damiani and G. De Micheli, “Synthesis and Optimization of Synchronous Logic Circuits from RecurrenceEquations,” in Proc. EuropeanConf. on Design Automation, pp. 226–231,Mar. 1992. [9] L. Entrena and K.-T. Cheng, “Sequential Logic Optimization by Redundancy Addition and Removal,” in Proc. Intl. Conf. on Computer-Aided Design, pp. 310–315,Nov. 1993. [10] J. Hartmanis and R. E. Stearns, Algebraic Structure Theory of SequentialMachines. Intl. Series in Applied Mathematics, Englewood Cliffs, N.J.: Prentice-Hall, 1966. [11] R. Rudell, Synopsys, Inc.. Personal communication,Mar. 1994. [12] C. Pixley, V. Singhal, A. Aziz, and R. K. Brayton, “Multi-level Synthesis for Safe Replaceability,” Tech.Rep. UCB/ERL M94/31,ElectronicsResearch Lab, Univ. of California, Berkeley, CA 94720, Apr. 1994. [13] V. Singhal and C. Pixley, “The Verification Problemfor Safe Replaceability,” in Proc. of the Conf. on Computer-Aided Verification (D. L. Dill, ed.), vol. 818 of Lecture Notes in Computer Science, pp. 311– 323,Springer-Verlag, June 1994. [14] H. Savoj and R. K. Brayton, “Observability Relations and Observability Don’t Cares,” in Proc. Intl.Conf.on Computer-AidedDesign, pp. 518–521,Nov. 1991. [15] E. M. Sentovich,V. Singhal, and R. K. Brayton, “Multiple Boolean Relations,” in Workshop Notes of the Intl. Workshop on Logic Synthesis, (Tahoe City, CA), May 1993. [16] S.-W. Jeong, Binary Decision Diagrams and their Applications to Implicit Enumeration Techniques in Logic Synthesis. PhD thesis, Department of Electrical and Computer Engineering,University of Colorado,Boulder, CO 80309, 1992. [17] R. K. Brayton, G. D. Hachtel, and A. L. Sangiovanni-Vincentelli, “Multilevel Logic Synthesis,” Proceedings of the IEEE, vol. 78, pp. 264–300, Feb. 1990. [18] R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984. [19] H. Savoj, R. K. Brayton, and H. Touati, “ExtractingLocal Don’t Cares for Network Optimization,” in Proc. Intl. Conf. on Computer-Aided Design, pp. 514–517, Nov. 1991. [20] E. Cerny and M. A. Marin, “An Approach to Unified Methodology of Combinational Switching Circuits,” IEEE Trans. Computers, vol. 27, no. 8, 1977. [21] E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Sequential Circuit Design Using Synthesis and Optimization,” in Proc. Intl. Conf. on Computer Design, pp. 328– 333,Oct. 1992. ICCAD94, Pages 450-457 Iterative Algorithms for Formal Verification of Embedded Real-Time Systems Felice Balarin, Alberto L. Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 Abstract Most embedded real-time systems consists of many concurrent components operating at significantly different speeds. Thus, an algorithm for formal verification of such systems must efficiently deal with a large number of states and large ratios of timing constants. We present such an algorithm based on timed automata, a model where a finite state system is augmented with time measuring devices called timers. We also present a semi-decision procedure for an extended model where timers can be decremented. This extension allows describing behaviors that are not expressible by timed automata, for example interrupts in a real-time operating system. References [1] R. Alur and D. L. Dill. Automata for modeling real-time systems. In Proceeding of ICALP'90. Springer-Verlag, 1990. LNCS vol. 443. [2] R. Alur et al. An implementation of three algorithms for timing verification based on automata emptiness. In Proceedings of IEEE Real-time Systems Symposium, 1992. [3] R. Alur et al. Timing verification by successive approximation. In Proceedings of CAV'92. Springer-Verlag, 1993. LNCS vol. 663. [4] A. Aziz et al. HSIS: A BDD-based environment for formal verification. In Proceedings of the 31th ACM/IEEE Design Automation Conference, 1994. [5] F. Balarin. Iterative Methods for Formal Verification of Discrete Event Systems. PhD thesis, University of California Berkeley, 1994. in preparation. [6] F. Balarin et al. Formal verification of the PATHO real-time operating system. In Proceedings of 33th Conference on Decision and Control, 1994. [7] F. Balarin and A. L. Sangiovanni-Vincentelli. An iterative approach to verification of real-time systems. Formal Methods in System Design: An International Journal, 1994. to be published. [8] T. A. Henzinger et al. Symbolic model-checking for real-time systems. In Proceedings of 7th LICS. IEEE Computer Society Press, 1992. [9] J. Hopcroft and J. Ullman. Introduction to Automata Theory, languages and Computation. Addison Wesley, 1979. [10] J. McManis and P. Varaiya. Suspension automata: A decidable class of hybrid automata. In Proceedings of CAV'94. Springer-Verlag, 1994. LNCS vol. 818. [11] R. E. Tarjan. Data Structures and Network Algorithms. Society for Industrial and Applied Mathematics, Philadelphia, PA, 1983. ICCAD94, Pages 458-465 Incremental Formal Design Verification Gitanjali M. Swamy, Robert K. Brayton Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA 94720 Abstract Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (properties or requirements), which it has to meet. If this check fails, language containment returns a subset of ‘fair’ states involved in behavior that the system exhibits but the specification does not. Current techniques for language containment do not take advantage of the fact that the process of design is incremental; namely that the designer repeatedly modifies and re-verifies his/her design. This results in unnecessary and cumbersome computation. We present a method, which successivelymodifies the latest result of verification each time the design is modified. Our incremental algorithm translates changes made by the designer to an addition or subtraction of edges, states or constraints (on acceptable behavior) from the transition behavior or specification of the problem. Next, these changes are used to update the set of ‘fair’ states previously computed. This incremental algorithm is superior to the current techniques for language containment; a conclusion supported by the experimental results presented in this paper. References [1] H. Touati, R. K. Brayton, and R. P. Kurshan, “Checking Language Containment using BDDs,” in Proc. of Intl. Workshop on FormalMethods in VLSI Design, (Miami, FL), Jan. 1990. [2] R. Hojati, T. R. Shiple, R. K. Brayton, and R. P. Kurshan, “A Unified Environment for LanguageContainment and Fair CTL Model Checking,” in Proc. of the Design Automation Conf., (Dallas, Texas), pp. 475–481, June 1993. [3] G. M. Swamy and R. K. Brayton, “Incremental Formal Design Verification,” Tech. Rep. UCB/ERL M94/, Electronics Research Lab, Univ. of California, Berkeley, CA 94720, 1994. [4] R. Bryant, “Graph-based Algorithms for Boolean Function Manipulation,” IEEE Trans. Computers, vol. C-35, pp. 677–691, Aug. 1986. [5] H. Touati, H. Savoj, B. Lin, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Implicit State Enumeration of Finite State Machines using BDD’s,” in Proc. Intl. Conf. on Computer-Aided Design, pp. 130–133,Nov. 1990. [6] R. S. Streett, “Propositional Dynamic Logic of Looping and Converse is Elementary Decidable,” Information and Control, vol. 54, pp. 121–141, 1982. [7] M. O. Rabin, Automata on Infinite Objects and Church’s Problem, vol. 13 of Regional Conf. Series in Mathematics. Providence, Rhode Island: American Mathematical Society, 1972. [8] E.A.Emerson, “Temporal andModalLogic,” inFormalModels and Semantics (J. van Leeuwen, ed.), vol. B of Handbook of Theoretical Computer Science, pp. 996–1072, Elsevier Science, 1990. [9] M. Y. Vardi and P. L. Wolper, “An Automata-Theoretic Approach to Program Verification,” in Proc. IEEE Symposium on Logic in Computer Science, pp. 332–334, 1986. [10] G. Ramalingam and T. Reps, “On the Computational Complexity of Incremental Algorithms,” Tech. Rep. TR 1033, University of Wisconsion, Madison, University of Wisconsion, Madison, 1991. [11] R.Hojati, V. Singhal, andR.K. Brayton, “Edge-Streett/Edge-Rabin Automata Environment for Formal Verification Using Language Containment,” Tech. Rep. UCB/ERL M94/12, Electronics Research Lab, Univ. of California, Berkeley, CA 94720, 1994. [12] R. Milner, Communication and Concurrency. New York: Prentice Hall, 1989. [13] R. B. et al., “HSIS: A BDD-Based Environment for Formal Verification,” in Proc. of the Design Automation Conf., pp. 454–459, June 1994. ICCAD94, Pages 468-473 Optimization of Critical Paths in Circuits with Level-Sensitive Latches Timothy M. Burks1 and Karem A. Sakallah2 1 2 Systems Technology and Architecture Division, IBM Corporation, Austin, TX Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI Abstract A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a sufficient set of constraints to ensure that, when all slacks are non-negative, the corresponding circuit will be free of late signal timing problems. Cycle stealing is directly permitted by the formulation. However, moderate restrictions may be necessary to ensure that the timing constraint graph is acyclic. Forcing the constraint graph to be acyclic allows a broad range of existing optimization algorithms to be easily extended to better optimize circuits with levelsensitive latches. We describe the extension of two such algorithms, both of which attempt to solve the problem of selecting parts from a library to minimize area subject to a cycle time constraint. References [1] K. Lockyer and J. Gordon, Critical Path Analysis and other Project Network Techniques, Pitman, 1991. [2] T. I. Kirkpatrick and N. R. Clark, “PERT as an Aid to Logic Design”, IBM Journal of Res. and Dev., vol. 10, no. 2, p. 135-141, March 1966. [3] R. B. Hitchcock, Sr., G. L. Smith, and D. D. Cheng, “Timing Analysis of Computer Hardware”, IBM Journal of Res. and Dev., vol. 26, no. 1, p. 100-105, January 1982. [4] Texas Instruments, TSC 700 Series 1-micron CMOS Standard Cells, SRSS035B-D3857, 1992. [5] J. P. Fishburn and A. E. Dunlop, “TILOS: A Posynomial Programming Approach to Transistor Sizing,” in ICCAD-85 Digest of Technical Papers, p. 326-328, 1985. [6] J. M. Shyu, A. Sangiovanni-Vincentelli, J. P. Fishburn, and A. E. Dunlop, “Optimization-Based Transistor Sizing,” IEEE Journal of Solid-State Circuits, 23(2), p. 400-409, April 1988. [7] S. Lin, M. Marek-Sadowska, and E. S. Kuh, “Delay and Area Optimization in Standard-Cell Design,” in Proc. Design Automation Conf., p. 349-352, 1990. [8] U. Hinsberger and R. Kolla, “A Cell-Based Approach to Performance Optimization of Fanout-Free Circuits,” IEEE Trans. on Computer-Aided Design, 11(10), p. 1317-1321, October 1992. [9] U. Hinsberger and R. Kolla, “Cell Based Performance Optimization of Combinational Circuits,” in Proc. European Conf. on Design Automation, p. 594-599, 1990. [10] K. A. Sakallah, T. N. Mudge, and O. A. Olukotun. checkTc and minTc: Timing Verification and Optimal Clocking of Synchronous Digital Circuits, in ICCAD-90 Digest of Technical Papers, p. 552-555, 1990. [11] T. G. Szymanski, “Computing Optimal Clock Schedules,” In Proc. Design Automation Conf., p. 399-404, 1992. [12] T. M. Burks, K. A. Sakallah, and T. N. Mudge, “Identification of Critical Paths in Circuits with Level-Sensitive Latches”, in ICCAD-92 Digest of Technical Papers, p. 137-141, 1992. [13] W. Chuang, S. S. Sapatnekar, and I. N. Hajj, “A Unified Algorithm for Gate Sizing and Clock Skew Optimization to Minimize Sequential Circuit Area,” in Proc. Design Automation Conf., p. 220-223, 1993. [14] R. M. Karp, “Reducability Among Combinatorial Problems,” in R.E. Miller and J. W. Thatcher (eds.), Complexity of Computer Computations, Plenum Press, New York, p. 85-103, 1972. [15] A. Ishii, C. E. Leiserson, and M. C. Papaefthymiou, “Optimizing Two-Phase Level-Clocked Circuitry,” in Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, p. 245-264, 1992. ICCAD94 Pages 474-480 Computing the Entire Active Area / Power Consumption versus Delay Trade–off Curve for Gate Sizing with a Piecewise Linear Simulator Michel R.C.M. Berkelaar 1,2, Pim H.W. Buurman2 and Jochen A.G. Jess2 1 IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, USA Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The Netherlands 2 Abstract The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost versus delay trade–off curve of a combinational logic circuit in an efficient way. Every point on the resulting curve is the global optimum of the corresponding gate sizing problem. The problem is solved by mapping it onto piecewise linear models in such a way, that a piecewise linear (circuit) simulator can do the job. It is shown that this setup is very efficient, and can produce trade–off curves for large circuits (thousands of gates) in a few minutes. Benchmark results for the entire set of MCNC ’91 two–level examples are given. Literature [1] BERKELAAR, M.R.C.M. and J.A.G. JESS, “Gate Sizing in MOS Digital Circuits with Linear Programming”, Proceedings of the European Design Automation Conference 1990, pp. 217–221. [2] BERKELAAR, M.R.C.M. and J.F.M. THEEUWEN, “Real Area–Power–Delay Trade–off in the EUCLID Logic Synthesis System”, Proceedings of the IEEE Custom Integrated Circuits Conference 1990, pp. 14.3.1–14.3.4. [3] BERKELAAR, M.R.C.M., “Area–Power–Delay Trade–off in Logic Synthesis”, Ph.D. Thesis Eindhoven University of Technology, Eindhoven, The Netherlands, 1992. [4] BRAYTON, R.K., R. RUDELL, A.L. SANGIOVANNI–VINCENTELLI and A. WANG, “MIS: A Multiple– Level Logic Optimization System”, IEEE Transactions on Computer–Aided Design of Integrated Circuits and Systems, Nov. 1987, Vol. CAD–6, pp. 1062–1081. [5] BUURMAN, H.W., “From Circuit to Signal: development of a piecewise linear simulator”, Ph.D. Thesis Eindhoven University of Technology, Eindhoven, The Netherlands, 1993. [6] FISHBURN, J.P. and A.E. DUNLOP, “TILOS: A Posynomial Programming Approach to Transistor Sizing”, Proceedings of the IEEE International Conference on Computer–Aided Design 1985, pp. 326–328. [7] GHOSH, A., S. DEVADAS, K. KEUTZER and J. WHITE, ‘‘Estimation of Average Switching Activity in Combinational and Sequential Circuits”, Proceedings of the 29th ACM/IEEE Design Automation Conference 1992, pp 253–259. [8] GLASSER, L.A. and L.P.J. HOYTE, “Delay and Power Optimization in VLSI Circuits”, Proceedings of the IEEE Design Automation Conference 1984, pp. 529–535. [9] HEDLUND, K.S., “Models and Algorithms for Transistor Sizing in MOS Circuits”, Proceedings of the IEEE International Conference on Computer Aided Design 1984, pp. 12–14. [10] KAO, W.H., “Algorithms for Automatic Transistor Sizing in CMOS Digital Circuits”, Proceedings of the 22nd Design Automation Conference 1985, pp. 781–784. [11] MARPLE, D., “Transistor Size Optimization in the Tailor Layout System”, Proceedings of the IEEE Design Automation Conference 1989, pp. 43–48. [12] MATSON, M.D., “Optimization of Digital MOS VLSI Circuits”, Proceedings of the Chapel Hill Conference on VLSI 1985, pp. 109–126. [13] NAJM, F.N., ‘‘Transition Density, a Stochastic Measure of Activity in Digital Circuits”, Proceedings of the 28th ACM/IEEE Design Automation Conference 1991, pp 644–649. [14] PANNE, C. VAN DE, “A Complementary Variant of Lemke’s Method for the Linear Complementarity Problem”, Mathematical Programming, 1974, Vol. 7, pp. 283–310. [15] RUEHLI, A.U., P.K. WOLFF and G. GOERTZEL, “Power and Timing Optimization of Large Digital Systems”, Proceedings of the IEEE International Symposium on Circuits And Systems 1976, pp. 402– 405. [16] SAPATNEKAR, S.S., V.B. RAO and P.M. VAIDYA, “A Convex Optimization Approach to Transistor Sizing for CMOS Circuits”, Proceedings of the IEEE International Conference on Computer Aided Design 1991, pp. 482– 485. [17] SAPATNEKAR, S.S., V.B. RAO, P.M. VAIDYA and S.M. KANG, ‘‘An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization”, IEEE Transactions on Computer–Aided Design of Integrated Circuits and Systems, Vol. 12, No. 11, November 1993, pp. 1621–1634. [18] SHYU, J., A. SANGIOVANNI–VINCENTELLI, J.P. FISHBURN, and A.E. DUNLOP, “Optimization–Based Transistor Sizing”, IEEE Journal of Solid–State Circuits, Vol. 23, No. 2, April 1988, pp. 400–409. [19] Yang, S., “Logic Synthesis and Optimization Benchmarks User Guide Version 3.0”, Report of the Microelectronics Center of North Carolina, 1991. ICCAD94, Pages 481-484 Dynamical Identification of Critical Paths for Iterative Gate Sizing How-Rern Lin and TingTing Hwang Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30043, R.O.C. Abstract Since only sensitizable paths contribute to the delay of a circuit, false paths must be excluded in optimizing the delay of the circuit. Just identifying false paths in the first place is not sufficient since during iterative optimization process, false paths may become sensitizable, and sensitizable paths false. In this paper, we examine cases for false path becoming sensitizable and sensitizable becoming false. Based on these conditions, we adopt a so-called loose sensitization criterion [ChD91] which is used to develop an algorithm for dynamically identification of sensitizable paths. By combining gate sizing and dynamically identification of sensitizable paths, an efficient performance optimization tool is developed. Results on a set of circuits from ISCAS benchmark set demonstrate that our tool is indeed very effective in reducing circuit delay with less number of gate sized as compared with other methods. References [BMG87] J. Benkoski, E.V. Meersch, L. Glaesen and H. De Man, “Efficient Algorithms for Solving the Fasle Path Problem in Timing Verification," Proc. ICCAD'87,pp. 44-47, Nov. 1987. [Bra87] R. K. Brayton, et al., “MIS: A multiple-level logic optimization system," IEEE Trans. on CAD, Vol. CAD6, pp. 1062-1081, Nov. 1987. [CDL91] H.C. Chen, H.C. Du and L.R. Liu, “Critical Path Selection for Performance Optimization," Proc. of 28th Design Automation Conf., pp.547-550, June 1991. [ChD91] H.C. Chen and H.C. Du, “Path Sensitization in Critical Path Problem," Proc. of ICCAD'91,pp. 208-211, Nov. 1991. [DKM91] S. Devadas, K. Keutzer and S. Malik, “Delay Computation in Combinational Logic Circuits: Theory and Algorithms," Proc. of ICCAD'91, pp. 176-179, Nov. 1991. [DYG89] H.C. Du, H.C. Yen and S. Ghanta, “On the General False Path Problem in Timing Analysis," Proc. of 26th Design Automation Conf., pp.555-560, June 1989. [HPS93] S.T. Huang, T.M. Parng and J.M. Shyu, “A New Method of Identifying Critical Paths for Performance Optimization," Proc. of EDAC-93, pp. 455-459, Feb. 1993. [JoF93] W.B. Jone and C.L. Fang, “Timing Optimization By Gate Resizing And Critical Path Identification," Proc. of 30th Design Automation Conf., pp. 135-140, June 1993. [McB89] P.C. McGeer and R.K. Brayton, “Efficient Algorithms for Computing the Longest Viable Path in a Combination Circuit," Proc. of 26th Design Automation Conf., pp. 561-567, June 1989. ICCAD94, Pages 486-490 Built-in Self-Test and Fault Diagnosis of Fully Differential Analogue Circuits S. Miry, V. Kolarik, M. Lubaszewskiz, C. Nielsen and B. Courtois INPG/TIMA Laboratory, 46, avenue Félix Viallet, 38031 Grenoble FRANCE Abstract An approach to the test and diagnosis of fully differential analogue circuits is described in this paper. The test approach is based on off-line monitoring via an analogue BIST observer the inputs of the operational amplifiers in the circuit. The analogue BIST can detect both hard and soft faults. Diagnosis resolution is improved by also monitoring the outputs of the operational amplifiers. Faulty components can then be located and the actual defective value of a faulty passive component determined. References [1] Y.P. Tsividis. R&D in analog circuits: Possibilities and needed support. In Proc. European Solid-State Circuits Conference, pages 1-15, Copenhaguen, 1992. [2] C.-L. Wey. Built-in self-test (BIST) structure for analog circuit fault diagnosis. IEEE Trans. on Instrumentation and Measurement, 39(3):517-521, June 1990. [3] M.J. Ohletz. Hybrid built-in self-test (HBIST) for mixed analog/digital integrated circuits. In 2nd European Test Conference, pages 307-316, 1991. [4] M. Slamani and B. Kaminska. T-BIST: A built-in self-test for analog circuits based on parameter translation. In Proc. Asian Test Symposium, pages 172-177, 1993. [5] P.R. Gray, B.A. Wooley, and R.W. Brodersen (Editors). Analog MOS Integrated Circuits, II. IEEE Press, 1989. [6] V. Kolarik, M. Lubaszewski, and B. Courtois. Towards self-checking mixed-signal integrated circuits. In European Solid-State Circuits Conference, pages 202-205, Seville, 1993. [7] V. Kolarik, M. Lubaszewski, and B. Courtois. Designing self-exercising analogue checkers. In Proc. VLSI Test Symposyum, pages 252-253, Cherry Hill, New Jersey, April 1994. ICCAD94, Pages 491-494 A New Built-In Self-Test Approach for Digital-to-Analog and Analog-to-Digital Converters Karim Arabi, Bozena Kaminska and Janusz Rzeszut Department of Electrical and Computer engineering, École Polytechnique de Montréal, P.O.Box 6079, Station Centre-Ville, Montréal, Québec, Canada H3C 3A7. Abstract This paper proposes a test approach and circuitry suitable for built-in self-test (BIST) of digitalto-analog (D/A) and analog-to-digital (A/D) converters. Offset, gain, linearity and differential linearity errors are tested without using test equipment. The proposed BIST structure decreases the test cost and test time. The BIST circuitry has been designed to D/A and A/D converters using CMOS 1.2 µm technology. By only a minor modification the test structure would be able to localize the fail situation. The small value of area overhead (AOH), the simplicity and efficiency of the proposed BIST architecture seem to be promising for manufacturing. References [1] B.G.Heriques and J.E.Francu, "High-Speed D/A Conversion with Linear Phase Sinx/x Compensation," ISCAS 1993, Vol. 2, pp. 1204-1207. [2] S.Max, "Fast, Accurate and Complete ADC Testing," Proc. IEEE ITC 1989, pp. 598-640. [3] L.Milor et al., "Optimal Test Set Design for Analog Circuits," Proc. IEEE ICCAD 1990, pp. 294-297. [4] J.R.Naylor, "Testing Digital/Analog and Analog/Digital Converters" IEEE Trans. on Circuits and Systems, Vol. CAS-25, No. 7. Jul. 1978, pp. 526-538. [5] M.Slamani and B.Kaminska, "Analog Circuit Fault Diagnosis Based on Sensitivity Computation and Functional testing," IEEE Design&Test of Computers, Mar. 1992, pp. 30-39. [6] M.Soma, "A Design-for-Test Methodology for Active Analog Filters," Proc. IEEE ITC 1990, pp. 183-192. [7] D.K.Su and B.A.Wooley, "A CMOS Oversampling D/A Converter with a Current-Mode Semidigital Reconstruction Filter," IEEE J. of Solid-State Circuits, Vol. 28, No. 12, Dec. 1993, pp. 1224-1233. [8] K.D.Wagner and T.W.Wiliams, "Design for Testability of Mixed Signal Integrated Circuits," Proc. IEEE ITC 1988, pp. 823-829. ICCAD94, Pages 495-498 Fault Detection and Input Stimulus Determination for the Testing of Analog Integrated Circuits Based on Power-Supply Current Monitoring Georges Gielen, Zhihua Wang, Willy Sansen Department of Electrical Engineering, Katholieke Universiteit Leuven, Kardinaal Mercierlaan 94, 3001 Heverlee, Belgium Abstract A new method for the testing and fault detection of analog integrated circuits is presented. Timedomain testing followed by spectral analysis of the power-supply current is used to detect both DC and AC faults. Spectral analysis is applied since the tolerances on the circuit parameters make a direct comparison of waveforms impossible. For the fault detection a probabilistic decision rule is proposed based on a multivariate statistical analysis. Since no extra testing pin is needed and the on-line calculation effort is small, the method can be used for wafer-probe testing as well as final production testing. In addition, a methodology for the selection of the input stimulus is presented that improves the testability. Examples demonstrate the efficiency and the effectiveness of the algorithms. References [1] P. Nigh, W. Maly, “Test generation for current testing,” IEEE Design and Testing of Computers, Vol. 7(2), pp. 26-38, February, 1990. [2] D. Camplin, I. Bell, G. Taylor, B. Bannister, “Can supply current monitoring be applied to the testing of analog as well as digital portion of mixed ASICs?,” proceedings European Design Automation Conference, pp. 538-542, 1992. [3] D. Papakostas, A. Hatzopoulos, “Analogue fault identification based on power supply current spectrum,” Electronics Letters, Vol. 29(1), pp. 118-119, 1993. [4] T. Anderson, “An introduction to multivariate statistical analysis,” John Wily & Sons,1958. [5] P. Banerjee, J. Abraham, “Fault characterization of VLSI MOS circuit,” proceedings IEEE International Conference on Circuits and Computers, pp. 546-568, 1982. [6] B. Epstein, M. Czigler, S. Miller, “Faults detection and classification in linear integrated circuits: an application of discrimination analysis and hypothesis testing,” IEEE Transactions on Computer-Aided Design, CAD-12(1), pp. 102-113, 1993. ICCAD94, Pages 500-507 An Enhanced Flow Model for Constraint Handling in Hierarchical Multi-View Design Environments Pieter van der Wolf, Olav ten Bosch and Alfred van der Hoeven Delft University of Technology, Department of Electrical Engineering / DIMES, Mekelweg 4, 2628 CD Delft, The Netherlands Abstract In this paper we present an enhanced design flow model that increases the capabilities of a CAD framework to support design activities on hierarchical multi-view design descriptions. This flow model offers new constructs for the configuration of complex design constraints in terms of conditions on the hierarchical multi-view structure of a design. The design flow management system enforces these constraints and uses them to inform the designer more effectively about the validity of verification results and the executability of tools. This helps to make the design process less error prone and to improve productivity. Our solution is original in that we introduce the notions of design hierarchy and equivalence in a design flow model. We thereby bridge a gap between the areas of data management and design flow management. Strong points of our solution are its simplicity and the seamless integration with existing flow management concepts. References 1. S. Kleinfeldt, M. Guiney, J. Miller, and M. Barnes, ‘‘Design Methodology Management’’, Proceedings of the IEEE 82(2) pp. 231-250 (Feb 1994). 2. P. van den Hamer and M.A. Treffers, ‘‘A Data Flow Based Architecture for CAD Frameworks’’, Proc. ICCAD 90, pp. 482-485 (1990). 3. J.B. Brockman and S.W. Director, ‘‘The Hercules CAD Task Management System’’, Proc. IEEE ICCAD - 91, pp. 254-257 (1991). 4. K.O. ten Bosch, P. Bingley, and P. van der Wolf, ‘‘Design Flow Management in the NELSIS CAD Framework’’, Proc. 28th ACM/IEEE Design Automation Conference, pp. 711-716 (June 1991). 5. A. Casotto, A.R. Newton, and A. Sangiovanni-Vincentelli, ‘‘Design Management based on Design Traces’’, Proc. 27th ACM/IEEE Design Automation Conference, pp. 136-141 (1990). 6. M. Rumsey and C. Farquhar, ‘‘Unifying Tool, Data and Process Flow Management’’, Proc. EURO-DAC 92, pp. 500-505 (Sept 1992). 7. K.O. ten Bosch, P. van der Wolf, and P. Bingley, ‘‘A Flow-Based User Interface for Efficient Execution of the Design Cycle’’, Proc. IEEE/ACM International Conference on CAD - 93, pp. 356-363 (Nov 1993). 8. P. van der Wolf, G.W. Sloof, P. Bingley, and P. Dewilde, ‘‘Meta Data Management in the NELSIS CAD Framework’’, Proc. 27th ACM/IEEE Design Automation Conference, pp. 142-145 (June 1990). 9. V. Vasudevan, Y. Mathys, and J. Tolar, ‘‘Damocles: An Observer-Based Approach to Design Tracking’’, Proc. IEEE/ACM International Conference on CAD - 92, pp. 546-551 (Nov 1992). 10. P. Bingley, K.O. ten Bosch, and P. van der Wolf, ‘‘Incorporating Design Flow Management in a Framework Based CAD System’’, Proc. IEEE/ACM International Conference on CAD - 92, pp. 538-545 (Nov 1992). 11. J.H. ter Bekke, Semantic Data Modeling, Prentice Hall, Englewood Cliffs, N.J. (1992). ISBN 0-13-806050-9. ICCAD94, Pages 508-515 On Modeling Top-Down VLSI Design Bernd Schürmann, Joachim Altmeyer, Martin Schütze University of Kaiserslautern, D-67653 Kaiserslautern, Germany Abstract We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept that describes the convergence of a design. The design history which makes the semantics of most other version concepts, is modeled explicitly by additional object classes (entities types) but not by the version graph itself. Top-down steps are modeled by splitting a design object into requirements and realizations. The composition hierarchy is expressed by a simple but powerful configuration method. Design data of iterative refinement processes are managed efficiently by storing incremental data only. References [1] M. Brielmann, E. Kupitz, “Representing the Hardware Design Process by a Common Data Schema”, Proc. Int. European Design Automation Conference, 1992 [2] “Design Representation Electrical Connectivity Information Model and Programming Interface”, CFI Pilot Release Document, CFI-92-P-6, 1992 [3] R.H. Katz, “Information Management for Engineering Design”, Springer Verlag, 1985 [4] R.H. Katz, “Towards a Unified Framework for Version Modeling in Engineering Databases”, ACM Computing Surveys, Vol. 22, No. 4, 1990 [5] M. Pedram, B. Preas, “A Hierarchical Floorplanning Approach”, Proc. Int. Conference on Computer Design, Cambridge, 1990 [6] B. Preas, K. Roberts, “YAL Language Description”, part of the MCNC benchmark distribution, MCNC Research Triangle Park, NC, 1987 [7] W. Sun, C. Sechen, “Efficient and Effective Placement for Very Large Circuits”, Proc. Int. Conference of Computer Aided Design, 1993 [8] B. Schuermann, J. Altmeyer, G. Zimmermann, “Three-Phase Chip Planning - An Improved Top-Down Chip Planning Strategy”, Proc. Int. Conference of Computer Aided Design, 1992 [9] E. Siepmann, G. Zimmermann, “An Object-Oriented Datamodel for the VLSI Design System PLAYOUT”, Proc. 26th Design Automation Conference, 1989 [10] G. Scholz, W. Wilkes, “Information Modelling of Folded and Unfolded Design”, Proc. Int. European Design Automation Conference, 1992 [11] P. van der Wolf, N. van der Meijs, T.G.R. van Leuken, et.al., “Data Management for VLSI Design: Conceptual Modeling, Tool Integration and User Interface”, Proc. IFIP Workshop on Tool Integration and Design Environments, 1988 [12] G. Zimmermann, “PLAYOUT - A Hierarchical Design System”, Information Processing 89, G.X. Ritter (ed.), Elsevier Science Publishers B.V. (North Holland), IFIP, 1989 [13] G. Zimmermann, “The MIMOLA Design System – A Computer Aided Digital Processor Design Method”, 25 Years of Electronic Design Automation, A compendium of papers from the Design Automation Conference, 1988 [14] “IEEE Standard VHDL Language Reference Manual”, The Institute of Electrical and Electronics Engineers, Inc., New York, 1988 ICCAD94, Pages 516-521 A Formal Basis for Design Process Planning and Management Margarida F Jacome Electrical and Computer Engineering Dept., University of Texas at Austin, Austin, TX 78712 Stephen W. Director Electrical and Computer Engineering Dept., Carnegie Mellon University, Pittsburgh, 15213 ABSTRACT In this paper we present a design formalism that allows for a complete and general characterization of design disciplines and for a unified representation of arbitrarily complex design processes. This formalism has been used as the basis for the development of several prototype CAD meta-tools that offer effective design process planning and management services. Bibliography [1] M.F. Jacome. Design Process Planning and Management for CAD Frameworks. PhD thesis, Carnegie Mellon University, Department of Electrical and Computer Engineering, September 1993. [2] M.F. Jacome, and S.W.Director. Design Process Management for CAD Frameworks. In Proceedings of 29th ACM/IEEE Design Automation Conference. ACM Press, 1992. [3] J.C. Lopez, M.F. Jacome, and S.W. Director. Design Assistance for CAD Frameworks. In Proceedings of First GI/ACM/IEEE/IFIP European Design Automation Conference. ACM Press, 1992. [4] H.A. Simon. The Sciences of the Artificial. The MIT Press, 1981. [5] E. D. Sacerdoci. Planning in a Hierarchy of Abstraction Spaces. Artificial Intelligence, 5:115-135, 1974. ICCAD94, Pages 524-531 Design of heterogeneous ICs for mobile and personal communication systems Gert Goossens, Ivo Bolsens, Bill Lin, Francky Catthoor IMEC, Kapeldreef 75, B-3001 Leuven, Belgium Abstract Mobile and personal communication systems form key market areas for the electronics industry of the nineties. Stringent requirements in terms of flexibility, performance and power dissipation, are driving the development of integrated circuits into the direction of heterogeneous single-chip solutions. New IC architectures are emerging which contain the core of a powerful programmable processor, complemented with dedicated hardware, memory and interface structures. In this tutorial we will discuss the real-life design of a heterogeneous IC for an industrial telecom application : a reconfigurable mobile terminal for satellite communication. Based on this practical design experience, we will subsequently discuss a methodology for the design of heterogeneous ICs. Design steps that will be addressed include : system specification and refinement, data path and communication synthesis, and code. References [1] R.P. Ang, N.K. Dutt, “A representation for the binding of RT-component functionality to HDL behavior", Proc. IFIP Conf. Hardw. Descr. Lang., pp. 251-266, Ottawa,April 1993. [2] “ARM7DM data sheet", Doc. No. ARM-DDI-0010-F, Advanced Risc Machines Ltd., Cambridge,May 1994. [3] T. Baba, H. Hagiwara, “The Mpg system : a machine-independent efficient microprogram generator", IEEE Trans. Computers, Vol. C-30, No. 6, pp. 373-395, 1981. [4] F. Balasa et al., “Dataflow-driven memory allocation for multi-dimensional signal processing systems", Proc. IEEE Int. Conf. Comp.-Aided Design, Santa Clara,Nov. 1994. [5] M.R. Barbacci, “Instruction Set Processor Specifications (ISPS) : the notation and its applications", IEEE Tr. Comp., Vol. C-30, No. 1, pp. 24-40, Jan. 1981. [6] G. Berry, G. Gonthier, “The Esterel synchronous programming language : design, semantics, implementation", Science of Comp. Prog., Vol. 19, No. 2, pp. 87-152, 1992 [7] G. Berry et al., “Communicating reactive processes", Proc. 20th ACM Principles of Prog. Lang., 1993. [8] G. Bilsen et al., “Static scheduling of multi-rate and cyclostatic DSP-applications", IEEE Workshop VLSI Signal Proc., La Jolla,Oct. 1994. [9] I. Bolsens et al., “User requirements for designing complex systems on silicon", IEEE Workshop VLSI Signal Proc., La Jolla,Oct. 1994. [10] R.K. Brayton et al., “Multi-level logic synthesis", Proc. IEEE, Vol. 72, No. 2, pp. 264-300, Feb. 1990. [11] J.T. Buck et al., “Ptolemy : a framework for simulating and prototyping heterogeneous systems", Int. J. Computer Simulation, January 1994. [12] F. Catthoor et al., “Global communication and memory optimizing transformations for low power signal processing systems", IEEE Workshop VLSI Signal Proc., La Jolla,Oct. 1994. [13] G. de Jong, B. Lin, “A communicating Petri net model for the design of concurrent asynchronous modules", Proc. 31st ACM Design Autom. Conf., pp. 49-55, San Diego,June 1994. [14] “DSP Architect - DFL - User's and Reference Manual", EDC/Mentor Graphics Corp., Leuven,1993. [15] J.R. Ellis, “Bulldog : a compiler for VLIW architectures", MIT Press, Cambridge,1986. [16] R. Ernst et al., “Hardware-software co-synthesis for microcontrollers", IEEE Design & Test of Computers, Vol. 10, No. 4, December 1993. [17] A. Fauth et al., “Generation of hardware machine models from instruction set descriptions", VLSI Signal Processing VI , pp. 242-250, 1993. [18] M. Ganapathi et al., “Retargetable compiler code generation", Computing Surveys, Vol. 14, No. 4, pp. 573-593, 1982. [19] D. Genin et al., “DSP specification using the Silage language", Proc. IEEE Int. Conf. Acoustics, Speech and Signal Proc., pp. 1057-1060, Albuquerque,April 1990. [20] W. Geurts et al., “Memory and data-path mapping for image and video applications", Application-driven architecture synthesis, pp. 143-166, Kluwer, Boston,1993. [21] G. Goossens et al., “Integration of signal processing systems on heterogeneous IC architectures", Pres. at 6th IEEE Int. Workshop High Level Synth., Dana Point,Nov. 1992. [22] R.K. Gupta, G. De Micheli, “Hardware-software co-synthesis for digital systems", IEEE Design & Test of Computers, Vol. 10, No. 3, pp. 29-41, Sept. 1993. [23] D. Harel et al., “Statemate : a working environment for the development of complex reactive systems" IEEE Tr. Software Eng., Vol. 16, No. 4, April 1990. [24] J.L. Hennessy, D.A. Patterson, “Computer architecture : a quantitative approach", Morgan Kaufmann Publ. 1990. [25] C.A.R. Hoare, “Communicating Sequential Processes", Prentice Hall, 1985. [26] T.B. Ismail et al., “Interactive system-level partitioning with Partif", Proc. European Design & Test Conf., pp. 464-468, Paris, Feb. 1994. [27] M. Janssen et al., “A specification invariant technique for operation cost minimisation in flow-graphs", Proc. 7th IEEE Int. Symp. High-Level Synth., pp. 146-151, Niagara-on-the-Lake,May 1994. [28] A. Jerraya, K. O'Brien, “Solar : an intermediate format for system level design and specification", Pres. at Int. Workshop Hardw./Softw. Co-Des., Grassau,May 1992. [29] G. Jones, M. Goldsmith, “Programming in Occam 2", C.A.R. Hoare Series in Computer Science, Prentice Hall. [30] A. Kalavade, E.A. Lee, “A hardware/software codesign methodology for DSP applications", IEEE Design & Test of Computers, pp. 16-28, Sept. 1993. [31] T. Kolks et al., “Sizing of communication buffers for communicating signal processors", VLSI Signal Processing VI , pp. 426-434, 1993. [32] D. Lanneer et al., “Data routing : a paradigm for efficient data-path synthesis and code generation", Proc. 7th IEEE Int. Symp. High-Level Synth., pp. 17-22, Niagara-on-the-Lake, May 1994. [33] E.A. Lee, “Programmable DSP architectures : Part I & Part II", IEEE ASSP Magazine, Dec. 1988 and Jan. 1989. [34] C. Liem et al., “Register assignment through resource classification for ASIP microcode generation", Proc. ACM/IEEE Int. Conf. Comp.-Aided Design, San Jose,Nov. 1994. [35] B. Lin, S. Vercauteren, “Synthesis of concurrent system interface modules with automatic protocol conversion generation", Proc. ACM/IEEE Int. Conf. Comp.-Aided Design, San Jose,Nov. 1994. [36] P. Marwedel, “Tree-based mapping of algorithms to predefined structures", Proc. IEEE/ACM Int. Conf. Comp.-Aided Design, pp. 586-593, Santa Clara,Nov. 1993. [37] M.C. McFarland et al., “The high-level synthesis of digital systems", Proc. of the IEEE, Vol. 78, No. 2, pp. 301-318, Feb. 1990. [38] R.A. Mueller et al., “Global methods in the flow graph approach to retargetable microcode generation", Proc. 17th Microprog. Workshop, pp. 275-284, 1984. [39] S. Note et al., “Cathedral III : architecture driven high-level synthesis for high throughput DSP applications", Proc. 28th ACM/IEEE Design Autom. Conf., pp. 597-602, San Francisco, June 1991. [40] S. Note et al., “A low-power, low-voltage dedicated DSP implementation of a GSM baseband processor with DSP-Station", IEEE Workshop VLSI Signal Proc., La Jolla,Oct. 1994. [41] S. Narayan et al., “System specification and synthesis with the SpecCharts language", Proc. ACM/IEEE Int. Conf. Comp.-Aided Design, pp. 266-271, Santa Clara,Nov. 1991. [42] P.G. Paulin et al., “DSP design tool requirements for embedded systems : a telecommunications industrial perspective", To be publ. in J. VLSI Signal Proc., 1994. [43] M. Potkonjak, J. Rabaey, “Optimizing resource utilization using transformations", Proc. IEEE Int. Conf. Comp.Aided Design, pp. 88-91, Santa Clara,Nov. 1991. [44] L. Philips et al., “Silicon integration of digital user-end mobile communication systems", Proc. Int. Conf. Communications, pp. 212-216, Geneva,May 1993. [45] L. Philips et al., “Silicon synthesis of a exible CDMA/QPSK mobile communication modem", DSP Applications, Jan. 1994. [46] J.M. Rabaey et al., “Fast prototyping of datapath-intensive architectures", IEEE Design & Test of Computers, pp. 40-51, June 1991. [47] D.S. Rao, F.J. Kurdahi, “Partitioning by regularity extraction", Proc. 29th ACM/IEEE Design Autom. Conf., pp. 235-238, Anaheim,June 1992. [48] E.M. Sentovich et al., “Sequential circuit design using synthesis and optimization", Proc. IEEE Int. Conf. Comp. Design, pp. 328-333, Oct. 1992. [49] “SPOX - The DSP operating system", Spectron Microsystems, Santa Barara,1992. [50] M.B. Srivastava, R.W. Brodersen, “Using VHDL for high level mixed mode system simulation", IEEE Design & Test of Computers, pp. 31-41, Sept. 1992. [51] P. Vanbekbergen et al., “A generalised state assignment theory for transformations on signal transition graphs", J. VLSI Signal Proc., pp. 101-116, Feb. 1994. [52] J. Vanhoof et al., “High-level synthesis for real-time digital signal processing" Kluwer Ac. Publ. Boston,1993. [53] C. Van Himbeeck, “The use of CDMA in European mobile satellite communication systems", Proc. IEEE Int. Symp. Spread Spectrum Techn. and Applic., Oulu,July 1994. [54] J. Van Praet at al., “Instruction set definition and instruction selection for ASIPs", Proc. 7th IEEE Int. Symp. on High-Level Synth., pp. 11-16, Niagara-on-the-Lake,May 1994. [55] M. van Swaaij et al., “Automating high-level control flow transformations for DSP memory management", VLSI Signal Processing V, pp. 397-406, IEEE Press, New York,1992. [56] W.F.J. Verhaegh et al., “Modeling periodicity by Phideo streams", Pres. at 6th IEEE Int. Workshop High-Level Synth., Dana Point,Nov. 1992. [57] S. Vernalde et al., “Synthesis of high throughput DSP ASICs using application specific datapaths", DSP Applications, June 1994. [58] “Virtuoso Classico user manual", Intelligent Systems International, Linden,1993. [59] R. Walker, D. Thomas, “Behavioral transformation for algorithmic level IC design", IEEE Transactions on Comp.-Aided Design, Vol. 8, No. 10, pp. 1115-1128, Oct. 1989. [60] C. Ykman-Couvreur et al., “Concurrency reduction transformations on state graphs for asynchronous circuit synthesis", Proc. Int. Workshop Logic Synth., Lake Tahoe,May 1993. ICCAD94, Pages 534-540 Embedded Systems Design for Low Energy Consumption Michael A. Schuette, Ph.D., John R. Barr, Ph.D., Motorola, Inc. Abstract This tutorial covers the circuit fundamentals of CMOS circuits which contribute to the consumption of energy in portable products, as well as guidelines for the design of systems in order to reduce energy consumption and prolong battery life. Circuit fundamentals will include a definition of terms, basic circuit elements, laws of operation, and basic circuit theory applying energy consumption. We will then present three major principles of energy reduction: reducing number of transitions, reducing the amount of switched capacitance, and reducing the operating voltage. Several guidelines that can be applied during the system design process which utilize the three major principles. References [1] Landman, P. and J.M. Rabaey, “Black-Box Capacitance Models for Architectural Power Analysis”, Int’l Workshop on Low Power Design, April, 1994, pp 165-170. [2] Rabaey, J., “Tutorial 3: Low Power System Design: Solutions and Challenges”, Design Automation Conference, June, 1994. [3] Chandrakasan, A., S. Sheng, and R. Brodersen, “Low-Power CMOS Digital Design”, IEEE Journal of SolidState Circuits, Vol. 27, No. 4, April, 1992, pp. 473-483. [4] Stanley, W., G. Dougherty, and R. Dougherty, “Digital Signal Processing”, Reston Publishing, 2nd Edition, 1984 [5] Bunda, J., D. Fussell, R. Jenevein, and W.C. Athas, “16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors”, 20th Int’l. Symposium on Computer Architecture, May 16-19, 1993, pp. 237-246 [6] Buyer’s Guide to DSP Processors, Berkeley Design Technologies Inc., 1994 [7] Wuytack, S., F. Catthoor, F. Franssen, L. Nachtergaele, and H. DeMan, “Global communication and memory optimizing transformations for low power systems”, Int’l Workshop on Low Power Design, April, 1994, pp 203208. ICCAD94, Pages 542-549 Synthesis of Hazard-Free Multi-level Logic under Multiple-Input Changes from Binary Decision Diagrams Bill Lina, Srinivas Devadasb a IMEC Laboratory, B-3001 Leuven, Belgium, Email:billlin@imec.be Department of EECS, MIT, Cambridge, MA, Email:devadas@mit.edu b Abstract We describe a new method for directly synthesizing a hazard-free multilevel logic implementation from a given logic specification. The method is based on free/ordered Binary Decision Diagrams (BDD's), and is naturally applicable to multiple-output logic functions. Given an incompletely-specified (multiple-output) Boolean function, the method produces a multilevel logic network that is hazard-free for a specified set of multiple-input changes. We assume an arbitrary (unbounded) gate and wire delay model under a pure delay (PD) assumption, we permit multiple-input changes, and we consider both static and dynamic hazards. This problem is generally regarded as a difficult problem and it has important applications in the field of asynchronous design. The method has been automated and applied to a number of examples. The results we have obtained are very promising. References [1] P.A. Beerel and T. Meng. Automatic gate-level synthesis of speed-independent circuits. In ICCAD-1992. [2] J. Beister. A unified approach to combinational hazards. IEEE Transactions on Computers, C-23(6), 1974. [3] J.G. Bredeson. Synthesis of multiple input-change hazard-free combinational switching circuits without feedback. Int. J. Electronics, 39(6):615-624, 1975. [4] R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C35(8):677-691, August 1986. [5] T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. Technical Report MITLCS-TR-393, Massachusetts Institute of Technology, 1987. [6] O. Coudert and J.C. Madre. A unified framework for the formal verification of sequential circuits. In ICCAD-90, pages 126-129, November 1990. [7] E.B. Eichelberger. Hazard detection in combinational and sequential switching circuits. IBM J. Res. Develop., 9(2):90-99, 1965. [8] A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. On the conditions for gate-level speed-independence of asynchronous circuits. In TAU-1993. [9] D.S. Kung. Hazard-non-increasing gate-level optimization algorithms. In ICCAD-1992. [10] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronous circuits. In DAC-91. [11] B. Lin and S. Devadas. Synthesis of Hazard-Free Multi-level Logic Implementations under Multiple-Input Changes from Binary Decision Diagrams". In IMEC Technical Report TR-VSDM-93-11., November, 1993. Revised May, 1994. [12] S. Nowick, 1993. Private communication. [13] S.M. Nowick and D.L. Dill. Automatic synthesis of locally-clocked asynchronous state machines. In ICCAD1991. [14] S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In ICCAD-1992. [15] S.H. Unger. Asynchronous Sequential Switching Circuits. New York: Wiley-Interscience, 1969. [16] P. Vanbekbergen, B. Lin, G. Goossens, and H. De Man. A generalized state assignment theory for transformations on signal transition graphs. In ICCAD-1992. [17] K. Y. Yun and D. L. Dill. Unifying Asynchronous/Synchronous State Machine Synthesis. In ICCAD-93, pages 255-260, November 1993. [18] K. Y. Yun, B. Lin, D. L. Dill, and S. Devadas. Performance-Driven Synthesis of Asynchronous Controllers. In ICCAD-94, November 1994. ICCAD94, Pages 550-557 Performance-driven Synthesis of Asynchronous Controllers Kenneth Y. Yun1, Bill Liny, David L. Dill3, Srinivas Devadas4 1 Department of ECE, University of California, San Diego, CA 92093 2 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium 3 Computer Systems Laboratory, Stanford University, Stanford, CA 94305 4 Department of EECS, MIT, Cambridge, MA 02139 Abstract We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs)—representations of logic functions factored recursively with respect to input variables — on extended burst-mode asynchronous synthesis. First, the use of the BDD-based synthesis reduces the constraints on state minimization and assignment, which reduces the number of additional state variables required in many cases. Second, in cases where conditional signals are sampled, it eliminates the need for state variable changes preceding output changes, which reduces overall input to output latency. Third, selection variables can easily be ordered to minimize the latency on a userspecified path, which is important for optimizing the performance of systems that use asynchronous components. We present extensive evaluations showing that, with only minimal optimization, the BDD-based synthesis gives comparable results in area with our previous exact two-level synthesis method. We also give a detailed example of the specified path optimization. References [1] V. Akella and G. Gopalakrishnan. SHILPA: A high-level synthesis system for self-timed circuits. In ICCAD-92, pp 587–591. [2] P. Beerel and T. Meng. Automatic gate-level synthesis of speed-independent circuits. In ICCAD-92, pp 581–586. [3] E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In ICCAD-89, pp 262–265. [4] R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C35(8):677-691, August 1986. [5] T.-A. Chu. Synthesis of self-timed VLSI circuits from graphtheoretic specifications. Technical Report MITLCS-TR-393, MIT, 1987. Ph.D. Thesis. [6] A. Davis, W. Coates, and K. Stevens. The Post Office experience: designing a large asynchronous chip. In HICSS, Volume I, pp 409–418, January 1993. [7] L. Lavagno and A. Sangiovanni-Vincentelli. Algorithms for synthesis and testing of hazard-free asynchronous circuits. Kluwer Academic, 1993. [8] B. Lin and S. Devadas. Synthesis of Hazard-Free Multi-level Logic Implementations under Multiple-Input Changes from Binary Decision Diagrams. In This Proceedings. [9] A. J. Martin. Programming in VLSI: From communicating processes to delay-insensitive VLSI circuits. In C. A. R. Hoare, editor, UT Year of Programming Institute on Concurrent Programming, Addison-Wesley, 1990. [10] Teresa H. Meng. Synchronization Design for Digital Systems. Kluwer Academic, 1990. [11] C. E. Molnar, T.-P. Fang, and F. U. Rosenberger. Synthesis of delay-insensitive modules. In Henry Fuchs, editor, 1985 Chapel Hill Conference on Very Large Scale Integration, pp 67–86. CSP, Inc., 1985. [12] C. W. Moon, P.R. Stephan, and R.K. Brayton. Specification, synthesis, and verification of hazard-free asynchronous circuits. In ICCAD-91, pp 322–325. [13] C. Myers and T. Meng. Synthesis of timed asynchronous circuits. In ICCD-92, pp 279–284. [14] S. Nowick, M. Dean, D. Dill, and M. Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. In HICSS, volume I, pp 419–427, January 1993. [15] S. M. Nowick and B. Coates. Automated design of high-performance unclocked state machines. In ICCD-94. [16] Steven M. Nowick. Automatic synthesis of burst-mode asynchronous controllers. Ph.D.Thesis, StanfordUniversity, 1993. [17] S. M. Nowick, K. Y. Yun, and D. L. Dill. Practical asynchronous controller design. In ICCD-92, pp 341–345. [18] Ivan Sutherland, 1994. Private communication. [19] Stephen H. Unger. Asynchronous Sequential Switching Circuits. Wiley-Interscience, 1969. [20] Peter Vanbekbergen. Synthesis of asynchronous controllers from graph-theoretic specifications. Ph.D. Thesis, Interuniversitair Micro-Elektronica Centrum, 1993. [21] C. Ykman-Couvreur, B. Lin, G. Goossens, and H. De Man. Synthesis and optimization of asynchronous controllers based on extended lock graph theory. In EDAC-93, pp 512–517. [22] Kenneth Y. Yun and David L. Dill. Automatic synthesis of 3D asynchronous state machines. In ICCAD-92, pp 576–580. [23] Kenneth Y. Yun and David L. Dill. Unifying Synchronous/Asynchronous State Machine Synthesis. InICCAD93, pp 255–260. ICCAD94, Pages 558-565 Decomposition Methods for Library Binding of Speed-Independent Asynchronous Designs Polly Siegel, Giovanni De Micheli Center for Integrated Systems, Stanford University, Stanford CA 94305 Abstract We describe methods for decomposing gates within a speed-independent asynchronous design. The decomposition step is an essential part of the library binding process, and is used both to increase the granularity of the design for higher quality mapping and to ensure that the design can be implemented. We present algorithms for simple hazard-free gate decomposition, and show results which indicate that we can decompose most of the gates in our benchmark set by this simple method. We then extend these algorithms to work for those cases in which no simple decomposition exists. References [1] P. Beerel and T. H.-Y. Meng, “Automatic gate-level synthesis of speed-independent circuits,” in ICCAD, Proceedings of the International Conference on Computer-Aided Design, pages 581–586, Nov. 1992. [2] P. Beerel and T. H.-Y. Meng, “Logic transformations and observability don’t cares in speed-independent circuits,” in TAU, Aug. 1993. [3] T.-A. Chu, “Synthesis of self-timed VLSI circuits from graph-theoretic specifications,” Technical Report MITLCS-TR-393, MIT, 1987. [4] W. S. Coates, A. L. Davis, and K. S. Stevens, “Automatic synthesis of fast compact self-timed control circuits,” in IFIP Workshop on Asynchronous Circuits, Manchester, UK, 1993. [5] W. S. Coates, A. L. Davis, and K. S. Stevens, “The post office experience: Designing a large asynchronous chip,” INTEGRATION, the VLSI journal, 15(4):341–366, 1993. [6] K. Keutzer, “DAGON: Technology binding and local optimization by DAG matching,” in 24th Design Automation Conference, pages 341–347, IEEE/ACM, 1987. [7] L. Lavagno and A. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits, Kluwer Academic Publishers, 1993. [8] F. Mailhot and G. De Micheli, “Algorithms for technology mapping based on binary decision diagrams and on boolean operations,” IEEE Transactions on CAD/ICAS, pages 599–620, May 1993. [9] E. J. McCluskey, Logic Design Principles With Emphasis on Testable Semicustom Circuits, Prentice-Hall, 1986. [10] T. H. Meng, Synchronization Design for Digital Systems, Kluwer Academic, 1990. [11] S. M. Nowick and D. L. Dill, “Synthesis of asynchronous state machines using a local clock,” in ICCD, Proceedings of the International Conference on Computer Design, pages 192–197, IEEE Computer Society Press, 1991. [12] J. K. Ousterhout, Tcl and the Tk Toolkit, Addison Wesley, 1993. [13] R. Rudell, Logic Synthesis for VLSI Design, PhD thesis, U. C. Berkeley, Apr. 1989, Memorandum UCB/ERL M89/49. [14] P. Siegel, Technology Mapping for Asynchronous Designs, PhD thesis, Stanford University, 1994. [15] P. Siegel, G. De Micheli, and D. Dill, “Automatic technology mapping for generalized fundamental-mode asynchronous designs,” in DAC, Proceedings of the Design Automation Conference, pages 61–67, June 1993. [16] S. H. Unger, Asynchronous Sequential Switching Circuits, New York: Wiley-Interscience, 1969. [17] V. I. Varshavsky, editor, Self-Timed Control of Concurrent Processes, Kluwer Academic Publishers, Dordrecht, The Netherlands, 1990. [18] K. Yun and D. Dill, “Automatic synthesis of 3D asynchronous finite-state machines,” in ICCAD, Proceedings of the International Conference on Computer-Aided Design, pages 576–580, Nov. 1992. ICCAD94, Pages 568-575 On Error Correction in Macro-Based Circuits Irith Pomeranz and Sudhakar M. Reddy  Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA 52242 Abstract We consider the problem of correcting errors in a macro-based circuit. Our formulation of the problem allows the correction of errors that arise both in the context of design error correction, before the circuit is realized, and in the context where a physical circuit needs to be corrected. Two error classes are defined, namely, component errors and line errors. Both single and multiple errors are considered. Accurate correction procedures are given for single errors. Heuristics are given for correcting multiple errors. Experimental results are given to demonstrate the correction procedures presented. References [1] K. Keutzer, "DAGON: Technology binding and local optimization by DAG Matching", in Proc. 24th Design Autom. Conf., 1987, pp. 341-347. [2] M. S. Abadir, J. Ferguson and T. E. Kirkland, "Logic Design Verification via Test Generation", IEEE Trans. on Computers, Jan. 1988, pp. 138-148. [3] S.-Y. Kuo, "Locating Logic Design Errors via Test Generation and Don’t-Care Propagation", 1992 Europ. Design-Autom. Conf., Sept. 1992, pp. 466-471. [4] P.-Y. Chung and I. N. Hajj, "ACCORD: Automatic Catching and Correction of Logic Design Errors in Combinational Circuits", 1992 Intl. Test Conf., pp. 742-751, 1992. [5] I. Pomeranz and S. M. Reddy, "On Correction of Multiple Design Errors", 3rd Intl. Conf. on VLSI and CAD, 1993. [6] Y. Kukimoto and M. Fujita, "Rectification Method for Lookup-Table Type FPGA’s", in Proc. 1992 Intl. Conf. on Computer-Aided Design, Nov. 1992, pp. 54-61. [7] E. J. McCluskey, "Test and Diagnosis Procedure for Digital Networks", Computer, Jan. 1971, pp. 17-20. [8] R. E. Tulloss, "Fault Dictionary Compression: Recognizing when a Fault May Be Unambiguously Represented by a Single Failure Detection", 1980 Test Conf., Nov. 1980, pp. 368-370. [9] R. Brayton, G. D. Hachtel, C. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984. [10] I. Pomeranz and S. M. Reddy, "Testability Considerations in Technology Mapping", 3rd Asia Test Symp., Nov. 1994. [11] I. Pomeranz and S. M. Reddy, "On Error Correction in Macro-Based Circuits", Technical Report No. 4-1-1994, ECE Dept., U. of Iowa. ICCAD94, Pages 576-579 Fault Dictionary Compaction by Output Sequence Removal Vamsi Boppana and W. Kent Fuchs Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801 Abstract Fault dictionary compaction has been accomplished in the past by removing responses on individual output pins for specific test vectors. In contrast to the previous work, we present techniques for eliminating entire sequences of outputs and for efficiently storing the remaining output sequences. Experimental results on the ISCAS 85 and ISCAS 89 benchmark circuits show that the sizes of dictionaries proposed are substantially smaller than the full fault dictionary, while the dictionaries retain most or all of the diagnostic capability of the full fault dictionary. References [1] R. E. Tulloss, “Size Optimization of Fault Dictionaries," Proc. SemiConductor Test Conf., 1978, pp.264-265. [2] P. G. Ryan, S. Rawat and W. K. Fuchs, “Two-Stage Fault Location," Proc. Intl. Test Conf., Oct. 1991, pp. 963968. [3] R. E. Tulloss, “Fault Dictionary Compression: Recognizing when a Fault may be Unambiguously Represented by a Single Failure Detection," Proc. Intl. Test Conf., Nov. 1980, pp. 368-370. [4] I. Pomeranz and S. M. Reddy, “On the Generation of Small Dictionaries for Fault Location," Proc. Intl. Conf. on Computer-Aided Design, Nov. 1992, pp. 272-279. [5] P. G. Ryan, W. K. Fuchs and I. Pomeranz, “Fault Dictionary Compression and Equivalence Class Computation for Sequential Circuits," Proc. Intl. Conf. on Computer-Aided Design, Nov. 1993, pp. 508-511. ICCAD94, Pages 580-583 Automatic Test Program Generation for Pipelined Processors Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, and Fumiyasu Hirose Fujitsu Laboratories Ltd., 1015 Kamikodanaka, Nakahara-ku, Kawasaki 211, Japan Abstract Simulation-based verification has both advantages and disadvantages compared with formal verification. Our demand is to find a practical way to verify actual microprocessors. This paper presents an efficient test program generation method for simulation-based verification using techniques developed for formal verification. Our test program generator enumerates all reachable states of a processor pipeline and generates instruction sequences for every reachable test case. The program covers complicated test cases that are difficult to cover with random instructions and impossible to cover with conventional test program generation methods. Our test program generator also works for larger microprocessor designs than formal verifiers have done. References [1] J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann,1990. [2] M. Johnson, Superscalar Microprocessor Design, Prentice Hall. 1991. [3] D. C. Lee and D. P. Siewiorek, "Functional Test Generation for Pipelined Computer Implementations," FTCS21, pp. 60-67,1991. [4] H. Iwashita, T. Nakata, and F. Hirose, "Behavioral Design and Test Assistance for Pipelined Processors," IEEE The First Asian Test Symposium, pp. 8-13,1992. [5] H. Iwashita, T. Nakata, and F. Hirose, "Integrated Design and Test Assistance for Pipeline Controllers," IEICE Transactions on Information and Systems, Vol. E76-D, No. 7, pp. 747-754,1993. [6] J. R. Butch and D. L. Dill, "Automatic Verification of Pipelined Microprocessor Control," Proc. Conf. on Computer-Aided Verification, pp. 68-80,1994. [7] D. L. Beatty and R. E. Bryant "Formally Verifying a Microprocessor Using a Simulation Methodology," Proc. 31st DAC, pp. 596-602,1994. [8) V. Bhagwati and S. Devadas, "Automatic Verification of Pipelined Microprocessors," Proc. 31st DAC, pp. 603-608, 1994. [9] R. E. Bryant, "Graph Based Algorithm for Boolean Function Manipulation," IEEE Transactions on Computers, C-35(8), pp. 677-691,1986. [10] H. J. Touati, H. Savoj, B. Lin, R. K. Brayton, A. Sangiovanni-Vincentelli, "Implicit State Enumeration of Finite State Machines using BDD's", ICCAD-90, pp. 130-133, 1990. ICCAD94, Pages 586-593 Synthesis of Manufacturable Analog Circuits Tamal Mukherjee, L.R. Carley and R.A Rutenbar Electrical and Computer Engineering Dept, Carnegie Mellon University, Pittsburgh, PA 15213 Abstract We describe a synthesis system that takes operating range constraints and inter- and intra- circuit parametric manufacturing variations into account while designing a sized and biased analog circuit. Previous approaches to CAD for analog circuit synthesis have concentrated on nominal analog circuit design, and subsequent optimization of these circuits for statistical fluctuations and operating point ranges. Our approach simultaneously synthesizes and optimizes for operating and manufacturing variations by mapping the circuit design problem into an Infinite Programming problem and solving it using an annealing within annealing formulation. We present circuits designed by this integrated synthesis system, and show that they indeed meet their operating range and parametric manufacturing constraints. References [1] K.J. Antriech, H.E. Graeb, and C.U. Wieser, “Circuit Analysis and Optimization Driven by Worst-Case Distances”, IEEE Trans. CAD, vol. 13, no. 1, pp. 57-71, Jan. 1994. [2] G.L. Bilbro and W.E. Snyder, “Optimization of Functions with Many Minima”, IEEE Trans on Systems, Man and Cybernetics, vol. 21, no. 4, pp. 840-849, July/August 1991. [3] I.D. Coope and G.A. Watson, “A Projected Lagrangian Algorithm for Semi-Infinite Programming”, Mathematical Programming, pp. 337-356, 1985. [4] M.G.R. Degrauwe et al., “Towards an analog system design environment,” IEEE JSSC, vol. SC-24, no. 3, June 1989. [5] A. Dharchoudhury and S.M. Kang, “Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits”, Proc. 30th ACM/IEEE DAC, pp. 154-158, 1993. [6] S.W. Director, P. Feldmann and K. Krishna, “Optimization of Parametric Yield: A Tutorial”, Proc IEEE CICC, pp. 3.1/1-8, May 1992. [7] B.C. Eaves and W.I. Zangwill, “Generalized Cutting Plane Algorithms”, SIAM Journal of Control, vol. 9, pp 529-542, 1971. [8] P. Feldmann and S.W. Director, “Integrated Circuit Quality Optimization using Surface Integrals”, IEEE Trans. CAD, vol. 12, no. 12, pp. 1868-1879, Dec. 1993. [9] A.V. Fiacco and K.O. Kortanek, eds., Semi-Infinite Programming and Applications, Lecture notes in Economics and Mathematical Systems 215, Springer-Verlag, 1983. [10] R. Fletcher, Practical Methods of Optimization, Wiley, 1990. [11] G. Gielen, et al., “Analog circuit design optimization based on symbolic simulation and simulated annealing,”IEEE JSSC, vol. SC-25, no. 3, June 1990. [12] R. Harjani, R.A. Rutenbar and L.R. Carley, “OASYS: a framework for analog circuit synthesis,”IEEE Trans. CAD, vol. 8, no. 12, Dec. 1989. [13] J. P. Harvey, et al., “STAIC: An Interactive Framework for Synthesizing CMOS and BiCMOS Analog Circuits,” IEEE Trans. CAD, Nov. 1992. [14] R. Heittich, ed., Semi-Infinite Programming, Lecture notes in Control and Information Sciences 15, SpringerVerlag, 1979. [15] D.E. Hocevar, P.F. Cox and P. Yang, “Parametric yield optimization for MOS circuit blocks”, IEEE Trans. CAD, vol. 7, no. 6, June 1988. [16] S. Hustin and A. Sangiovanni-Vincentelli, “TIM, a new standard cell placement program based on the simulated annealing algorithm”, presented at IEEE Physical Design Workshop on Placement and Floorplanning, Hilton Head, SC, April 1987. [17] S. Kirkpatrick, C.D. Gelatt, M.P. Vecchi, “Optimization by simulated annealing,” Science, vol. 220, no. 4598, 13 May 1983. [18] H.Y. Koh, C.H. Sequin, and P.R. Gray, “OPASYN: a compiler for MOS operational amplifiers,” IEEE Trans. CAD, vol. 9, no. 2, Feb. 1990. [19] J. Lam and J.M. Delosme, “Performance of a New Annealing Schedule,” Proc. 25th ACM/IEEE DAC, pp. 306311, 1988. [20] P.C. Maulik and L.R. Carley, “Automating Analog Circuit Design using Constrained Optimization Techniques”, Proc. IEEE ICCAD, pp. 390-393, Nov. 1991. [21] P.C. Maulik, L.R. Carley and D.J. Allstot, “Sizing of Cell-Level Analog Circuits Using Constrained Optimization Techniques”, IEEE JSSC, vol. SC-28, no. 3, March 1993. [22] Metasoft Corp. HSPICE manual, 1990. [23] T. Mukherjee, “Incorporating Manufacturing and Operating Point Related Considerations into Optimizationbased methods for Analog Circuit Synthesis”, Phd Prospectus, Carnegie Mellon University, Dec. 1992. [24] W. Nye, et al., “DELIGHT.SPICE: an optimization-based system for the design of integrated circuits,” IEEE Trans. CAD, vol. 7, no. 4, April 1988. [25] E.S. Ochotta, R.A. Rutenbar, and L.R. Carley, “Equation-Free Synthesis of High-Performance Linear Analog Circuits,” Proc. 1992 Brown/MIT Adv. Res. VLSI and Parallel Systems Conf., pp 129-143, The MIT Press, 1992. [26] E.S. Ochotta, R.A. Rutenbar, and L.R. Carley, “ASTRX/OBLX: Tools for Rapid Synthesis of High Performance Analog Circuits,” Proc. 31st ACM/IEEE DAC, pp. 24-30, June 1994. [27] E.S. Ochotta, L.R. Carley and R.A. Rutenbar, “Analog Circuit Synthesis for Large, Realistic Cells: Designing a Pipelined A/D Converter with ASTRX/OBLX”, Proc. IEEE CICC, pp. 365-368, May 1994. [28] E.S. Ochotta, “Synthesis of High-Performance Analog Cells in ASTRX/OBLX,” Ph.D thesis, Carnegie Mellon University, 1994. [29] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching properties of MOS transistors”, IEEE JSSC, vol. SC-24, no.5, Oct. 1989. [30] R.A. Rohrer, et al., “AWE Inspired,” Proc. IEEE CICC, pp. 18.1.1-8, May 1993. [31] R.A. Rohrer, “Fully Automated Network Design by Digital Computer: Preliminary Considerations”, Proceedings of the IEEE, vol. 55, no. 11, pp. 1929-1939, Nov. 1967. [32] F. Romeo and A. Sangiovanni-Vincintelli, “A Theoretical Framework for Simulated Annealing”, Algorithmica, 6: 302-345, 1991. [33] M.A. Styblinski and L.J. Opalski, “Algorithms and software tools of IC yield optimization based on fundamental fabrication parameters”, IEEE Trans. CAD, vol. 5, no. 1, Jan. 1986. [34] W. Swartz and C. Sechen, “New Algorithms for the Placement and Routing of Macrocells,” Proc. IEEE ICCAD, pp. 336-339, Nov. 1990. ICCAD94, Pages 594-597 A Statistical Optimization-Based Approach for Automated Sizing of Analog Cells F. Medeiro, F. V. Fernández, R. Domínguez-Castro and A. Rodríguez-Vázquez Dept. of Analog Circuit Design, Centro Nacional de Microelectrónica, Sevilla, SPAIN Abstract This paper presents a CAD tool for automated sizing of analog cells using statistical optimization in a simulation based approach. A nonlinear penalty-like approach is proposed to define a cost function from the performance specifications. Also, a group of heuristics is proposed to increase the probability of reaching the global minimum as well as to reduce CPU time during the optimization process. The proposed tool sizes complex analog cells starting from scratch, within reasonable CPU times (approximately 1hour for a fully differential opamp with 51 transistors), requiring no designer interaction, and using accurate transistor models to support the design choices. Tool operation and feasibility is demonstrated via experimental measurements from a working CMOS prototype of a folded-cascode amplifier. References [1] G. Gielen and W. Sansen: “Symbolic Analysis for Automated Design of Analog Integrated Circuits”. Kluwer, 1991. [2] W. Nye et al.: “DELIGHT.SPICE: An Optimization-Based System for the Design of Integrated Circuits”. IEEE Transactions on Computer-Aided Design, Vol. 7, pp. 501-519, April 1988. [3] “HSPICE User Manual”. Meta Software Inc. 1988. [4] P.J.M. van Laarhoven and E.H.L. Aarts: “Simulated Annealing: Theory and Applications”, Kluwer Academic Pub., 1987. [5] R. A. Rutenbar: “Simulated Annealing Algorithms: An Overview” IEEE Circuits and Devices Magazine, Vol. 5, pp. 19-26, January 1989. ICCAD94, Pages 598-603 Time-Domain non-Monte Carlo Noise Simulation for Nonlinear Dynamic Circuits with Arbitrary Excitations Alper Demir, Edward W.Y. Liu, Alberto L. Sangiovanni-Vincentelli Department of Electrical Engineering & Computer Sciences, University of California, Berkeley, CA 94720 Abstract A new, time-domain, non-Monte Carlo method for computer simulation of electrical noise in nonlinear dynamic circuits with arbitrary excitations is presented. This time-domain noise simulation method is based on the results from the theory of stochastic differential equations. The noise simulation method is general in the sense that any nonlinear dynamic circuit with any kind of excitation, which can be simulated by the transient analysis routine in a circuit simulator, can be simulated by our noise simulator in time-domain to produce the noise variances and covariances of circuit variables as a function of time, provided that noise models for the devices in the circuit are available. Noise correlations between circuit variables at different time points can also be calculated. Previous work on computer simulation of noise in integrated circuits is reviewed with comparisons to our method. Shot, thermal and flicker noise models for integratedcircuit devices, in the context of our timedomain noise simulation method, are described. The implementation of this noise simulation method in a circuit simulator (SPICE) is described. Two examples of noise simulation (a CMOS ring-oscillator and a BJT active mixer) are given. References [1] P.R. Gray and R.G. Meyer. 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Sugawara, “Numerical Noise Analysis for Nonlinear Circuits with a Periodic Large Signal Excitation Including Cyclostationary Noise Sources”,IEEE Transactions on Circuits and Systems-1: Fundamental Theory and Applications, vol. 40, No. 9, p. 581, September 1993. [7] P. Bolcato and R. Poujois, “A New Approach for Noise Simulation in Transient Analysis”, Proc. IEEE International Symposium on Circuits and Systems,p. 887, 1992. [8] A. Jordan and N. Jordan, “Theory of Noise in Metal Oxide Semiconductor Devices”, IEEE Transactions on Electron Devices,p. 148-156, March 1965. [9] B. Pellegrini, R. Saletti, B. Neri and P. Terreni, “ Noise Generators”, in Noise in Physical Systems and Noise, p. 425, 1985. [10] A.L. Sangiovanni-Vincentelli, “Circuit Simulation”, in Computer Design Aids for VLSI Circuits, The Netherlands, Sijthoff & Noordhoff, 1980. [11] L. Arnold. Stochastic Differential Equations: Theory and Applications. John Wiley & Sons. 1974. [12] P.E. Kloeden and E. Platen. Numerical Solution of Stochastic Differential Equations. Berlin; New York: Springer-Verlag, 1992. [13] V.S. Pugachev and I.N. Sinitsyn.Stochastic Differential Systems: Analysis and Filtering. Chichester, Susses; New York: Wiley, 1987. [14] T.L. Quarles. Analysis of Performance and Convergence Issues for Circuit Simulation. Ph.D. Thesis. U.C. Berkeley, April 1989. [15] A. Demir, E. Liu, A.L. Sangiovanni-Vincentelli and Iasson Vassiliou, “Behavioral Simulation Techniques for Phase/Delay-Locked Systems”, Proc. IEEE Custom Integrated Circuits Conference, p. 453, May 1994. [16] A. Demir. Time-Domain non-Monte Carlo Noise Simulation for Nonlinear Dynamic Circuits with Arbitrary Excitations. M.S. Project. Technical Report UCB/ERL M94/39, U.C. Berkeley, May 1994. [17] E. Tomacruz, J. Sanghavi and A. Sangiovanni-Vincentelli, “A Parallel Iterative Linear Solver for Solving Irregular Grid Semiconductor Device Matrices”, Supercomputing ‘94, 1994. ICCAD94, Pages 606-609 Improving Over-The-Cell Channel Routing In Standard Cell Design Xiaolin Liu and Ioannis G. Tollis Dept. of Computer Science, The Univ. of Texas at Dallas, Richardson, TX 75083–0688 xliu@utdallas.edu, tollis@utdallas.edu Abstract The first stage of over-the-cell routing in the horizontally connected vertically connected (HCVC) model is formulated as follows: Given two rows of terminals, find a planar routing to connect a subset of nets (with weights) on each row of terminals using a fixed number of tracks to maximize the total weight. This problem is called the two row fixed height planar routing (TFPR) problem [CPL93]. The complexity of the TFPR problem was unknown up to now. An approximation algorithm for the TFPR problem was presented in [CPL93]. In this paper we present a O(n2* h2) time algorithm to solve the TFPR problem optimally, where n is the number of terminals and h is the height of the standard cells. Our algorithm can be used to improve the performance of several over-the-cell channel routers including the ones in [CPL93] and [HSS93]. References [CL90] J. Cong and C.L.Liu, “Over-the-cell Channel Routing”, IEEE Trans. on CAD, vol.9, no.4, pp.408–418, April 1990. [CPL93] J.Cong, B. Preas, and C.L. Liu, “Physical Models and Efficient Algorithms for Over-the-cell Routing in Standard Cell Design”, IEEE Trans. on CAD, vol. 12, no.5, pp. 723–734, 1993. [DSMP94] S. Danda, N. Sherwani, S. Madhwapathy, and A. Panyam “An Optimal Algorithm for the Two Row Maximum Planar Subset Problem,” Manuscript 1994. [GN87] G. Gudmundsson, and S. Ntafos, “Channel Routing with Superterminals”, Proc. 25th Allerton Conf., pp. 375–376, 1987. [HSS93] N.D Holmes, N. Sherwani, and M. Sarrafzadeh, “Utilization of Vacant Terminals for Improved over-thecell channel routing”, IEEE Trans. on CAD, vol.12, no.6, pp.780–792, 1993. [LT94] X. Liu and I.G. Tollis, “Improving Over-The-Cell Channel Routing in Standard Cell Design,” Tech. Rep. UTDCS-9–94, Jan. 1994. [LPHL91] M. Lin, H. Perng, C.Hwang, and Y.Lin, “Channel Density Reduction by Routing Over The Cells”, Proc. 28th DAC, pp. 120–125, 1991. [RF82] R.L. Rivest and C. M. Fiduccia, “ A ‘Greedy’ Channel Router ”, Proc. 19th DAC., pp. 418–424, 1982. [SS87] Y. Shiraishi and Y. Sakemi, “A Permeation Router”, IEEE Trans. on CAD, vol, CAD-6, pp. 462–471, May 1987. ICCAD94, Pages 610-615 Minimum Crosstalk Switchbox Routing Tong Gao and C. L. Liu Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, Illinois, 61801 Abstract As technology advances, interconnection wires are placed in closer proximity. Consequently, reduction of crosstalks between interconnection wires becomes an important consideration in VLSI design. In this paper, we study the gridded switchbox routing problems with the objectives of satisfying crosstalk constraints and minimizing the total crosstalk in the nets. We propose a new approach to the problems which utilizes existing switchbox routing algorithms and improves upon the routing results by re-assigning the horizontal and vertical wire segments to rows and columns, respectively, in an iterative fashion. This approach can also be applied to the channel routing problem with crosstalk constraints. A novel mixed ILP formulation and effective procedures for reducing the number of variables and constraints in the mixed ILP formulation are then presented. The experimental results are encouraging. References [1] H. H. Chen and C. K. Wong. Wiring and Crosstalk Avoidance in Multi-Chip Module Design. In Proc. Custom Integrated Circuits Conference, pages 28.6.1-28.6.4, 1992. [2] W. M. Dai, R. Kong, J. Jue, and M. Sato. Rubber Band Routing and Dynamic Data Representation. In Proc. International Conference on Computer-Aided Design, pages 52-55, 1990. [3] T. Gao and C. L. Liu. Minimum Crosstalk Channel Routing. In Proc. International Conference on ComputerAided Design, pages 692-696, 1993. ICCAD94, Pages 616-619 Techniques for Crosstalk Avoidance in the Physical Design of High-Performance Digital Systems Desmond A. Kirkpatrick, Alberto L. Sangiovanni-Vincentelli Department of EECS, University of California, Berkeley, CA 94720 Abstract Interconnect performance does not scale well into deep submicron dimensions, and the rising number of analog effects erodes the digital abstraction necessary for high levels of integration. In particular, crosstalk is an analog phenomenon of increasing relevance. To cope with the increasingly analog nature of highperformance digital systemdesign, we propose using a constraintdrivenmethodology. In this paper we describe new constraint generation ideas incorporating digital sensitivity. In constraint-driven synthesis, we show that a fundamental subproblem of crosstalk channel routing, coupling-constrainedgraph levelization (CCL), is NPcomplete, and develop a novel heuristic algorithm. To demonstrate the viability of our methodology, we introduce a gridless crosstalk-avoiding channel router as an example of a robust and truly constraint-driven synthesis tool. References [1] T. Gao and C. L. Liu. Minimum crosstalk channel routing. In Digest of Technical Papers of the 1993 IEEE International Conference on Computer–Aided Design, 1993. [2] K. Chaudhary, A. Onozawa, and E. S. Kuh. A spacing algorithm for performance enhancement and cross-talk reduction. In Digest of Technical Papers of the 1993 IEEE International Conference on Computer–Aided Design, 1993. [3] Henry Chang, Alberto L. Sangiovanni-Vincentelli, Felice Balarin, et al. A top-down, constraint-driven designmethodology for analog integrated circuits. In Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, New York, NY, USA, pages 8.4/1–6, 1992. [4] U. Choudhury and A. Sangiovanni-Vincentelli. Constraint-based channel routing for analog and mixed analog/digital circuits. In Digest of Technical Papers of the 1990 IEEE International Conference on Computer– AidedDesign, 1990. [5] H. H. Chen and E. S. Kuh. Glitter: A gridless variable-width channel router. IEEE Transactions on Computer– Aided Design of Integrated Circuits and Systems, 5(4):459–465, October 1986. [6] M. R. Garey and D. S. Johnson. Computers and Intractability. W. H. Freeman and Co., 1979. ICCAD94, Pages 622-627 Efficient Breadth-First Manipulation of Binary Decision Diagrams Pranav Ashar, Matthew Cheong C&C Research Labs, NEC USA, Princeton, NJ 08540 Abstract We propose new techniques for efficient breadth-first iterative manipulation of ROBDDs. Breadth-first iterative ROBDD manipulation can potentially reduce the total elapsed time by multiple orders of magnitude compared to the conventional depth-first recursive algorithms when the memory requirement exceeds the available physical memory. However, the breadthfirst manipulation algorithms proposed so far [5] have had a large enough overhead associated with them to make them impractical. Our techniques are geared towards minimizing the overhead without sacrificing the speed up potential. Experimental results indicate considerable success in that regard. References [1] K. Brace, R. Rudell, and R. Bryant. An efficient implementation of a BDD package. In The Proceedings of the Design Automation Conference, pages 40–45, June 1990. [2] R. Bryant. Graph-based algorithms for Boolean function manipulation. In IEEE Transactions on Computers, volume C-35, pages 677–691, August 1986. [3] D. Long. ROBDD Package. CarnegieMellon University, 1993. [4] S. Malik, A. R. Wang, R. Brayton, and A. Sangiovanni-Vincentelli. LogicVerification usingBinaryDecisionDiagrams in a Logic Synthesis Environment. In Proceedings of the International Conference on Computer-AidedDesign, pages 6–9, November 1988. [5] H.Ochi, K.Yasuoka, and S.Yajima. Breadth-firstmanipulation of very large binary-decision diagrams. In Proceedings of the International Conference on Computer-Aided Design, pages 48–55, November 1993. [6] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Proceedings of the International Conference on Computer-Aided Design, pages 42–47, November 1993. [7] R. Rudell. Personal Communication. 1994. ICCAD94, Pages 628-631 Symmetry Detection and Dynamic Variable Ordering of Decision Diagrams Shipra Panda, Fabio Somenzi Dept. of Electrical and Computer Engineering, University of Colorado at Boulder Bernard F. Plessier Motorola Inc., Austin, TX Abstract Knowing that some variables are symmetric in a function has numerous applications; in particular, it can help produce better variable orders for Binary Decision Diagrams (BDDs) and related data structures (e.g., Algebraic Decision Diagrams). It has been conjectured that there always exists an optimum order for a BDD wherein symmetric variables are contiguous. We propose a new algorithm for the detection of symmetries, based on dynamic reordering, and we study its interaction with the reordering algorithm itself. We show that combining sifting with an efficient symmetry check for contiguous variables results in the fastest symmetry detection algorithm reported to date and produces better variable orders for many BDDs. The overhead on the sifting algorithm is negligible. References [1] R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi. Algebraic decision diagrams and their applications. In Proceedings of the International Conference on Computer-Aided Design, pages 188-191, Santa Clara, CA, November 1993. [2] K. S. Brace, R. L. Rudell, and R. E. Bryant. Efficient implementation of a BDD package. In Proceedings of the 27th Design Automation Conference, pages 40-45, Orlando, FL, June 1990. [3] N. Calazans, Q. Zhang, R. Jacobi, B. Yernaux, and A.-M. Trullemans. Advanced ordering and manipulation techniques for binary decision diagrams. In Proceedings of the European Conference on Design Automation, pages 452-457, Brussels, Belgium, March 1992. [4] D. I. Cheng and M. Marek-Sadowska. Verifying equivalence of functions with unknown input correspondence. In Proceedings of the European Conference on Design Automation, pages 81-85, Paris, France, February 1993. [5] E. Felt, G. York, R. K. Brayton, and A. Sangiovanni-Vincentelli. Dynamic variable reordering for BDD minimization. In Proceedings of the European Design Automation Conference, pages 130-135, Hamburg, Germany, September 1993. [6] M. Fujita, Y. Matsunaga, and T. Kakuda. On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. In Proceedings of the European Conference on Design Automation, pages 50-54, Amsterdam, February 1991. [7] N. Ishiura, H. Sawada, and S. Yajima. Minimization of binary decision diagrams based on exchanges of variables. In Proceedings of the International Conference on Computer-Aided Design, pages 472-475, Santa Clara, CA, November 1991. [8] S.-W. Jeong, T.-S. Kim, and F. Somenzi. An efficient method for optimal BDD ordering computation. In International Conference on VLSI and CAD (ICVC'93), Taejon, Korea, November 1993. [9] Y.-T. Lai and S. Sastry. Edge-valued binary decision diagrams for multi-level hierarchical verification. In Proceedings of the Design Automation Conference, pages 608-613, Anaheim, CA, June 1992. [10] S. Malik, A. Wang, R. Brayton, and A. Sangiovanni-Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 6-9, Santa Clara, CA, November 1988. [11] S.-I. Minato. Zero-suppressed BDDs for set manipulation in combinatorial problems. In Proceedings of the Design Automation Conference, pages 272-277, Dallas, TX, June 1993. [12] D. Möller, J. Mohnke, and M. Weber. Detection of symmetry of boolean functions represented by ROBDDs. In Proceedings of the International Conference on Computer-Aided Design, pages 680-684, Santa Clara, CA, November 1993. [13] B. F. Plessier. A General Framework for Verification of Sequential Circuits. PhD thesis, University of Colorado at Boulder, Dept. of Electrical and Computer Engineering, 1993. [14] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Proceedings of the International Conference on Computer-Aided Design, pages 42-47, Santa Clara, CA, November 1993. [15] C. E. Shannon. A symbolic analysis of relay and switching circuits. AIEE Trans., 57:713-723, 1938. [16] C. C. Tsai and M. Marek-Sadowska. Detecting symmetric variables in boolean functions using generalized Reed-Muller forms. In Proceedings of the International Symposium on Circuits and Systems, London, Britain, May 1994. ICCAD94, Pages 632-637 A Redesign Technique for Combinational Circuits Based on Gate Reconnections Yuji Kukimoto, Masahiro Fujita1, Robert K. Brayton 1 University of California, Berkeley, CA 94720 Fujitsu Laboratories of America, San Jose, CA 95134 Abstract In this paper,we consider a redesign technique applicable to combinational circuits implemented with gate-array or standard-cell technology, where we rectify an existing circuit only by reconnecting gates on the circuit with all the gate types unchanged. This constraint allows us to reuse the original placement as is, thereby speeding up the total time needed for a redesign. We formulate this problem as a Boolean-constraint problem and give a BDD-based algorithm to check the feasibility of redesign. References [1] M. Fujita. A method for automatic design error correction in sequential circuits. In Proceedings of the European Conference on Design Automation(EDAC-93), pages 76–80, February 1993. [2] M. Fujita, T. Kakuda, and Y. Matsunaga. Redesign and automatic error correction of combinational circuits. In Proceedings of the IFIP TC10/WG10.5 Workshop on Logic and Architecture Synthesis, pages 253–262. North Holland, May 1990. [3] M. Fujita, Y. Tamiya, Y. Kukimoto, and K.-C. Chen. Application of Boolean unification to combinational logic synthesis. In Proceedings of IEEE International Conference on Computer-Aided Design, pages 510–513,November 1991. [4] N. Ishiura. Private communication, April 1994. [5] Y. Kukimoto andM. Fujita. Rectification method for lookuptable type FPGA’s. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pages 54–61, November 1992. [6] B.Lin and F. Somenzi.Minimization of symbolic relations. In Proceedings of IEEE InternationalConferenceon Computer-Aided Design, pages 88–91, November 1990. [7] S. Muroga and T. Ibaraki. Design of optimal switching networks by integer programming. IEEE Transactions on Computers, C-21:573–582, June 1972. [8] S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney. The Transduction method – design of logic network based on permissible functions. IEEE Transactions on Computers, 38(10):1404–1424,October 1989. [9] Y. Watanabe and R. K. Brayton. Incremental synthesis for engineering changes. In Proceedings of IEEE International Conference onComputerDesign,pages 40–43,October 1991. ICCAD94, Pages 640-645 Non-Scan Design-For-Testability of RT-Level Data Paths Sujit Dey and Miodrag Potkonjak C&C Research Laboratories, NEC USA, Princeton, NJ 08540 Abstract This paper presents a non-scan design-for-testability technique applicable to register-transfer (RT) level data path circuits, which are usually very hard-to-test due to the presence of complex loop structures. We develop a new testability measure, and utilize the RT-level structure of the data path, for cost-effective re-design of the circuit tomake it easily testable, without having to either scan any flip-flop or break loops directly. The non-scanDFT technique was applied to several data path circuits. Experimental results demonstrate the feasibility of producing non-scan testable data paths, which can be tested at-speed. The hardware overhead and the test application time required for the non-scan designs is significantly lower than the corresponding partial scan designs. REFERENCES [1] S. S. K. Chiu and C. Papachristou. A Built-In Self-Testing Approach For Minimizing Hardware Overhead. In Proceedings of the International Conference on Computer Design, 1991. [2] L. Avra. Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths. In Proceedings of the International Test Conference, 1991. [3] L. Avra and E. McCluskey. Synthesizing for Scan Dependence in Built-In Self-Testable Designs. In Proc. ITC, pages 734 – 743, October 1993. [4] C.-H. Chen and D. G. Saab. Behavioral Synthesis for Testability. In Proc. ICCAD, pages 612 – 615, November 1992. [5] T. C. Lee, N. K. Jha, andW. H.Wolf. Behavioral Synthesis of Highly Testable Data Paths underNon-Scan and Partial Scan Environments. In Proc. Design Automation Conf., pages 292–297, 1993. [6] S. Dey,M. Potkonjak, andR. Roy. ExploitingHardware Sharing in High Level Synthesis for Partial Scan Optimization. In Proceedings of the International Conference on Computer-Aided Design, pages 20 – 25, November 1993. [7] S. Dey and M. Potkonjak. Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs. In Proc. ITC, October 1994. [8] S. Bhattacharya, F. Brglez, and S. Dey. Transformations and Resynthesis for Testability of RT-Level ControlData Path Specifications. IEEE Transactions on VLSI Systems, 1(3):304–318,September 1993. [9] V. Chickermane, J. Lee, and J. H. Patel. A Comparative Study of Design for Testability Methods Using HighLevel and Gate-Level Descriptions. In Proc. ICCAD, pages 620 – 624, November 1992. [10] H. Harmanani and C. Papachristou. An ImprovedMethod for RTL Synthesis with Testability Tradeoffs. In Proc. ICCAD, pages 30 – 35, November 1993. [11] S.M. Reddy and R. Dandapani. Scan Design Using Standard Flip-Flops. IEEE Design and Test, pages 52 – 54, Feb 1987. [12] S. Narayanan and M.A. Breuer. Reconfigurable Scan Chains: A Novel Approach To Reduce Test Application Time. In Proc. of ICCAD, pages 710 – 715, 1993. [13] P.C. Maxwell, R.C. Aitken, V. Johansen, and I. Chiang. The Effect ofDifferent Test Sets On Quality Level Prediction: When is 80% Better Than 90%? In Proc. of the Intl Test Conference, pages 358 – 364, Oct 1991. [14] V. Chickermane, E.M. Rudnick, P. Banerjee, and J. H. Patel. Non-Scan Design-for-Testability Techniques for Sequential Circuits. In Proc. Design Automation Conf., pages 236 – 241, June 1993. [15] J. Rabaey, C. Chu, P. Hoang, and M. Potkonjak. Fast Prototyping of Data Path Intensive Architectures. IEEE Design and Test, pages 40 – 51, 1991. [16] K.T. Cheng and V.D. Agrawal. A Partial Scan Method for Sequential Circuits with Feedback. IEEE Transactions on Computers, 39(4):544 – 548, April 1990. [17] D.H. Lee and S.M.Reddy. OnDeterminingScan Flip-Flops in Partial-Scan Designs. In Proceedings of the InternationalConference on Computer-Aided Design, pages 322 – 325, November 1990. [18] V. Chickermane and J. H. Patel. A Fault Oriented Partial Scan Design Approach. In Proceedings of the InternationalConference on Computer-Aided Design, pages 400 – 403, November 1991. [19] T. M. Niermann and J. H. Patel . HITEC:A Test Generation Package for Sequential Circuits. In Proc. EDAC, pages 214–218, 1991. [20] S. Dey andM. Potkonjak. Non-ScanDesign-for-Testabilityof RT-Level Data Paths. Technical Report 94C008,C&C Research Labs, NEC USA, May 1994. [21] R.A. Haddad and T.W. Parsons. Digital Signal Processing: Theory, Applications and Hardware. Computer Science Press, New York, NY, 1991. [22] E.M. Sentovich,K.J. Singh,C. Moon,H. Savoj,R.K. Brayton, and A. Sangiovanni-Vincentelli. Sequential Circuit Design using Synthesis and Optimization. In Proceedings of the InternationalConference on Computer Design, October 1992. [23] S. Yang. Logic Synthesis and Optimization Benchmarks, User Guide Version 3.0. In International Workshop on Logic Synthesis, MCNC, Research Triangle Park, NC, May 1991. ICCAD94, Pages 646-650 Selecting Partial Scan Flip-Flops for Circuit Partitioning Toshinobu Ono NEC Corporation, Kawasaki, JAPAN Abstract This paper presents a new method of selecting scan flip-flops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned into many small subcircuits which can be dealt with separately by a test pattern generator. This permits easy automatic test pattern generation for arbitrarily large sequential circuits. Algorithms of selecting scan FFs to allow such partitioning and of scheduling tests for subcircuits are given. Experimental results show that the proposed method makes it possible to generate test patterns for extra large sequential circuits which previous approaches cannot deal with. References [1] E. Trischler, “Incomplete Scan Path with an Automatic Test Generation Methodology", International Test Conf., pp.153-162, 1980. [2] R. Gupta, R. Gupta and M. A. Breuer, “BALLAST: A Methodology for Partial Scan Design", International Symp. on Fault-Tolerant Computing, pp.118-125, June 1989. [3] K.-T. Cheng and V. D. Agrawal, “A Partial Scan Method for Sequential Circuits with Feedback", IEEE Trans. Computers, Vol.39, No.4, pp.544-548, April 1990. [4] V. Chickermane and J. H. Patel, “An Optimization Based Approach to the Partial Scan Design Problem ", International Test Conf., pp.377-386, September 1990. [5] K. S. Kim and C. R. Kime, “Partial Scan by Use of Empirical Testability", International Conf. on ComputerAided Design, pp.314-317, November 1990. [6] D. S. Lee and S. M. Reddy, “On Determining Scan Flip-Flops in Partial-Scan", International Conf. on ComputerAided Design, pp.322-325, November 1990. [7] S. Park and S. B. Akers, “A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination", International Test Conf., pp.303-311, September 1992. [8] P. Ashar and S. Malik, “Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications", Design Automation Conf., pp.77-80, June 1994. [9] S. T. Chakradhar, A. Balakrishnan and V. D. Agrawal, “An Exact Algorithm for Selection Partial Scan FlipFlops", Design Automation Conf., pp.81-86, June 1994. [10] F. Brglez, D. Bryan and K. Kozminski, “Combinational Profiles of Sequential Benchmark Circuits", International Symp. on Circuits and Systems, pp.1929-1934, May 1989. [11] T. Niermann and J. H. Patel, “HITEC: A Test Generation Package for Sequential Circuits", European Design Automation Conf., pp.214-218, March 1991. ICCAD94, Pages 651-654 Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection Nur A. Touba and Edward J. McCluskey Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA 94305-4055 Abstract This paper presents new logic synthesis techniques for generating multilevel circuits with concurrent error detection based on a parity-check code scheme that can detect all errors caused by single stuck-at faults. These synthesis techniques fully automate the design process and allow for a better quality result than previous methods thereby reducing the cost of concurrent error detection. An algorithm is described for selecting a good parity-check code for encoding the outputs of a circuit. Once the code has been chosen, a new procedure called structureconstrained logic optimization is used to minimize the area of the circuit as much as possible while still using a circuit structure that ensures that single stuck-at faults cannot produce undetected errors. The implementation that is generated is path fault secure and when augmented by a checker forms a self-checking circuit. Results indicate that self-checking multilevel circuits can be generated which require significantly less area than using duplication. References [1] Brayton, R.K., R. Rudell, A. Sangiovanni-Vincentelli, A.R. Wang, “MIS: A Multiple-Level Logic Optimization System,” IEEE Trans. Comp.-Aided Design, pp. 1062-1081, Nov. 1987. [2] Brayton, R.K., R. Rudell, A. Sangiovanni-Vincentelli, A.R. Wang, “Multi-Level Logic Optimization and The Rectangular Covering Problem,” Proc. of ICCAD, pp. 66-69, 1987. [3] De, K., C. Natarajan, D. Nair, and P. Banerjee, “RSYN: A System for Automated Synthesis of Reliable Multilevel Circuits,” IEEE Transactions on VLSI Systems, pp. 186-195, Jun. 1994. [4] Detjens, E., G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, “Technology Mapping in MIS,” Proc. of Int. Conf. on Computer-Aided Design (ICCAD), pp. 116-119, 1987. [5] Gupta, S.K., and D.K. Pradhan, “Can Concurrent Checkers Help BIST?,” Proc. of International Test Conf., pp. 140-150, 1992. [6] Hughes, J.L.A., E.J. McCluskey, and D.J. Lu, “Design of Totally Self-Checking Comparitors with an Arbitrary Number of Inputs,” IEEE Transactions on Computers, pp. 546-550, Jun. 1984. [7] Jha, N.K., and S.-J. Wang, “Design and Synthesis of Self-Checking VLSI Circuits and Systems,” IEEE Transactions on Computer-Aided Design, pp. 878-887, Jun. 1993. [8] Keutzer, K., “Dagon: Technology Binding and Local Optimization by DAG Matching,” Proc. of the 24th Design Automation Conference, pp. 341-347, 1987. [9] Khakbaz, J., “Self-Testing Embedded Parity Trees”, Proc. of FTCS-12, pp. 109-116, 1982. [10] Khodadad-Mostashiry B., “Break Faults in Circuits with Parity Prediction,” Tech. Note No. 183, CRC, Stanford University, Stanford, CA, Dec. 1980. [11] Leveugle R., “Optimized State Assignment of Single Fault Tolerant FSMs Based on SEC Codes”, Proc. of the 30th Design Automation Conference, pp.-14-18, 1993. [12] Rajski, J., and J. Vasudevamurthy, "The Testability-Preserving Concurrent Decomposition and Factorization of Boolean Expressions," IEEE Trans. on CAD, pp. 778-793, Jun. 1992. [13] Sechen C., and A. Sangiovanni-Vincentelli, “TimberWolf3.2: A New Standard Cell Placement and Global Routing Package”, Proc. of the 30th Design Automation Conference, pp. 432-439, 1986. [14] Sedmak, R.M., “Design for Self-Verification: An Approach for Dealing with Testability Problems in VLSIBased Designs”, Proc. of International Test Conference, pp. 112-120, 1979. [15] Smith, J.E., and G. Metze, “Strongly Fault Secure Logic Networks,” IEEE Trans. on Computers, pp. 491-499, Jun. 1978. [16] Touba, N.A., and E.J. McCluskey, "Logic Synthesis for Concurrent Error Detection", Technical Report No. 936, CRC, Stanford University, Stanford, CA, Nov. 1993. ICCAD94, Pages 656-663 Macromodeling of Analog Circuits for Hierarchical Circuit Design Jianfeng Shao and Ramesh Harjani Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455, USA Abstract Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A modified simplicial approximation technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. However, due to lack of space, only details of the performance macromodeling techniques are included. Macromodels are developed and verified for analog blocks at three different levels of hierarchy (current mirror, opamp, and A/D converter). References [1] R. Harjani, R. A. Rutenbar, and L. R. Carley, “OASYS a framework for analog circuit syntheis," IEEE Tran. CAD, Dec. 1989. [2] S. W. Director and G. D. Hachtel, “The simplicial approach to design centering," IEEE Tran. CAS, Jul. 1977. [3] R. K. Brayton, G. D. Hachtel, and A. S. Vincentelli, “A survey of optimization techniques for integrated-circuit design," Proceedings of IEEE, Oct. 1981. [4] K. K. Low, A Methodology for Statistical Integrated Circuit Design. PhD thesis, Carnegie Mellon University, Pittsburgh, 1989. [5] J. Shao and R. Harjani, “Feasibility region modeling of analog circuits for hierarchical circuit design," in IEEE MWSCS, 1994. [6] Y. Aoki, H. Masuda, S. Shimada, and S. Sato, “A new design centering methodology for vlsi device development," IEEE Tran. CAD, May 1987. [7] A. R. Alvarez, et. al., “Application of statistical design and response surface methods to computer-aided VLSI device design," IEEE Tran. CAD, Feb. 1988. [8] T. Yu, S. Kang, I. Hajj, and T. Trick, “Statistical performance modeling and parametric yeild estimation of MOS VLSI," IEEE Tran. CAD, Nov. 1987. [9] P. Cox, et. al., “Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits," IEEE Tran. ED, Feb 1985. [10] C. Shyamsundar, “Mulreg - user's manual," technical report, Carnegie Mellon University, 1986. [11] G. Box, W. Hunter, and J. Hunter, Statistics for Experimenters: an Introduction to Design Data Analysis and Model Building. John Wiley, 1978. [12] M. Powell, “Radial basis functions for multivariable integration: A review," in IMA Conference on Algorithm and Approximations and Data, RMCS, 1985. [13] E. S. Ochotta, R. A. Rutenbar, and L. R. Carley, “ASTRX/OBLX: Tools for rapid synthesis of highperformance analog circuits," in ACM/IEEE DAC, 1994. ICCAD94, Pages 664-671 Approximate Symbolic Analysis of Large Analog Integrated Circuits Qicheng Yu and Carl Sechen Department of Electrical Engineering, FT-10, University of Washington, Seattle, WA 98195 Abstract This paper describes a unified approach to the approximate symbolic analysis of large linearized analog circuits. It combines two new approximation-during-computation strategies with a variation of the classical two-graph tree enumeration method. The first strategy is to generate common trees of the two-graphs, and therefore the product terms in the symbolic network function, in the decreasing order of magnitude. The second approximation strategy is the sensitivity-based simplification of two-graphs, which excludes from the two-graphs many circuit elements that have little effect on the network function being derived. Our approach is therefore able to symbolically analyze much larger analog integrated circuits than previous reported, using complete small signal models for the semiconductor devices. We show accurate yet reasonably sized symbolic network functions for integrated circuits with up to 39 transistors whereas previous approaches were limited to less than 15. References [1] M. Amadori, R. Guerrieri and E. Malavasi, “Symbolic Analysis of Simplified Transfer Functions,” Analog Integ. Circuits Sig. Processing, Vol. 3, No. 1, pp. 9-29, 1993. [2] S.-M. Chang, J. F. MacKay and G. M. Wierzba, “Matrix reduction and numerical approximation during computation techniques for symbolic analog circuit analysis,” Proc. IEEE ISCAS, 1992, pp. 1153-1156. [3] C. S. Chiang, A Perturbation Approach to the Symbolic Analysis of Analog Circuits, Ph.D. Dissertation, Yale University, New Haven, 1992. [4] L. O. Chua and P. M. Lin, Computer-aided Analysis of Electronic Circuits: Algorithms and Techniques, Englewood Cliffs, New Jersey: Prentice-Hall, 1975. [5] T. H. Cormen, C. E. Leiserson and R. L. Rivest, Introduction to Algorithms, Cambridge, Massachusetts: The MIT Press, 1990. [6] F. V. Fernandez, A. Rodriguez-Vazquez and J. L. Huertas, “Interactive AC modeling and characterization of analog circuits via symbolic analysis,” Analog Integ. Circuits Sig. Processing, Vol. 1, No. 3, pp. 183-208, 1991. [7] F. V. Fernandez, A. Rodriguez-Vazquez, J. D. Martin and J. L. Huertas, “Formula Approximation for Flat and Hierarchical Symbolic Analysis,” Analog Integ. Circuits Sig. Processing, Vol. 3, No. 1, pp. 43-58, 1993. [8] H. N. Gabow, “Two algorithms for generating weighted spanning trees in order,” SIAM J. Computing, Vol. 6, pp. 139-150, Mar. 1977. [9] G. Gielen, H. Walscharts, W. Sansen, “ISAAC: a symbolic simulator for analog integrated circuits,” IEEE J. Solid-State Circuits, Vol. SC-24, pp. 1587-1597, Dec. 1989. [10] G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits, Boston: Kluwer Academic Publishers, 1991. [11] G. Gielen, P. Wambacq and W. Sansen, “Symbolic analysis methods and applications for analog circuits: a tutorial overview,” Proc. IEEE, Vol. 82, pp. 287-304, Feb. 1994. [12] M. M. Hassoun and P. M. Lin, “A new network approach to symbolic simulation of large-scale networks,” Proc. IEEE ISCAS, 1989, pp. 806-809. [13] M. M. Hassoun and K. S. McCarville, “Symbolic Analysis of largescale networks using a hierachical signal flowgraph approach,” Analog Integ. Circuits Sig. Processing, Vol. 3, No. 1, pp. 31-42, 1993. [14] J.-J. Hsu and C. Sechen, “Low-frequency symbolic analysis of large analog integrated circuits,” Proc. Custom Integ. Circuits Conf., 14.7.1-5, May 1993. [15] J.-J. Hsu and C. Sechen, “Fully symbolic analysis of large analog integrated circuits,” Proc. Custom Integ. Circuits Conf., pp. 457-460, May 1994. [16] A. Liberatore and S. Manetti, “SAPEC - a personal computer program for the symbolic analysis of electric circuits,” Proc. IEEE ISCAS, 1988, pp. 897-900. [17] P. M. Lin, Symbolic Network Analysis, Studies in Electrical and Electronic Engineering 41, New York: Elsevier, 1991. [18] W. Mayeda, Graph Theory, New York: Wiley-Interscience, 1972. [19] S. J. Seda, M. G. R. Degrauwe and W. Fichtner, “A symbolic analysis tool for analog circuit design automation,” IEEE/ACM ICCAD, Digest Tech. Papers, 1988, pp. 488-491. [20] S. J. Seda, M. G. R. Degrauwe and W. Fichtner, “Lazy-expansion symbolic expression approximation in SYNAP,” IEEE/ACM ICCAD, Digest Tech. Papers, 1992, pp. 310-317. [21] J. A. Starzyk and A. Konczykowska, “Flowgraph Analysis of Large Electronic Networks,” IEEE Trans. Circuits and Syst., Vol. CAS-33, pp. 302-315, Mar. 1986. [22] P. Wambacq, G. Gielen and W. Sansen, “A cancellation-free algorithm for the symbolic simulation of large analog circuits,” Proc. IEEE ISCAS, 1992, pp. 1157-1160. [23] P. Wambacq, F. V. Fernandez, G. Gielen and W. Sansen, “Efficient symbolic computation of approximated small-signal characteristics,” Proc. Custom Integ. Circuits Conf., pp. 461-464, May 1994. [24] W.-C. S. Wu et al, “Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges,” IEEE J. Solid-State Circuits, Vol. SC-29, pp. 63-66, Jan. 1994. [25] Q. Yu and C. Sechen, “Generation of color-constrained spanning trees with application in symbolic circuit analysis,” Proc. 4th Great Lakes Symp. VLSI, pp. 252-255, Mar. 1994. ICCAD94, Pages 672-678 Testing of Analog Systems Using Behavioral Models and Optimal Experimental Design Techniques Eric Felt, Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 Abstract This paper describesa new CAD algorithm which performs automatic test pattern generation (ATPG) for a general class of analog systems, namely those circuits which can be efficiently modeled as an additive combination of user-defined basis functions. The algorithm is based on the statistical technique of I-optimal experimental design, in which test vectors are chosen to be maximally independent so that circuit performance will be characterized as accurately as possible in the presence of measurement noise and model inaccuracies. This technique allows analog systems to be characterizedmore accurately and more efficiently, thereby significantly reducing system test time and hence total manufacturing cost. References [1] L. Bonet, J. Ganger, J. Girardeu,C. Greaves,M. Pendelton and D. Yatim, “Test features of theMC145472 ISDN U-transceiver”, Proc. 1990 International Test Conf., pp. 68–79, 1990. [2] Semiconductor Industry Technology Workshop Conclusions, Semiconductor Industry Association, 1993. [3] M.H.Schultz, E.Trischler andT.M.Sarfert, “SOCRATES: a highly efficient automatic test pattern generationsystem”, IEEE Trans. on CAD, vol. Vol. 7,No. 1, pp. 126–137, 1988. [4] A. Ghosh, S. Devadas and A. Richard Newton, Sequential Logic Testing and Verification, Kluwer, Boston, 1992. [5] G. Stenbakken and T. Souders, “Test-Point Selection and Testability Measures viaQR Factorizationof LinearModels”, IEEE Transactionson Instrumentation andMeasurement, June 1987. [6] T. Souders and G. Stenbakken, “Cutting the high cost of testing”, IEEE Spectrum, pp. 48–51,March 1991. [7] L. Milor and A. L. Sangiovanni-Vincentelli, “Minimizing production test time to detect faults in analog circuits”, IEEE Trans. on CAD, vol. Vol. 13,No. 6, pp. 796–813, June 1994. [8] J. Kiefer, Collected Papers III: Design of Experiments, Springer-Verlag, New York, 1985. [9] G. E. P. Box and N. R. Draper, Empirical Model-Building and Response Surfaces, Wiley, New York, 1987. [10] S.B. Crary, “Optimal design of experimentsfor sensor calibration”, Proc. IEEE International Conference on Solid-State Sensors and Actuators, pp. 404–407, 1991. [11] N. K. Nguyen and A. J. Miller, “A review of some exchange algorithms for constructing discrete D-optimal designs”, Computational Statistics and Data Analysis, vol. Vol. 14, pp. 489–498, 1992. [12] R. H. Hardin and N. J. A. Sloane, “A new approach to the construction of optimal designs”, Journal of Statistical Planning and Inference, vol. Vol. 37, pp. 339–369, 1993. [13] E. Liu, A. Sangiovanni-Vincentelli, G. Gielen and P. Gray, “A behavioral representation for nyquist rate A/D converters”, in Proc. IEEE ICCAD, pp. 386–389,November 1991. [14] A. Vladimirescu, A. R. Newton and D. O. Pederson, SPICE Version 2G.1 User’s Guide, Dept. of Electrical Engineering and Computer Sciences, Univ. of California, Berkeley, CA, 1980. [15] R. Hooke and T. A. Jeeves, “‘Direct Search’ solution of numerical and stastical problems”, J. Assoc. Comp. Machinery, vol. Vol. 8, pp. 212–229, 1961. [16] G. N. Stenbakken and T. M. Sounders, “Linear error modeling of analog and mixed-signal devices”, Proc. IEEEInternationalTest Converence, pp. 573–581, 1991. [17] E. W. Y. Liu, W. Kao, E. Felt and A. L. Sangiovanni-Vincentelli, “Analog testability analysis and fault diagnosis using behavioralmodeling”, Proc. IEEE Custom IntegratedCircuits Conference, 1994. [18] T.M. Sounders andG.N. Stenbakken, “Acomprehensive approach for modeling and testing analog and mixedsignal devices”, Proc. IEEE International Test Converence, pp. 169–174, 1990. ICCAD94, Pages 680-685 Layer Assignment for High-Performance Multi-Chip Modules Kai-Yuan Chao1, D. F. Wong2 1 Department of Electrical and Computer Engineering 2 Department of Computer Sciences University of Texas at Austin, Austin, Texas, 78712 Abstract In this paper, we present a layer assignment method for high-performance multi-chip module environments. In contrast with treating global routing and layer assignment separately, our method assigns nets to layers while considering preferable global routing topologies simultaneously. We take transmission line effects into account to avoid noise in high-speed circuit packages. The problem is formulated as a quadratic Boolean programming problem and an algorithm is presented to solve the problem after linearization. Our method is applied to a set of benchmark circuits to demonstrate the effectiveness. References [1] H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publ. Co., 1990. [2] E. Balas and J. B. Mazzola, "Quadratic 0-1 Programming by a New Linearization," Presented at the ORSA/TIMS National Meeting, Washington, D. C., 1980. [3] R. E. Burkard and T. Bonniger, "A Heuristic for Quadratic Boolean Programs with Applications to Quadratic Assignment Problems," Euro. J. of Operational Res., v. 13, pp. 374-386, 1983. [4] J. D. Cho, S. Raje, M. Sarrafzadeh, and et. al., "Crosstalk-Minimum Layer Assignment," Proc. of IEEE Custom Integrated Circuits Conf., pp. 29.7.1-29.7.4, 1993. [5] J. M. Ho, M. Sarrafzadeh, G. Vijayan and C. K. Wong, "Layer Assignment for Multichip Modules," IEEE trans. on CAD, v. 9, no. 12, pp. 1272-1277, 1990. [6] E. E. Davidson, P. W. Hardin, et. al., "Physical and Electrical Design Features of IBM Enterprise System/9000 Circuit Modules," IBM J. Res. Develop., v. 36, no. 5, 1992. [7] D. A. Joy and M. J. Ciesielski, "Layer Assignment for Printed Circuit Boards and Integrated Circuits, " Proc. of the IEEE, v. 80, no. 2, pp. 311-331, 1992. [8] K.-Y. Khoo and J. Cong, "An Efficient Multilayer MCM Router Based on Four-Via Routing," Proc. of the 30th DAC, pp. 590-595, 1993. [9] D. P. LaPotin, "Early Assessment of Design, Packaging and Technology Tradeoffs," Int'l J. of High Speed Electronics, v. 2, no. 4., 209-233, 1991. [10] M. Shih and E. S. Kuh, "Quadratic Boolean Programming for Performance-Driven System Partitioning," Proc. of the 30th DAC, pp. 761-765, 1993. [11] M. Sriram and S. M. Kang, "Detailed Layer Assignment for MCM Routing," Proc. of ICCAD, pp. 386-389, 1992. [12] D. Theune, R. Thiele, T. Lengauer, and A. Feldmann, "HERO: Hierarchical EMC-Constrained Routing," Proc. of I C C A D , p p . 4 6 8 - 4 7 2 , 1992. ICCAD94, Pages 686-689 The Reproducing Placement Problem with Applications Wei-Liang Lin, M. Sarrafzadeh, Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208 C. K. Wong Watson Research Center, IBM Corp., Yorktown Heights, NY 10598 Abstract We study a new placement problem: the reproducing placement problem (RPP). In each phase a module (or gate) is decomposed into two (or more) simpler modules. The goal is find a “good" placement in each phase. The problem, being iterative in nature, requires an iterative algorithm. The problem finds applications in several gate-level placement problems, e.g., in layout-driven logic synthesis. We introduce the notion of minimum floating Steiner trees (MFST). We employ an MFST algorithm as a central step in solving the RPP. A Hanan-like theorem is established for the MFST problem and two approximation algorithms are proposed. Experiments on commonly employed benchmarks verify the effectiveness of the proposed technique. References [CCMS93] D. I. Cheng, S. Chang, and M. Marek-Sadowska. “Partitioning Combinational Circuits in Graph and Logic Domains". In Proceedings of Synthesis And SImulation Meeting and International Interchange (SASIMI-93), 1993. [CKR+92] J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong. “Provably Good Performance-Driven Global Routing". IEEE Transactions on Computer Aided Design, 11(6):739-752, June 1992. [CWS92] C. Chiang, C. K. Wong, and M. Sarrafzadeh. “A Globar Router Based on Weighted Steiner Trees". Technical report, Northwestern University, 1992. to appear in IEEE Transactions on Computer –Aided Design, 1994. [GP87] G. Georgakopoulos and C. H. Papadimitriou. “The 1-Steiner Tree Problem". Journal of Algorithms, 8:122130, 1987. [KR92] A. Kahng and G. Robins. “A New Class of Iterative Steiner Tree Heuristics with Good Performance". IEEE Transactions on Computer Aided Design, 11(7):893-902, 1992. [LPP93] S. Liu, K. Pan, and M. Pedram. “Alleviating Routing Congestion by Combining Logic Resynthesis and Linear Placement". In European Design Automation Conference, pages 578-582, 1993. [PB91] M. Pedram and N. Bhat. “Layout Driven Technology Mapping". In Design Automation Conference, pages 99-105, 1991. [SM91] K. Shahookar and P. Mazumder. “VLSI Cell Placement Techniques". ACM Computing Surveys, 23(2):143220, June 1991. ICCAD94, Pages 690-695 RISA: Accurate and Efficient Placement Routability Modeling Chih-liang Eric Cheng Cadence Design Systems, Inc., San Jose, CA 95134 Abstract The prevalence of net list synthesis tools raises great concern on routability of cell placement created with state-of-the-art placement techniques. In this paper, an accurate and efficient placement routability modeling technique is proposed and incorporated into the prevailing simulated annealing approach. This accurate and efficient modeling is based on the supply versus demand analysis of routing resource over an array of regions on a chip. Vertical and horizontal routability is analyzed separately due to the bias of routing resource in multiple-metal-layer ASIC designs. A special technique on net bounding box partitioning is also proposed and critical to the accuracy of this modeling at the presence of mega cells, which tend to cause local routing congestion. By incorporating this efficient modeling into the cost function of simulated annealing, experiments conducted on small to large industrial designs indicate that placement routability evaluated with a global router is greatly improved as a result of the proposed accurate modeling. References [1] U. Lauther, “A Min-cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation”, Proceedings of DAC, pp1-10, 1979 [2] R.-S. Tsay, E. Kuh, and C.-P. Hsu, “PROUD: A Sea-of-gates Placement Algorithm”, IEEE Design & Test of Computers, pp44-56, 1988 [3] J.M. Kleinhans, G. Sigl, and F.M. Johannes, “GORDIAN: A New Global Optimization Rectangle Dissection Method for Cell Placement”, IEEE International Conf. on CAD, pp427-432, 1988 [4] W.-J. Sun and C. Sechen, “Efficient and Effective Placement for Very Large Circuits”, IEEE International Conf. on CAD, pp170-177, 1993 [5] M. Burstein and S.J. Hong, “Hierarchical VLSI Layout: Simultaneous Placement and Wiring of Gate Arrays” In VLSI 1983, pp45-60, 1983 [6] S. Mayrhofer and U. Lauther, “Congestion-Driven Placement Using a New Multi-partitioning Heuristic”, IEEE International Conf. on CAD, pp332-335, 1990 [7] R.-S Tsay, and S.C. Chang, “Early Wirability Checking and 2-D Congestion-Driven Circuit Placement”, IEEE International Conf. on ASIC, 1992 [8] Bryan Preas & Michael Lorenzetti, “Physical Design Automation of VLSI Systems”, 1988, pp.96-97. [9] W.-J. Sun & C. Sechen, “Efficient and Effective Placement for Very Large Circuits”, IEEE International Conference on CAD, 1993, pp.170-177 [10] J. Soukup, “Circuit Layout”, Proceedings of the IEEE, Vol.69, No.10, Oct. 1981. [11] G. Persky, “PRO - An Automatic String Placement Program for Polycell Layout”, IEEE Proceedings of the 13th DAC., p.353-361, 1977 [12] P. G. Karger & M. Malek.”Formulation of Component Placement as a Constrained Optimization Problem”, Proceedings of the ICCAD., p.814-819, 1984 [13] J. Jung, S. Goto & H. Hirayama, “A New Approach to the Two-dimensional Placement of Wire Congestion in Master-Slice LSI Layout Design”, Trans. Inst. of Electronics and Communications Engineers of Japan, vol J64-A, No.1, p55-62, 1981 [14] S. Goto & T. Mitsuda, “Partitioning, Assignment and Placement”, Advances in CAD for VLSI, Vol. 4: Layout Design and Verification, T. Ohtsuki, ed., Amsterdam, the Netherlands, North Holland, Chapter 5, 1986. [15] Y.-C. Wei, “Circuit Partitioning and its Applications to VLSI Designs”, Ph.D Thesis, UCSD CSE Dept.,September 1990. ICCAD94, Pages 698-701 A New Approach for Factorizing FSM's C. Rama Mohan Cadence Design Systems (India) Pvt Ltd SDF A-1/B-8, NEPZ, Noida-201305, India P.P. Chakrabarti Dept of Computer Science and Engg I.I.T, Kharagpur -721302, India Abstract Exact Factors as defined in [2], if present in an FSM can result in most effective way of factorization. However, it has been found that most of the FSM's are not exact factorizable. In this paper, we have suggested a method of making FSM's exact factorizable by minor changes in the next state space while maintaining the functionality of the FSM. We have also developed a new combined state assignment algorithm for state encoding of Factored and Factoring FSM's. Experimental results on MCNC benchmark examples, after running MISII on the Original FSM, Factored FSM and Factoring FSM have shown a reduction of 40% in the worst case signal delay through the circuit in a multilevel implementation. The total number of literals, on an average is the same after factorization as that obtained by running MISII on the original FSM. For two-level implementation, our method has been able to factorize Benchmark FSM s with a 14% average increase in overall areas, while the areas of combinational components of Factored and Factoring FSM's have been found to be significantly leas than the area of the combinational component of the original FSM. References [1] Pranav Ashar, Srinivas Devadas, and A.Richard Newton. Optimum and heuristic algorithms for an approach to finite state machine decomposition. IEEE Trans. on CAD, 10(3), March 1991. [2] Srinivas Devadas and A.R. Newton. Decomposition and factorization of sequential finite state machines. IEEE.Trans. on CAD, 8(11), November 1989. [3] R.K.Brayton, R.Rudell, A.Sangiovanni Vincentelli, and A.R.Wang. MIS:a multiple level logic optimization system. IEEE Trans. on CAD, 6(6):1062, November 1987. [4] Saeyan Yang and Maciej J.Ciesielski. Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. IEEE Trans. on CAD, 10(1), January 1991. ICCAD94, Pages 702-706 Boolean Constrained Encoding: a new formulation and a case study Ney Laert Vilar Calazans Instituto de Informática - PUCRS - Porto Alegre, RS - BRAZIL e-mail: calazans@brpucrsm.bitnet Abstracts This paper provides a new, generalised approach to the problem of encoding information as vectors of binary digits. We furnish a formal definition for the Boolean constrained encoding problem, and show that this definition encompasses many particular encoding problems found in VLSI design, at various description abstraction levels. Our approach can capture equivalence and/or compatibility classes in the original symbol set to encode, by allowing symbols codes to be cubes of a Boolean space, instead of the usual minterms. Besides, we introduce a unified framework to represent encoding constraints which is more general than previous efforts. The framework is based upon a new definition of the pseudodichotomy concept, and is adequate to guide the solution of encoding problems through the satisfaction of constraints extracted from the original problem statement. An encoding problem case study is presented, the state assignment of synchronous finite state machines with the simultaneous consideration of state minimisation. The practical comparison with well-established approaches to solve this problem in two separate steps, shows that our solution is competitive with other published results. However, the case study is primarily intended to show the feasibility of the Boolean constrained encoding problem formulation. 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Middlefield Road, Mountain View, California 94 043, USA Abstract This paper explores the influence of optimization along the boundary between hierarchically described components. A novel technique called repartitioning combines partitioning and sequential resynthesis of the design under various quality measures. It is applied to various digital circuits which consist of a controller and a datapath. The outcome of this effort is a versatile, parametrizable resynthesis tool which preserves this hierarchy. Due to the cost measures, an average improvement ranging between 5% and 15% was obtained. References [1] Design compiler (tm) reference manual. Technical Report 3.0, Synopsys, inc., December 1992. [2] R. Camposano and J.T.J. van Eijndhoven. Combined synthesis of control logic and datapath. In Proc. of the ICCAD, pages 327–329, Santa Clara, CA, 1987. ACM/IEEE. [3] G. Dueck. New optimization heuristics: The great deluge algorithm and the record-to-record-travel. Journal of Computational Physics, 104(1):86–92, 1993. [4] C.M. Fiduccia and R.M. Mattheyses. A linear-time heuristics for improving network partitions. In Proc. of the 19th DAC, pages 175–181, Miami, FL, 1982. ACM/IEEE. [5] D.D. Gaijski, N. Dutt, A. Wu, and S. Lin. High-Level Synthesis. Kluwer Academic Publishers, Boston/Dordrecht/London, 1992. [6] R. Genevriere and A. Hoffmann. PMOSS – a modular synthesis and HW/SW-codesign system. Technical Report SFB - 358 - B2 - 2/94, Universität Paderborn, Fachbereich 17, Germany, March 1994. [7] A. Ghosh, S. Devadas, K. Keutzer, and J. White. Estimation of average switching activity in combinational and sequential circuits. In Proc. of the 29th DAC, pages 153–159. ACM/IEEE, 1992. [8] S. C.-Y. Huang and Wayne Wolf. How datapath allocation influences controller delay. In Seventh ACM / IEEE Int. WS on High-Level Synthesis, Niagara Falls, Canada, May 18 - 20 1994. [9] B.W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. In Bell Systems Technical Report, volume 49, pages 291–307, 1970. [10] B. Lin and A.R. Newton. Implicit manipulation of equivalence classes using binary decision diagrams. In Proc. of the ICCD, pages 81 – 85, Cambridge, MA, 1991. IEEE. [11] M.J. Mlinar. Control path/data path tradeoffs in VLSI design. Technical Report CEng 91-16, University of Southern California, May 1991. [12] E.M. Sentovich, K.J. Singh, and L. et al. Lavagno. SIS: A system for sequential circuit synthesis. Technical Report Memorandum No. UCB/ERL M92/41, University of California at Berkeley, May 1992. ICCAD94, Pages 714-718 HyHOPE : A Fast Fault Simulator with Efficient Simulation of Hypertrophic Faults Chen-Pin Kung & Chen-Shang Lin Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. Abstract In sequential circuit fault simulation, the hypertrophic faults, which result from lengthened initialization sequence in the faulty circuits, usually produce a large number of fault events during simulation and require excessive gate evaluations. These faults degrade the performance of fault simulators attempting to simulate them exactly. In this paper, an exact simulation algorithm is developed to identify the hypertropic faults and to minimize their effects during the fault simulation. The simulator HyHOPE based on this algorithm shows that the average speedup ratio over HOPE 1.1 is 1.57 for ISCAS89 benchmark circuits. Furthermore, the result indicates the performance of HyHOPE is close to the approximate simulator in which faults are simply dropped when they become potentially detected. References [1] F. Ozguner, et al., “On Fault Simulation Techniques,” Journal of Design Automation and Fault Tolerant Computing, Vol. 3, No. 2, pp. 83-92, 1979. [2] W. T. Cheng and J. H. Patel, “PROOFS: A Super Fast Fault Simulator for Sequential Circuits,” Proc. The European Conference on Design Automation, pp. 475-479, 1990 [3] T. M. Niermann, W. T. Cheng and J. H. Patel, “PROOFS: A Fast, Memory Efficient Sequential Circuit Fault Simulator,” IEEE Trans. on Computer Aided Design, Vol. 11, No 2. pp. 198-207, Feb. 1992. [4] H. K. Lee and D. S. Ha, “HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits,” Proc. 29th Design Automation Conference, pp. 336-340, June 1992. [5] H. K. Lee and D. S. Ha, “New Methods of Improving Parallel Fault Simulation in Synchronous Sequential Circuits,” Proc. Int. Conf. on Computer-Aided Design, pp. 10-17, Oct. 1993. [6] C. P. Kung and C. S. Lin, “Parallel Sequence Fault Simulation for Synchronous Sequential Circuits,” Proc. The European Conference on Design Automation, pp. 434-438, Mar. 1992. [7] N. Gouders and R. Kaibel, “PARIS: A Parallel Pattern Fault Simulator for Synchronous Sequential Circuits,” Proc. Int. Conf. on Computer-Aided Design, pp. 542-545, Nov. 1991. [8] J. A.Waicukauski, E. B. Eichelberger,D. O. Forlenza, E. Lindbloom andT. McCarthy, “Fault Simulation for StructuredVLSI,” VLSI System Design, pp. 20-32, December 1985. [9] S. Gai, P. L. Montessoro and F. Somenzi, “The Performance of the Concurrent Fault Simulation Algorithms in MOZART,” Proc. 25th Design Automation Conference, pp. 682-697, June, 1988. [10] G. Gabodi, S. Gai and M. Sonza Reorda, “Fast Differential Fault Simulation by Dynamic Fault Ordering,” Proc. International Conference on Computer Design, pp. 60-63, 1991. [11] E. G. Ulrich and T. Baker, “The Concurrent Fault Simulation of Nearly Identical Digital Networks,” Proc. 10th Design Automation Workshop, Vol. 6, pp. 145-150, June, 1973. [12] S. Seshu, “OnAn Improved Diagnosis Program,” IEEE Trans. Electron. Comput., Vol. EC-16, pp. 76-79, Feb. 1965. [13] W-T. Cheng, “The BACK Algorithm for Sequential Test Generation,” Proc. International Conference on Computer Design, pp. 66-69, Oct. 1988. [14] F. Brglez, D. Bryan, and K. Kozminski, “Combinational Profiles of Sequential Circuits,” Proc. International Symposium of Circuits and System , pp. 1929-1934, May 1989. ICCAD94, Pages 719-722 Fast Timing Simulation of Transient Faults in Digital Circuits A. Dharchoudhury, S. M. Kang, H. Cha and J. H. Patel Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801. Abstract Transient fault simulation is an important verification activity for circuits used in critical applications since such faults account for over 80% of all system failures. This paper presents a timing level transient fault simulator that bridges the gap between electrical and gate-level transient fault simulators. A generic MOS circuit primitive and analytical solutions of node differential equations are used to perform transistor level simulation with accurate MOSFET models. The transient fault is modeled by a piece-wise quadratic injected current waveform; this retains the electrical nature of the transient fault and provides SPICE-like accuracy. Detailed comparisons with SPICE3 show the accuracy of this technique and speedups of two orders of magnitude are observed for circuits containing up to 2000 transistors. Latched error distributions of the benchmark circuits are also provided. References [1] R. K. Iyer and D. Rossetti, “A measurement-based model for workload dependence of CPU errors," IEEE Trans. Comput., vol. C-35, pp. 511-519, June 1986. [2] F. L. Yang and R. A. Saleh, “Simulation and analysis of transient faults in digital circuits," IEEE J. Solid State Circuits, vol. 27(3), pp. 258-264, March 1992. [3] H. Cha, E. M. Rudnick, G. S. Choi, J. H. Patel, and R. K. Iyer, “A fast and accurate gate-level transient fault simulation environment," Digest 23rd Int. Symp. Fault-Tolerant Comput., pp. 310-319, June 1993. [4] G. C. Messenger, “Collection of charge on junction nodes from ion tracks," IEEE Trans. Nucl. Sci., vol. NS29(6), pp. 2024-2031, Dec. 1982. [5] V. Carreno, G. Choi, and R. K. Iyer, “Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system," NASA Technical Memo 4241, Nov. 1990. [6] Y. H. Shih and S. M. Kang, “Analytic transient solution of general MOS circuit primitives," IEEE Trans. Computer-Aided Design, vol. 11(6), pp. 719-731, June 1992. [7] A. Dharchoudhury, S. Kang, K. Kim and S. Lee, “Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics," Proc. ICCAD, 1994. [8] F. Brglez, D. Bryan, and K. Kozminski, “Combinational profiles of sequential benchmark circuits," Proc. IEEE Int. Symp. Circuits and Systems, pp. 1929-1934, May 1989. [9] W. T. Cheng and S. Davidson, “Sequential circuit test generator (STG) benchmark results," Proc. IEEE Int. Symp. on Circuits and Systems, pp. 1938-1941, May 1989. ICCAD94, Pages 723-726 A Fast and Memory-Efficient Diagnostic Fault Simulation for Sequential Circuits Jer Min Jou and Shung-Chin Chen Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C. Abstract In this paper, a fast and memory-efficient diagnostic fault simulator for sequential circuits is proposed. In it, a two-level optimization technique is developed and used to prompt the processing speed. In the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus the number of diagnostic comparisons is minimized. In the second low level, a bitparallel comparison is developed to speed up the comparing process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault. Experimental results show that this diagnostic simulator achieves a significant speedup compared to previous methods. References [1] P. Camurati, D. Medine, P. Prinetto, and M. S. Reorda, "A Diagnostic Test Pattern Generation Algorithm," Proc. International Test Conference, pp. 52-58,1990. [2] K. Kubiak, S. Parkes, W. K. Fuchs. and R. Saleh, "Exact Evaluation of Diagnostic Test Resolution," Proc. 29th Design Automation Conference, pp. 347-352,1992. [3] T. M. Niermann, W. -T. Cheng, and J. H. Patel, "PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator," IEEE Trans. CAD, pp. 198-207, Feb. 1992. [4] E. M. Rudnick, W. K. Fuchs, and J. H. Patel, "Diagnostic Fault Simulation of Sequential Circuits," Proc. International Test Conference, pp. 178-186,1992. [5] H. K. Lee and D. S. Ha, "HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits," 29th Design Automation Conference, pp. 336-340,1992. [6] F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," International Symposium of Circuits & Systems, pp.1929-1934,1989. [7] W. -T. Cheng and T. J. Chakraborty, "GENTEST, An Automatic Test Generation System for Sequential Circuits," Computer, pp. 43-49, Apr. 1989. [8] W. -T. Cheng and S. Davidson, "Sequential Circuit Test Generator (STG) Benchmark Results," International Symposium of Circuits & Systems, pp.1938-1941,1989. ICCAD94, Pages 728-735 Timing Uncertainty Analysis for Time-of-Flight Systems John R. Feehrer and Harry F. Jordan Optoelectronic Computing Systems Center, Campus Box 525, University of Colorado, Boulder, CO 80309-0525 {feehrer,harry}@boulder.colorado.edu Abstract Time-of-flight synchronization is a new digital design methodology that eliminates all latching devices, allowing higher clock rates than alternative timing schemes. Synchronization is accomplished by precisely balancing connection delays. Many effective pipeline stages are created by pipelining combinational logic, similar in concept to wave pipelining but differing in several respects. Due to the unique flow-through nature of circuits and to the need for pulsemode operation, time-of-flight design exposes interesting new areas for CAD timing analysis. This paper discusses how static propagation delay uncertainty limits the clock period for time-offlight circuits built with opto-electronic devices. We present algorithms for placing a minimum set of clock gates to restore timing in feedback loops that implement memory and for propagating delay uncertainty through a circuit graph. A mixed integer program determining the minimum feasible clock period subject to pulse width and arrival time constraints is discussed. Algorithms are implemented in XHatch, a time-of-flight CAD package. References [1] P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic De-sign. Kluwer Academic Publishers, 1991. [2] D. C. Wong, G. D. Micheli, and M. J. Flynn, “Designing high-performance digital circuits using wave pipelining: Algorithms and practical experiences," IEEE Transactions on CAD, pp. 25-46, January 1993. [3] D. A. Joy and M. J. Ciesielski, “Clock period minimization with wave pipelining," IEEE Transactions on CAD, vol. 12, pp. 461-472, April 1993. [4] W. K. Lam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Valid clocking in wavepipelined circuits," Proceedings of ICCAD, 1992, pp. 518-525. [5] C. T. Gray, W. Liu, and R. K. G. III, “Timing constraints for wave pipelined systems," Tech. Report NCSUVLSI-92-06, Dept. of Electrical and Computer Engineering, North Carolina State University, December 1992. [6] T. Soukup, R. Feuerstein, and V. Heuring, “Implementation of a fiber-optic delay-line memory," Applied Optics, vol. 31, pp. 3233-3240, June 10 1992. [7] P. Main, R. Feuerstein, V. Heuring, H. Jordan, J. Feehrer, and C. Love, “Implementation of a general purpose stored-program digital optical computer," Applied Optics, vol. 33, p. 1619, March 10 1994. [8] D. Blumenthal et al., “First demonstration of multihop all-optical packet switching," IEEE Photonics Technology Letters, March 1994. [9] J. Feehrer, L. Ramfelt, and J. Sauer, “Design and implementation of a prototype optical deflection network," ACM SIGCOMM '94 Conference on Communications Architectures, Protocols, and Applications, August 31 1994. [10] H. F. Jordan, A. R. Mickelson, B. V. Zeghbroeck, and I. Januar, “An integrated optics, stored program computer," Topical Meeting in Optical Computing, Optical Society of America, March 1993, pp. 318-321. [11] M. Salerno, “Xhatch user's manual," Tech. Report 91-25, Optoelectronic Computing Systems Center, University of Colorado Boulder, October 1991. ftp cs.colorado.edu:/pub/distribs/xhatch. [12] A. Yariv, Optical Electronics. Saunders College Publishing, 4th ed., 1991. [13] H. F. Jordan and V. P. Heuring, “Time multiplexed optical computers," Supercomputing 91, 1991, pp. 370-378. [14] J. A. McHugh, Algorithmic Graph Theory. Prentic Hall, Inc., 1990. [15] J. P. Pratt and V. P. Heuring, “Delay synchronization in time-of-ight optical systems," Applied Optics, vol. 31, pp. 2430-2437, May 10 1992. [16] A. Lempel and I. Cederbaum, “Minimum feedback arc and vertex sets of a directed graph," IEEE Transactions on Circuit Theory, vol. CT-13, pp. 399-403, December 1966. [17] E. M. Sentovich et al., “SIS: A system for sequential circuit synthesis," Tech. Report UCB/ERL M92/41, Electronics Research Lab., University of California, Berkeley, May 4 1992. [18] B. Berger and P. W. Shor, “Approximation algorithms for the maximum acyclic subgraph problem," Proceedings of 1st Annual ACM-SIAM Symposium on Discrete Algorithms, 1990, pp. 236-243. [19] G. Hadley, Nonlinear and Dynamic Programming. Addison-Wesley, 1964. [20] C. E. Leiserson and J. B. Saxe, “Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5-35, 1991. [21] J. R. Feehrer, “Minimizing the major clock cycle in bit-serial time-of-ight synchronized digital circuits," Tech. Report 93-03, Optoelectronic Computing Systems Center, University of Colorado Boulder, March 1993. [22] D. Lee and S. Reddy, “On determining scan flip-flops in partial-scan design," Proceedings of IC-CAD, 1990, pp. 322-325. ICCAD94, Pages 736-742 Provably Correct High-Level Timing Analysis without Path Sensitization Subhrajit Bhattacharya Dept. of Computer Science, Duke University, Durham, NC 27706 Sujit Dey C&C Research Labs, NEC USA, Princeton, NJ 08540 Franc Brglez CBL, Dept. of ECE, North Carolina State Univ, Raleigh, NC 27695 Abstract This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit which may be pessimistic, or use gate-level timing analysis for calculating the true delay, which may be prohibitively expensive. We show that the paths in the implementation of a behavioral specification can be partitioned into two sets, SP and UP. While the paths in SP can affect the delay of the circuit, the paths in UP cannot. Consequently, the true delay of the resulting circuit can be computed by just measuring the topological delay of the paths in SP, eliminating the need for the computationally intensive process of path sensitization. Experimental results show that high-level true delay estimation can be done very fast, even when gate-level true delay estimation becomes computationally infeasible. The high-level delay estimates are verified by comparing with delay estimates obtained by gate-level timing analysis on the actual implementation. REFERENCES [1] H-C. Chen and D. H. C. Du. Path Sensitization in Critical Path Problem. In ICCAD, 1991. [2] S. Devadas, K. Keutzer, and S. Malik. Delay Computation in Combinational Logic Circuits: Theory and Algorithms. In ICCAD, 1991. [3] P.C. McGeer, A. Saldanha, P.R. Stephan, and R.K. Brayton. Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. In ICCAD, Nov 1991. [4] P. Ashar, S.Malik, and S. Rothweiler. Functional Timing Analysis using ATPG. In EDAC, 1993. [5] S. Perremans, L. Claesen, and H. De Man. Static Timing Analysis of Dynamically Sensitizable Paths. In 26th DAC, 1989. [6] C. Ramachandran, F. J. Kurdahi, D. D. Gajski, A. C.-H. Wu, and V. Chaiyakul. Accurate Layout Area and Delay Modeling for System Level Design. In ICCAD, August 1992. [7] A. Kuehlmann and R. A. Bergamaschi. Timing Analysis in High-Level Synthesis. In ICCAD, August 1992. [8] P.K. Jha andN.D.Dutt. Rapid Estimation for Parameterized Components in High-Level Synthesis. IEEE Transactions on VLSI Systems, 1(3):296–303, Sept 1993. [9] C. Safinia, R. Leveugle, and G. Saucier. Taking Advantage of High Level Functional Information to Refine Timing Analysis and TimingModeling. In ED&T, 1994. [10] C. Ramachandran and F. J. Kurdahi. Combined Topological and Functionality Based Delay Estimation Using a Layout-Driven Approach for High Level Applications. In EDAC, 1992. [11] R. A. Bergamaschi. The Effects of False Paths in High-Level Synthesis. In ICCAD, 1991. [12] B. Gregory, D. MacMillen, and D. Fogg. ISIS: A System for Performance Driven Resource Sharing. In 29th DAC, 1992. [13] S. Bhattacharya, S. Dey, and F. Brglez. Clock Period Optimization During Resource Sharing and Assignment. In 31st DAC, 1994. [14] S. Bhattacharya, S. Dey, and F. Brglez. Provably Correct High-Level Timing Analysis without Path Sensitization. Technical report, C&C Research Labs, NEC USA, June 1994. [15] Kenneth Hintz and Daniel Tabak. Microcontrollers: Architecture, Implementation, and Programming. McGraw-Hill, New York, NY 10020, 1992. [16] K. Kozminski (ed.). OASIS Users Guide. MCNC, Research Triangle Park, N.C. 27709, 1992. [17] E.M. Sentovich, K.J. Singh, C. Moon, H. Savoj, R.K. Brayton, and A. Sangiovanni-Vincentelli. Sequential Circuit Design using Synthesis and Optimization. In ICCD, October 1992. ICCAD94, Pages 743-748 A Timing Analysis Algorithm for Circuits with Level-Sensitive Latches Jin-fuw Lee, Donald T. Tang, and C. K. Wong IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598 Abstract For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the modified shortest and longest path method. The computational complexity of our algorithm is generally better than that of known algorithms in the literature. The implementation (CYCLOPSS) has been applied to an industrial chip to verify the clock schedules. References 1. K. A. Sakallah, T. N. Mudge, and O. A. Olukotun, "Check Tc and min Tc: Timing verification and optimal clocking of synchronous digital circuits," Proc. ICCAD, pp. 552-555, Nov 1990. 2. T. G. Szymanski, and N. Shenoy, "Verifying clock schedules" Proc. ICCAD, pp. 124-131, Nov. 1992 3. R. B. Hitchcock, "Timing verification and the timing analysis program," Proc. 19 th Design Automation conference, pp. 605-615, 1982. 4. R. S. Tsay and Ichiang Lin, "A system timing verifier for multiple-phase level-sensitive clock design," Research Report RC 17272, IBM Yorktown, 1991. 5. N. Shenoy, R. Brayton, and A. Sangiovanni-Vincentelli, "Graph Algorithms for clock schedule optimization," ICCAD, pp. 132-136, Nov. 1992. 6. T. G. Szymanski, "Computing optimal clock schedules," Proc. 29 th Design Automation conference, pp. 399-404, 1992. 7. A. V. Aho, J. E. Hopcroft, and J. D. Ullman, "Data structure and algorithms," Addison-Wesley, 1983, pp. 216218. 8. R. E. Tarjan, "Data structures and network algorithms," the Society for Industrial and Applied Mathematics, 1983. 9. E. L. Lawler, "Combinational Optimzation: Networks, and Matroids," Holt, Rinehart and Winston, 1976. 10. J. F. Lee, D. T. Tang and C. K. Wong, "Timing Verification Algorithm for Clock Design with Slack Sharing," IBM Technical Disclosure Bulletin, pp. 249-252, 1993. ICCAD94, Pages 750-753 An Object-Oriented Cell Library Manager Naresh K. Sehgal Intel Corporation, Santa Clara, CA C. Y. Roger Chen ECE Department, Syracuse University, Syracuse, NY John M. Acken CrossCheck Technology, Inc., San Jose, CA Abstract New techniques are proposed to obtain better estimates and optimizations at higher levels of design abstractions, which are then used for library cell selection. A single object-oriented database repository is used during all phases of VLSI design to enhance the early design estimates. As compared to a relational database using sorted tables of attribute values, the proposed object-oriented cell library manager reduces search time for an appropriate cell, with m constraints among n cells, from O(nm) to O(m log n). The proposed method also reduces design cycle time by reducing the number of iterations due to mismatched performance estimates done in the earlier phases of a design. References [1] Object Store 2.0.1 reference manual, 1992. ODI Inc. [2] Turbo C++ Users Guide, pp. 127-128, Borland Corp., 1992. [3] N. K. Sehgal, C. Y. Chen, and J. M. Acken, “Datapath Cell Design Strategy for Channelless Routing,” ASIC’94. [4] N. K. Sehgal, C. Y. Chen, and J. M. Acken, “A Cell Library Paradigm for the Channelless Datapath Layout Design,” IEEE International Conference on Microelectronics’94. ICCAD94, Pages 754-761 Reuse of Design Objects in CAD Frameworks Joachim Altmeyer, Stefan Ohnsorge, Bernd Schürmann University of Kaiserslautern, D-67653 Kaiserslautern, Germany Abstract The reuse of well-tested and optimized design objects is an important aspect for decreasing design times, increasing design quality, and improving the predictability of designs. Reuse spans from the selecting cells from a library up to adapting already designed objects. In this paper, we present a new model for reusing design objects in CAD frameworks. Based on experiences in other disciplines, mainly in software engineering and case-based reasoning, we developed a feature-based model to describe design objects and their similarities. Our model considers generic modules as well as multifunctional units. We discuss the relationships of the model to the design process and to the configuration hierarchy of complex design objects. We examined our model with the prototype system RODEO. References [1] J. Allen, “Performance-Directed Synthesis of VLSI Systems”, Proceedings of the IEEE, February 1990 [2] V.R. Basili, D.D. Rombach, “Support for Comprehensive Reuse”, IEEE Software Engineering Journal, Sept. 1991 [3] B. Becker, G. Hotz, R. Kolla, P. Molitor, “Hierarchical Design Based on a Calculus of Nets”, Proc. 24th Design Automation Conference, 1987 [4] T. J. Biggerstaff, A. J. Perlis (Ed.), “Software Reusability / Volume I / Concepts and Models”, ACM Press Frontier Series, 1989 [5] E. L. Rissland et. al., “Case-Based Reasoning“, Proc. Case-Based Reasoning Workshop (DARPA), 1989 [6] S. Y. Foo, Y. Takefuji, “Database and Cell-Selection Algorithms for VLSI Cell Libraries“, IEEE Computer, February 1990 [7] D. D. Gajski (Ed.), “Silicon Compilation”, Addison-Wesley, 1988 [8] E. Girczyc, S. Carlson, “Increasing Design Quality and Engineering Productivity through Design Reuse”, Proc. 30th Design Automation Conference, 1993 [9] R. H. Katz, “Towards a Unified Framework for Version Modeling in Engineering Databases”, ACM Computing Surveys, Vol. 22, No. 4, 1990 [10] J. L. Kolodner, “An Introduction to Case-Based Reasoning“, Artificial Intelligence Review, 6, 1992 [11] R. Prieto-Diaz, P. Freeman, “Classifying Software for Reusability”, IEEE Software Magazine, January 1987 [12] M. M. Richter, “Classification and Learning of Similarity Measures”, Studies in Classification, Data Analysis and Knowledge Organization, Springer, 1992 [13] E. Rich, K. Knight, “Artificial Intelligence”, McGraw Hill, 1991 [14] B. Schürmann, J. Altmeyer, M. Schütze, “On Modeling Top-Down VLSI Design”, Proc. Int. Conference of Computer Aided Design, San Jose, California, 1994 [15] E. Siepmann, “Entwurfstheorie und Entwurfsdatenmodellierung fuer CAD-Frameworks“, Ph.D. Dissertation, University of Kaiserslautern, 1991, in German [16] E. Siepmann, G. Zimmermann, “An Object-Oriented Data-model for the VLSI Design System PLAYOUT”, Proc. 26th Design Automation Conference, 1989 [17] A. Tversky, “Features of Similarity”, Psychological Review 84, 1977 [18] G. Zimmermann, “PLAYOUT - A Hierarchical Design System”, Information Processing 89, G.X. Ritter (ed.), Elsevier Science Publishers B.V. (North Holland), IFIP, 1989 ICCAD94, Pages 762-767 Towards Support for Design Description Languages in EDA Frameworks Olav Schettler, Susanne Heymann GMD, D-53754 Sankt Augustin, Germany Abstract We report on a new framework service for design tool encapsulation, based on an information model for design management. The new service uses generated language processors that perform import and export of design files to and from a design management database with the support of nested syntax specifications and extension language scripts. Our prototype design environment is based on the Nelsis CAD Framework and several tools from the Synopsys high-level synthesis and simulation tool suite. References 1. Batory, D.S. Kim,W., "Modeling Concepts for VLSI CAD Objects", ACM Transactions on Database Systems, vol. 10 #3, 1985, pp. 322-346 2. Biliris, A., “Database support for evolving design objects”, 26th ACM/IEEE Design Automation Conference, 1989 3. Bredenfeld, Ansgar, "Definition of Modeling Concepts for a Procedural Interface between VLSI-Design Tools and a Common Database", Proc. of the 2nd International Workshop on Electronic Design Automation Frameworks, Charlotteville, Virginia, 1990 4. Brielmann, Maria; Kupitz, Elisabeth, “Representing the Hardware Design Process by a Common Data Schema”, ACM/IEEE European Design Automation Conference, 1992 5. Carter, Donald E.; Stilwell Baker, Barbara, "Concurrent Engineering: The Production Development Environment for the 1990s", Mentor Graphics Corporation, 1991 6. CAD Framework Initiative, Architecture Working Group, "Framework Architecture Reference", Version 1.2, 1993 7. CAD Framework Initiative, Architecture TC, "CAD Framework - Users, Goals, and Objectives", Version 0.92, 1990 8. Ferrans, James, C.; Hurst, David W.; Sennet, Michael A.; Covnet, Burton M.; Ji, Wenguang; Kajka, Peter; Ouyang, Wei, "Hyper-Web: A Framework for Hypermedia-Based Environments", 5th ACM SigSoft Symposium on SDEs, Tysons Corner, Virginia, 1992, pp. 1-10 9. Gajski, D., Kuhn, R. H., "Guest Editors Introduction - New VLSI Tools", IEEE Computer, vol. 16 #2, 1983, pp. 14-17 10.Katz, Randy H.; Anwarrudin, M.; Chang, E., “A Version Server for Computer-Aided Design Data”, 23rd ACM/IEEE Design Automation Conference, 1986, pp. 27-33 11.Ousterhout90, John K., "Tcl: An Embeddable Command Language", Winter USENIX Conference, 1990 12.ter Bekke, Johan H., “Semantic Data Modeling”, Prentice Hall International (UK), 1992 13.Institute of Electrical and Electronic Engineers, “IEEE Standard VHDL - Language Reference Manual”, IEEE Std 1076-1987, March 31, 1988 14.Wagner, F.; Golendziner, L.; Lacombe, J.; de Lima, A., “Design Version Management in the STAR Framework”, in T. Rhyne (ed.), Electronic Design Automation Frameworks, North Holland, 1992, pp. 85-97 15.van der Wolf, Pieter, "Architecture of an Open and Efficient CAD Framework", PhD Dissertation, TU Delft, 1993
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De Grossi Mazzorin J., 2016, Nuovi dati sui cavalli etruschi: i resti equini della tomba dei “Demoni azzurri” a Tarquinia, 2016
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Riassunto-Si presentano i risultati dello studio effettuato sui resti di cavallo rinvenuti nella famosa tomba dei Demoni azzurri a Tarquinia, databile intorno alla metà del V secolo a.C. Si tratta di una deposizione funeraria con evidenti caratteri simbolici. Summary-The results of the study of the horse remains from the famous Etruscan tomb of the "Blue Demons" in Tarquinia are here reported. The burial, dated to the half of the 5 th century BC, presents evident symbolic characters. Introduzione Nel 1985, a seguito di uno scavo effettuato sulla Strada Provinciale dei Monterozzi per la posa in opera dell'acquedotto comunale di Tarquinia, veniva intercettato il dromos di una tomba a camera etrusca, le cui successive indagini archeologiche evidenziavano trattarsi di una sepoltura di eccezionale importanza per una serie di raffigurazioni pittoriche sulle pareti della camera mortuaria (Adinolfi et al. 2005a). La tomba presentava un dromos monumentale (lungo ca. m 13 x 2,4 di larghezza) inclinato a scivolo verso la porta della camera, il cui ingresso era chiuso da due grossi lastroni sovrapposti di calcarenite. Dalla sequenza stratigrafica risultano almeno tre fasi di riempitura del dromos (Adinolfi et al. 2005a, p. 431 ss.) (Fig. 1). Una prima fase, iniziale, è caratterizzata da alcuni strati di accumulo con scarsi materiali ceramici (Adinolfi et al. 2005a, p. 431, nota 4) e diverse ossa animali. Questa prima colmatura parziale del dromos arrivava a coprire le lastre di accesso della porta per tutta la loro altezza. Una seconda colmatura sembra esser stata effettuata successivamente dopo un periodo relativamente breve testimoniato da un paio di strati sottili a matrice sabbiosa che separano nettamente le due fasi di colmatura. Questa seconda fase, che dovrebbe rappresentare l'interro finale e quindi la conclusione di tutti gli atti legati alle cerimonie funebri, è caratterizzata da un potente riempimento, che colma i due terzi del dromos, ricco di frammenti ceramici e altri resti ossei animali. La datazione del repertorio ceramico colloca questa fase di riempimento del dromos in un arco cronologico compreso tra il 440 a.C. e il 430 a.C. (Adinolfi et al. 2005a, p. 432). Al di sopra di queste due colmature ce n'è una terza più recente che oblitera completamente il dromos e pare completamente estranea alla successione degli atti funerari. Conclude la sequenza stratigrafica il riempimento di una fossa di violazione che dalla superficie raggiungeva il punto di congiunzione tra il lastrone superiore della porta e il corrispondente architrave (Adinolfi et al. 2005a, p. 433). All'interno della camera (Fig. 2), in corrispondenza dell'ingresso, vi era infatti un conoide dovuto allo scivolamento del terreno infiltratosi al momento della violazione (che deve esser stata effettuata prima del 1826) e dal successivo interramento della fossa di violazione. Anche questo terreno conteneva alcune ossa animali scivolate dagli strati di riempimento del dromos. Dall'imponente dromos si accedeva quindi ad un ampia camera di circa m 6 per lato, sulle cui pareti sono raffigurate, a sinistra il viaggio trionfale del defunto su carro trainato da due cavalli e accompagnato da una solenne processione, sulla parete di fondo il simposio del defunto con la
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Ultrafast real-time vibronic coupling of a breather soliton intrans-polyacetylene using a laser pulse with few cycles
Physical Review B, 2009
Valerii Kobryanskii
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Systolic Blood Pressure and the Risk of Kidney Replacement Therapy and Mortality in Patients with Chronic Kidney Disease Stages 4–5
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MARIA DE ALCANTAR VALLIN
Introduction: In patients with chronic kidney disease stages 4 and 5 (CKD stages 4–5) without dialysis and arterial hypertension, it is unknown if the values of systolic blood pressure (SBP) considered in control (<120 mm Hg) are associated with kidney replacement therapy (KRT) and mortality. Methods: In this retrospective cohort study, hypertensive CKD stages 4–5 patients attending the Renal Health Clinic at the Hospital Civil de Guadalajara were enrolled. We divided them into those that achieved SBP <120 mm Hg (controlled group) and those who did not (>120 mm Hg), the uncontrolled group. Our primary objective was to analyze the association between the controlled group and KRT; the secondary objective was the mortality risk and if there were subgroups of patients that achieved more benefit. Data were analyzed using Stata software, version 15.1. Results: During 2017–2022, a total of 275 hypertensive CKD stages 4–5 patients met the inclusion criteria for the analysis: 62 in ...
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