Logic circuits

The recent development of Field-Programmable Gate Array (FPGA) architectures, with soft core (MicroBlaze) and hard core (PowerPC) processors, embedded memories and IP cores, offers the potential for high computing power. Presently FPGAs are considered as a major platform for high performance embedded applications as it provides the opportunity for reconfiguration as well as good clock speed and design resources. As the complexities in the embedded applications increase, use of an operating system brings in a lot of advantages. In present day application scenarios most embedded systems have real-time requirements that demand the use of Real-time operating systems (RTOS), which creates a suitable environment for real time applications to be designed and expanded easily. In an RTOS the design process is simplified by splitting the application code into separate tasks and then the scheduler executes them according to a specific schedule, meeting the real-time deadline. In this research work, we propose the design and implementation of a real-time FPGA based application, which demonstrates the creation of real-time process tasks in FPGA systems for successful real-time communication between multiple FPGA systems. We have chosen the RSA based encryption and decryption algorithm for this implementation, as security is one of the most important need for data communication. At first we demonstrate the real-time execution of multiple process tasks in a single FPGA system for the encryption and decryption of data. Next we describe the most challenging part of our work, where we establish the real-time communication between two FPGA systems, each running the encryption engine and decryption engine respectively and communicating with one another via an RS232 communication link. The results show that our design is better in terms of execution speed in comparison with the existing research works.

In this paper, we explain a new EDA tool framework that extends the reach of electrical DFM analysis across cross-domain applications by providing the ability to do layout analysis and logical analysis of the schematics in context. To demonstrate the effectiveness and the flexibility of the integrated environment this new framework provides, we show several real-time applications of layout verification

ABSTRACT This paper presents a self-test methodology and test structures for testing Through Silicon Vias (TSVs) in 3D-IC system prior to stacking in order to improve overall yield. A Scan Switch Network (SSN) architecture is proposed to perform pre-bond TSV scan testing. In the SSN, novel self-test structures are proposed and integrated to detect TSV defects by stuck-atfault and delay-based tests. By exploiting the inherent delay characteristics of TSV, the variation of TSV-to-substrate resistance caused by TSV defects can be mapped to a path delay change and detected. Compared with prior works, the proposed test architecture addresses pre-bond TSV testing under an integrated test solution with low overhead. Test chip measurement and analysis are presented to verify the proposed self-test methodology and structures.