In this paper, we propose a simulation-before-test (SBT) fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type... more
In this paper, we propose a simulation-before-test (SBT) fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS) analog integrated circuits (ICs) interconnects. The fault dictionary is built by simulating the most likely defects causing the faults to be detected at the layout level. Then, for each injected fault, the spectre's frequency responses and the power consumption obtained by simulation are stored in a table which constitutes the fault dictionary. In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate a considered defect. When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full custom CMOS operational amplifier is implemented in 0.25 µm technology and the most likely faults of open-circuit type are deliberately injected and simulated at the layout level.
Sigma-Delta modulators (SDMs) are ubiquitous for implementation of high resolution analog-to-digital converters (ADCs.) However, SDMs are applicable to other signal processing functions such as signal multiplication and filtering. This... more
Sigma-Delta modulators (SDMs) are ubiquitous for implementation of high resolution analog-to-digital converters (ADCs.) However, SDMs are applicable to other signal processing functions such as signal multiplication and filtering. This paper will introduce via-configurable array technology as a cost effective approach for developing circuits like SDMs and provide application examples using these techniques.
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by... more
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
— A clock and data recovery PLL is described for serial nonreturn-to-zero (NRZ) data transmission. The voltage controlled oscillator (VCO) works at half the data rate, which means for a 1-Gb/s data rate, the VCO runs at 500 MHz. A... more
— A clock and data recovery PLL is described for serial nonreturn-to-zero (NRZ) data transmission. The voltage controlled oscillator (VCO) works at half the data rate, which means for a 1-Gb/s data rate, the VCO runs at 500 MHz. A specially designed phase comparator uses a delay-locked loop (DLL) to generate the required sampling clocks to compare clock and data. The VCO can typically be tuned from 350 MHz to 890 MHz and the phase-locked loop (PLL) locks between 720 Mb/s and 1.3 Gb/s. Data recovery is error free up to 1.2 Gb/s with a 9-b pseudorandom data sequence. The core consumes 85 mW (3.3 V) at 1 Gb/s.
This paper presents two new analog multipliers/dividers using a new universal active element, called the current differencing buffered amplifier (CDBA). The reported circuits are suitable for monolithic chip realization for use in... more
This paper presents two new analog multipliers/dividers using a new universal active element, called the current differencing buffered amplifier (CDBA). The reported circuits are suitable for monolithic chip realization for use in battery-powered, portable electronic equipments. The circuits can be used as a multiplier and divider without changing circuit topologies. The workability of the proposed configurations is tested through different applications with PSPICE simulations using TSMC 0.35 μm CMOS process parameters. The simulated results show that: for ±2.5 V power supply, the total harmonic distortions are less than 3.1% and 2.25% for the first and second configuration respectively. It also shows that the −3 dB bandwidths are 59.09 MHz and 68.55 MHz and static power dissipations are 0.28 mW and 0.23 mW respectively. The sensitivity of the output of the circuits is low with respect to temperature variations.
Abstract--- Image compression is an important topic in digital world. It is the art of representing the information in a compact form. We present a new design of low-power and high speed Discrete Cosine Transform (DCT) for image... more
Abstract--- Image compression is an important topic in digital world. It is the art of representing the information in a compact form. We present a new design of low-power and high speed Discrete Cosine Transform (DCT) for image compression to be implemented on Field Programmable Gate Arrays (FPGAs).The architecture of DCT is based on Lo-effler method which is a fast and low complexity algorithm. The DCT optimization is based on the hardware simplification of the multipliers used to compute the DCT coefficients. Low power approaches like Canonic signed digit representation for constant coefficients and sub-expression elimination methods have been used. The 2D DCT is performed on 8x8 image matrix using two 1D DCT blocks and a transposition block. Similar to DCT, the IDCT is also implemented using the Lo-effler algorithm for IDCT. Verilog HDL is used to implement the design. ISIM of XILINX is used for the simulation of the design. X power analyzer tool of xilinx is used to obtain the detailed dynamic power report of the design. MATLAB is used as the support tool to obtain the input pixel values of the image.
Organic materials and devices are gaining more and more attention in microelectronics. They are dedicated to low cost applications and easy fabrication. Organic thin film transistors (OTFTs) are now making significant inroads into many... more
Organic materials and devices are gaining more and more attention in microelectronics. They are dedicated to low cost applications and easy fabrication. Organic thin film transistors (OTFTs) are now making significant inroads into many new large-area applications, considering that they can be fabricated at low temperatures and with high throughput on a wide range of unconventional substrates, such as glass, plastic, fabric, and paper. In this paper an OTFT model is used in cadence, a Verilog-a code is written and used to create an OTFT device. This is done so that OTFT circuits can be simulated before fabrication. First, the model is validated by characterizing the device, showing its FET characteristics. Second, the device is used inside a circuit, and the circuit performance is analyzed. Inverter circuit is implemented using the modelled OTFT device, transfer characteristics, input and output waveforms are drawn using the simulation tool. The transistors used have 10m/20u W/L ratio, the inverter is used at 1 kHz frequency.
Introduction This lab session has a purpose of practical implementation of theoretical knowledge about transistors. There are four parts in the work: • NPN and PNP Transistors • Transistors Biasing • Q point stabilization Apparatus... more
Introduction
This lab session has a purpose of practical implementation of theoretical knowledge about transistors. There are four parts in the work:
• NPN and PNP Transistors
• Transistors Biasing
• Q point stabilization
Apparatus
The following equipment was used during the lab:
• MCM3/EV board
• Power supply PSLC or PS1-PSU/EV
• Accessories
As in the previous lab, the whole lab work is done with the MCM/EV board. The oscilloscope was used for the visualization of the waveforms. Screwdriver was used for the variable resistor configuration.
The aim of this laboratory work is to get practical experience with BJT and FETs. From theory, we know that Field Effect Transistors are voltage controlled unlike from BJTs, which are current controlled devices. There are Source, Gate and... more
The aim of this laboratory work is to get practical experience with BJT and FETs. From theory, we know that Field Effect Transistors are voltage controlled unlike from BJTs, which are current controlled devices. There are Source, Gate and Drain electrode sides. The Gate electrode voltage is used to control Drain-Source characteristics. In this lab, we are to obtain the results in order to prove above said.
Equipment used:
- Power Supply PS1-PSU/EV
- Module MCM4/EV
- Multimeter
- Jumpers
Voltage Controlled Oscillator plays significant role in communication system design. The design of Voltage Controlled Oscillator (VCO) with low power consumption and high frequency range is presented in this paper. The VCO is based on a... more
Voltage Controlled Oscillator plays significant role in communication system design. The design of Voltage Controlled Oscillator (VCO) with low power consumption and high frequency range is presented in this paper. The VCO is based on a single ended CMOS inverter ring oscillator. Accurate frequency of oscillation in Ring Oscillator is an important design issue. A Voltage Controlled Ring Oscillator with wide tuning range from 917.43MHz to 4189.53MHz can be achieved using bulk driven technique by varying the threshold voltage of the MOS circuits. The circuit is designed using 0.13µm CMOS process for a supply voltage of 1V. Simulation results show better accuracy compared to existing current staved ring VCO using different number of inverter stages.
The design of a linear integrated Op Amp circuit as an alternative solution to differential equation model of RLC Circuit is presented. The fundamental assumption used in the cascaded Operational Amplifier (Op Amp) design is that Op Amp... more
The design of a linear integrated Op Amp circuit as an alternative solution to differential equation model of RLC Circuit is presented. The fundamental assumption used in the cascaded Operational Amplifier (Op Amp) design is that Op Amp acts linearly. In this paper, we will examine the behavior of the Op Amp when it is used in the cascaded circuit that is an electrical analog to the differential equation model of RLC circuit, which arises in numerous applications particularly in control and communication systems such as ringing circuits, resonant circuits, filters and oscillators. We will design the cascaded op amp circuit that is analog to differential equation model of RLC circuit and obtain graphical results of output function versus time using PSpice Software Probe. To confirm the validity of the design of a linear integrated Op Amp circuit as an alternative solution to differential equation model of RLC circuit implemented in the PSpice Software, simulation results are compared with RLC circuit where we find good agreement between the theoretical predictions of the differential equation model of RLC circuit and the design of a linear integrated Op Amp circuit.
—This paper focuses on and analysis and design of current starved voltage controlled ring oscillator. The analysis includes effect of delay time, phase noise, layout area, technology etc. on the frequency of oscillation at various power... more
—This paper focuses on and analysis and design of current starved voltage controlled ring oscillator. The analysis includes effect of delay time, phase noise, layout area, technology etc. on the frequency of oscillation at various power supplies and control voltages. The simulation results shows that the circuit has higher tuning range and low power consumption suitable for various application domains. Added benefit of this VCO is to maintain a constant amplitude level and oscillation. It is also proved here that the frequency of oscillation is inverse of the supply voltage and therefore consuming less power.
In the first laboratory work of Integrated Circuit Design course, we are going to fasten all obtained theoretical knowledge in practice. In other words, we are going to get familiarized with MOSFETS, their operation and related circuits.... more
In the first laboratory work of Integrated Circuit Design course, we are going to fasten all obtained theoretical knowledge in practice. In other words, we are going to get familiarized with MOSFETS, their operation and related circuits. Moreover, for the first time we will work with software equipment called Tanner EDA, which is widely used in designing and simulation of Integrated Circuits.
A 5.6 GHz band frequency synthesizer with an improved LC-tank Colpitts voltage-controlled oscillator (VCO) has been designed and successfully implemented in tsmc 0.18 μm CMOS technology. The VCO is formed by two complementary nMOS and... more
A 5.6 GHz band frequency synthesizer with an improved LC-tank Colpitts voltage-controlled oscillator (VCO) has been designed and successfully implemented in tsmc 0.18 μm CMOS technology. The VCO is formed by two complementary nMOS and pMOS transistors for generating negative resistance to compensate the loss in the LC-tank of the VCO. A 3-bit binary weighted capacitor array is connected to the LC-tank for frequency coarse tuning and a gain boosting Colpitts technique is employed to achieve low power consumption and reduce phase noise. Under the supply voltage of1.8 V, measured results introduce that the output frequency is tuneable from 5.25 to 5.75 GHz corresponding to 9.1% with a power consumption of 17.8 mW, the phase noise at 1 MHz offset frequency from 5.6 GHz is -110.12dBc/Hz and the output power spectrum at the locked frequency of 5.606 GHz is -3.14dBm. Including pads, the chip dimension is 0.665 (0.774×0.86)mm2.
Signal & Image Processing : An International Journal is an Open Access peer-reviewed journal intended for researchers from academia and industry, who are active in the multidisciplinary field of signal & image processing. The scope of the... more
Signal & Image Processing : An International Journal is an Open Access peer-reviewed journal intended for researchers from academia and industry, who are active in the multidisciplinary field of signal & image processing. The scope of the journal covers all theoretical and practical aspects of the Digital Signal Processing & Image processing, from basic research to development of application.
Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Signal & Image processing.
— Phase Locked Loop (PLL) is basic building block of several communication systems to achieve synchronization. In this paper the PLL is designed using improved performance ring VCO with 0.18 μm CMOS technology and supply voltage of 3 V.... more
— Phase Locked Loop (PLL) is basic building block of several communication systems to achieve synchronization. In this paper the PLL is designed using improved performance ring VCO with 0.18 μm CMOS technology and supply voltage of 3 V. The proposed ring VCO which has higher tuning range is used for implementation of PLL in order of GHz frequency range. The phase frequency detector (PFD) is another part of PLL which is designed using multiplexer which gives more accurate results. The low pass filter which is connected with charge pump is designed using switched capacitor technique in which resistor is replaced by transistors and capacitor by which the overall area of the circuit is reduced. The designed PLL has a power consumption of approximately 28 mW at the operating frequency of 2.5 GHz.
This paper presents the ring oscillator based CMOS temperature sensor. The method is highly area efficient, simple and easy for IC implementation as compared to traditional temperature sensors. The proposed temperature sensor was... more
This paper presents the ring oscillator based CMOS temperature sensor. The method is highly area efficient, simple and easy for IC implementation as compared to traditional temperature sensors. The proposed temperature sensor was fabricated using 0.35 μm technology, which occupies extremely small silicon area. It exploits the frequency of the ring oscillator that is proportional to temperature, which is displayed in the form of a digital output. The proposed CMOS temperature sensor comprises a ring oscillator, a voltage level shifter, a 10-bit counter, and a 10-bit register. The designed ring oscillator is frequency-tunable and the voltage level shifter provides the output to full-scale to make sure that the number of its rising edge is counted by the counter. The register saves the counted output.
En este reporte se detalla el diseño, implementación y desempeño de diferentes etapas de procesamiento de audio conectadas en cascada, las cuales toman directamente la señal de salida de una guitarra eléctrica, añadiendo efectos de sonido... more
En este reporte se detalla el diseño, implementación y desempeño de diferentes etapas de procesamiento de audio conectadas en cascada, las cuales toman directamente la señal de salida de una guitarra eléctrica, añadiendo efectos de sonido muy utilizados en la música. Además, se trabajó con un medidor de grá fico de barras o Vúmetro, el cual da una representación gráfi ca mediante LEDs de la intensidad de la señal de la guitarra.
—This paper presents the design of a simple multi-phase ring oscillator (RO). It represents a new technique for RO output signal phase control. This RO uses a voltage injection principle to produce different phases output signal. The... more
—This paper presents the design of a simple multi-phase ring oscillator (RO). It represents a new technique for RO output signal phase control. This RO uses a voltage injection principle to produce different phases output signal. The proposed RO consumes only 3.6 mW from a 1.8V power supply while having an oscillation frequency of 5.5 GHz with a 330 MHz fine tuning range. This RO is employing the pulse injection technique for phase noise enhancement. It has a phase noise less than-133.5 dBc/Hz @ 1 MHz offset. It achieves a figure of merit (FoM) of-182.75 dBc/Hz .This RO is designed and simulated in the standard 0.18 µm CMOS technology.
This paper proposed a method that combines Polar Fourier Transform, color moments, and vein features to retrieve leaf images based on a leaf image. The method is very useful to help people in recognizing foliage plants. Foliage plants are... more
This paper proposed a method that combines Polar Fourier Transform, color moments, and vein features to retrieve leaf images based on a leaf image. The method is very useful to help people in recognizing foliage plants. Foliage plants are plants that have various colors and unique patterns in the leaf. Therefore, the colors and its patterns are information that should be counted on in the processing of plant identification. To compare the performance of retrieving system to other result, the experiments used Flavia dataset, which is very popular in recognizing plants. The result shows that the method gave better performance than PNN, SVM, and Fourier Transform. The method was also tested using foliage plants with various colors. The accuracy was 90.80% for 50 kinds of plants.
Automatic leaf recognition system is a case coming to improve time-consuming and troublesome tasks which have mainly been carried out by botanists manually. This application as judged by common characteristics is popular in institutes for... more
Automatic leaf recognition system is a case coming to improve time-consuming and troublesome tasks which have mainly been carried out by botanists manually. This application as judged by common characteristics is popular in institutes for discovering new plant species, modernizing the management of botanical gardens and horticulture fields. In order to conduct a leaf recognition system, the features must be sufficiently distinctive to identify specific objects among many alternatives, where contain both local and global properties. So far, many researchers have represented some techniques which use local or global features only where face problems, such as many images are captured in different intensity, they are maybe sick or calamity, leaves have been damaged or cropped and so on. In this paper, a new method for leaf recognition system is proposed where both local descriptors and global features are employed, combined and finally the most discriminant features are selected by employing a linear discriminant analysis method. The experimental results show that using the feature vector containing the local features and global characteristics leads us to obtain 94.3% recognition rate.
This paper discusses the design of a 2.4 GHz operated, ultra-low power CMOS down-converting active mixer based on double balanced Gilbert-cell resistor-loaded topology fabricated in standard 180 nm RF CMOS low-power technology. All the... more
This paper discusses the design of a 2.4 GHz operated, ultra-low power CMOS down-converting active mixer based on double balanced Gilbert-cell resistor-loaded topology fabricated in standard 180 nm RF CMOS low-power technology. All the MOS transistors of the mixer core have ideally been biased to sub-threshold region. Consuming only 500 μW of DC power using 1.0 V supply and minimal LO power of −16 dBm, this mixer demonstrates a simulated power conversion gain of 17.2 dB with Double Side Band (DSB) noise figure of 13.3 dB. With the same DC power dissipation and LO power, −11.7 dBm IIP3 and −20.1 dBm 1-dB point have been obtained as discussed in the paper. Pre-layout and post layout simulation results match very well. The ultra-low power consumption of the proposed mixer due to subthreshold region of operation and lower local oscillator power are the advantages of this subthreshold mixer.
In this report a transistor-level design of a GHz ∑Δ analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational... more
In this report a transistor-level design of a GHz ∑Δ analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers. The clock frequency used for verification was 2.5 GHZ and the output bandwidth was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.
In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18µm CMOS process model. Simulation... more
In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18µm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25µw quiescent power with 2GHz bandwidth and 1.5% THD.
Image Morphing is one of the most powerful Digital Image processing technique, which is used to enhance many multimedia projects, presentations, education and computer based training. It is also used in medical imaging field to recover... more
Image Morphing is one of the most powerful Digital Image processing technique, which is used to enhance many multimedia projects, presentations, education and computer based training. It is also used in medical imaging field to recover features not visible in images by establishing correspondence of features among successive pair of scanned images. This paper discuss what morphing is and implementation of Triangulation based morphing Technique and Feature based Image Morphing. IT analyze both morphing techniques in terms of different attributes such as computational complexity, Visual quality of morph obtained and complexity involved in selection of features.
Signal & Image Processing : An International Journal is an Open Access peer-reviewed journal intended for researchers from academia and industry, who are active in the multidisciplinary field of signal & image processing. The scope of the... more
Signal & Image Processing : An International Journal is an Open Access peer-reviewed journal intended for researchers from academia and industry, who are active in the multidisciplinary field of signal & image processing. The scope of the journal covers all theoretical and practical aspects of the Digital Signal Processing & Image processing, from basic research to development of application.
Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Signal & Image processing.
A triple-band (TB) oscillator was implemented in the TSMC 0.18 μm 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6th order resonator with three resonant frequencies. The oscillator... more
A triple-band (TB) oscillator was implemented in the TSMC 0.18 μm 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6th order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) mA and 2.4(2.29, 2.28) mW, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68GHz,5.82-6.15GHz, and 3.68-4.08 GHz. The die area of the triple-band oscillator is 0.835× 1.103 mm2.
Abstract: In this paper, a general two-admittance current-mode circuit structure using Dual-Output OTA (DO-OTA) is explored to derive new second-order and fourth-order band-pass filters. The proposed second-order band-pass filter circuits... more
Abstract: In this paper, a general two-admittance current-mode circuit structure using Dual-Output OTA (DO-OTA) is explored to derive new second-order and fourth-order band-pass filters. The proposed second-order band-pass filter circuits offer advantageous features like ease of design, good sensitivity and orthogonal tunability of pole-Q. The proposed fourth-order band-pass filter circuit is attractive as it requires less number of OTAs and capacitors. PSPICE simulation results are given for the proposed circuits.
—This paper presents a low-cost implementation and measurement setup of an accurate Time–to-Digital converter (TDC). The design was realized using ring oscillator-based TDC architecture. The circuit consists of two ring oscillators having... more
—This paper presents a low-cost implementation and measurement setup of an accurate Time–to-Digital converter (TDC). The design was realized using ring oscillator-based TDC architecture. The circuit consists of two ring oscillators having slightly different frequencies. The TDC accuracy is determined by the difference between the periods of the two oscillators. Since that the silicon prototyping is costly and time consuming, the design was implemented and tested on low-cost Xilinx Spartan-3AN field-programmable gate array (FPGA) platform. In addition, a low-cost, yet accurate, measurement platform is presented. The post synthesis simulation and measurement results showed that the design was capable of measuring a pulse width as narrow as 23 pSec. The design is intended to be used in low-power low-cost level-crossing analog to digital converters.
– Clock-Data recovery (CDR) architecture with multi-rate option in receiver of a high-speed serial link presented. Proper clock phase choosing and let it track data phase shifts over time are the main difficulties of all kind of CDR... more
– Clock-Data recovery (CDR) architecture with multi-rate option in receiver of a high-speed serial link presented. Proper clock phase choosing and let it track data phase shifts over time are the main difficulties of all kind of CDR structures. This system helps to shift reference clock according to data signal phase to sample it in the most secure way regarding data errors and information loses. Meanwhile, since data signal can change phase over time due to noises and other uncertainties (jitter in the input point of receiver), CDR system should have some tracking option which could track data phase shifts over time and accordingly change phase of reference clock which coming from PLL. Such kind of systems are used in high and super speed serial links and makes information reading part of interfaces more safety and helps to decrease bit error rate (BER) of such systems. Proposed architecture has multi-rate options which increase system universality. Structure is 15% more jitter tolerance than USB specification required and hence it can be used in the special input/output circuits of Universal Serial Bus (USB) and some other protocols as well. Keywords – receiver (RX), transmitter (TX), clock-data recovery (CDR), bit error rate (BER), serial link, jitter, process-voltage-temperature (PVT)
Voltage Controlled Oscillator is one of the most important basic building block for analog, digital as well as in mixed signal circuits. This paper presents a new technique to improve the performance of ring oscillator. The VCO is based... more
Voltage Controlled Oscillator is one of the most important basic building block for analog, digital as well as in mixed signal circuits. This paper presents a new technique to improve the performance of ring oscillator. The VCO is based on single ended ring oscillator. The circuit is designed using 0.13 μm CMOS technology with supply voltage of 3.3 V. A VCO with high frequency range from 2.26GHz to 3.50 GHz is achieved by using this technique. Simulation results reveal the better performance of the proposed design as compared to existing current staved ring VCO in terms of oscillation frequency and power consumption.
Behavioral modeling of nonlinear passband systems like radio frequency power amplifiers is mainly based on polynomial baseband models. Motivated by the convolution property of the Fourier transform applied to passband signals, it is... more
Behavioral modeling of nonlinear passband systems like radio frequency power amplifiers is mainly based on polynomial baseband models. Motivated by the convolution property of the Fourier transform applied to passband signals, it is common practice to include only odd-order terms in these models. Experimental results show, however, that significant improvements can be achieved by also including even-order terms. In this paper, the fundamental relationship of even-order terms in polynomial passband and baseband models is analyzed, providing a theoretical foundation for the improved modeling accuracy of polynomial baseband models with even-order terms.
— This paper presents a new technique for a low-power low delay dispersion comparator for low-cost high-speed level-crossing Analog-to-Digital Converters (LC-ADCs). Only three transistors, representing a variable driving-current block... more
— This paper presents a new technique for a low-power low delay dispersion comparator for low-cost high-speed level-crossing Analog-to-Digital Converters (LC-ADCs). Only three transistors, representing a variable driving-current block (VDCB), have been added to the conventional comparator circuit. The VDCB works to control the charging behavior of the difference amplifier' output node such that it is supplied with a current that is inversely proportional with the difference between the positive and negative inputs (overdrive voltage). The modification incurs small area overhead and low power consumption compared with the previous works. The proposed circuit is implemented in 130nm technology. The simulation results show that the overdrive-related propagation delay dispersion of the proposed technique is 23% of its counterpart in the conventional comparator for an input frequency up to 600MHz. The active area of the technique 140.2 μm2 and the power consumption is 227μW at 200MHz. The proposed circuit is also design and simulated using 45nm technology. The simulation results came in the same direction, which implies that the proposed circuit is scalable.
A GPS and Miracast RFIC-on-chip antenna in 0.18 um CMOS 1p6M process is presented. The HFSS 3-D EM simulator is employed for design simulation. A printed 1.575GHz and 2.4GHz antenna has been realized by using the CMOS RFIC-on-chip. The... more
A GPS and Miracast RFIC-on-chip antenna in 0.18 um CMOS 1p6M process is presented. The HFSS 3-D EM simulator is employed for design simulation. A printed 1.575GHz and 2.4GHz antenna has been realized by using the CMOS RFIC-on-chip. The measured VSWR is less than 2 from 1.575GHz and 2.4- to 2.483-GHz. This propose super quadric combo antenna in free space, electromagnetic coupling between super quadric antenna and human body and rectangular antenna for wrist watch type wireless communication applications. The measured phase distribution of the input impedance is quite linear and the H-plane patterns are almost omnidirectional and field tried GPS integration. In addition, in order to improve the way controlling this provide switch by software, a novel circuit structure which will control antenna pattern switching automatically by hardware is also developed for wireless healthcare and mobile biomedical application. RFIC-on-chip GPS and Miracast antenna also merger T/R-Switch design on single chip solution for 2.4GHz CMOS transceiver RF front-end. The old man can monitor healthcare and transfer to health center or passive devices by Miracast with software and show GPS location for wearable ambulatory application.
This application is an On the Go diagnosis system to measure lifesaving vital signs like Cardio-graph, Oxygen content and Temperature sensor all inclusive under 40$. The complete unit gives the option of three diagnostic devices built... more
This application is an On the Go diagnosis system to measure lifesaving vital signs like Cardio-graph, Oxygen content and Temperature sensor all inclusive under 40$. The complete unit gives the option of three diagnostic devices built into one with a variety of display unit like TV Set and an Mounted TFT LCD. The complete device has been designed to be an interactive one with user friendly interface to choose between either of the working modes available in the unit. The option of SD Card storage gives the option of plotting the data on distant doctor's computer wirelessly or on his Android Device.
This paper presents the new OTA-C current-mode/ transimpedance second-order continuous-time filters based on passive R-L-C circuits using component substitution method. The resistor and inductor in these biquads are realized using OTA-C... more
This paper presents the new OTA-C current-mode/ transimpedance second-order continuous-time filters based on passive R-L-C circuits using component substitution method. The resistor and inductor in these biquads are realized using OTA-C counterparts. The current through resistor/ inductor is used to implement useful current-mode transfer functions in addition to transimpedance filters. The current through resistor/ inductor is made available using a dual output OTA (DO-OTA) in place of single output OTA (SO-OTA). The proposed biquads are attractive due to their advantageous features like ease of design, good sensitivity and orthogonal tunability of pole-Q. The biquads have been simulated using practical OTAs as well as their behavioral macro-model and the results are given to verify the theoretical analysis.
