2018 International Conference on Advanced Computation and Telecommunication (ICACAT)
A Women safety band (WSB) is a technology used to protect women from various and unnecessary dang... more A Women safety band (WSB) is a technology used to protect women from various and unnecessary dangerous situation. This paper presents switch-over text messaging and also describes various uses advantages of women protection band and also compares the technologies developed in the field of women security. The device mainly works on the principle of global positioning system, Bluetooth, multiple functioning microcontroller and switch over methodology. Meanwhile, the device can be easily made compatible with the smartphone having an app named “ALERT” which can be downloaded from google play store.
— Voltage controlled Oscillators or Ring Oscillators are crucial components in any timing and mem... more — Voltage controlled Oscillators or Ring Oscillators are crucial components in any timing and memory circuits. The goal of this paper is to do physical design for a high speed, low power consumption multistage high performance ring oscillator circuit based on 300 nm CMOS technology which provides frequency of high order (KHz). This oscillator is used for high speed wireless communication applications and in control circuitries of numerous analog and digital integrated circuits. This ring oscillator is designed to be controlled in a oscillation frequency by a voltage input. The physical design will include C5 process, simultaneously various design rule check and network consistency checks were performed to improve performance characteristics of the oscillator. The Complementary-Metal-Oxide-Semiconductor (CMOS) is the most popular technology for the modern integrated circuit design and fabrication. Based on this technology, a VCO can be implemented by the LC resonant or Ring structure...
2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), 2017
The differential amplifier is mostly used as an input to allow supply voltages to propagate so th... more The differential amplifier is mostly used as an input to allow supply voltages to propagate so that further gain stages in operational amplifier which are also function of input biasing voltages didn't get affected. The differential amplifiers are also fundamental building block of advanced analog integrated circuits in our presented design multistage operational amplifier design. Design presented in this paper is a multistage CMOS differential amplifiers and time and frequency analysis of the same is also carried out and evaluated the effect of various parameters on the characteristics of differential amplifier, which operates at suitable biasing sources using C5 process for scalable CMOS technology. Differential amplifier design presented here in this paper will be implemented using Electric VLSI 9.06. Simulation outcomes and further analysis is tabulated using LTSpiceXVII. There are numerous number of configurations for operational amplifier exists in literature. The presented designs will also define the operating characteristics of differential amplifiers; a brief comparison is also presented for operating point analysis for multiple stage operational amplifiers. FFT analysis is also done for better noise index results. Here parameters are computed and response curves are computed.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
Noise behavior in microelectronic devices is mainly contributed by shot noise, thermal noise and ... more Noise behavior in microelectronic devices is mainly contributed by shot noise, thermal noise and flicker noises, avalanche noise and burst noises etc. Other factors that constitute to noise are various generation and recombination procedures, power lines and scaling technology associated in CMOS designs. Thermal noise or noise due to thermal agitations with flicker noise are the primary noise sources in scalable MOSFET circuit designs however there are many more sources of noise. This paper analyzes how input referred noise sources are summed up to a CMOS design model to calculate output noise. The noise temperature and its impact on performance of a CMOS design will also be in consideration along with characterization of input and output noises.
International journal of advanced research in electrical, electronics and instrumentation engineering, 2015
System on chip is integration of multimillion transistors in single chip for reducing the cost of... more System on chip is integration of multimillion transistors in single chip for reducing the cost of design. With the new level of integration the System on Chip design is methodology where intellectual property blocks combined on single chip and allow huge chips to be design at acceptable cost and quality. Hence a standard interface bus protocol is required to increase the productivity with design time reduction. Wishbone is flexible System on Chip bus architecture, connecting IP cores together and alleviating System on Chip integration problems. Wishbone can communicate over variety of devices. Motivated by this, this paper presents different feature of wishbone bus interface. TheSoC design with DMA master cores and memory slave cores using wishbone point to point interconnection and shared bus interconnection scheme has been designed in Xilinx 12.3. This paper investigates and compare wishbone interconnection point to point and shared scheme.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
MIPS abbreviation for Microprocessor without Interlocked Pipeline Stages it is an efficient versi... more MIPS abbreviation for Microprocessor without Interlocked Pipeline Stages it is an efficient version of RISC reduced instruction set computer. The MIPS processor is practiced and used often in because it has moderate level of complexity to comprise of features of futurist computational units, but isn’t highly complex. The latest version of MIPS processor is MIPS32/64 Release 6.In the previous to previous decade it is the most widely used processing unit that the predictions were made that it will be used each and every electronic designs and systems in the future and the area of application it will cover will be very vast like in Gaming Consoles to advance defense technologies. In this paper a brief study of 8-bit MIPS processor is carried out with few basic simulations. The design software used for implementation is Electric CAD and simulations are carried out using LTSpice.
International Journal for Scientific Research and Development, 2013
the design of VLSI circuits can be achieved at many different refinement levels from the most det... more the design of VLSI circuits can be achieved at many different refinement levels from the most detailed layout to the most abstract architectures. VLSI design has been the study of electronic design automation and related semiconductor science, and many software tools have been written to solve one or more problems associated with the VLSI design flow. VLSI CAD tools have emerged as a boon in assisting VLSI Design engineers to choose and optimize various design models and technology. The importance of CAD tool can be understood by seeing its complex algorithms, data structures and modeling assumptions used in each of the following steps namely logic synthesis, logic verification, layout synthesis, timing verification and many others. Thus a number of standard tools have emerged to design and analyze VLSI chip from one step of the flow to another. Computer-aided design (CAD) is the use of computer systems to assist in the creation, modification, analysis, or optimization of a design. ...
This paper deals with the design, implementation and analysis of multistage CMOS operational ampl... more This paper deals with the design, implementation and analysis of multistage CMOS operational amplifier. The technology employed for designing is 300nm C5 process CMOS technology. The CAD tool used for designing and simulation are Electric CAD and LTspice respectively. DC, AC and Transient analysis are carried out to study the response. Under this analysis various parameters of Op-amp such as Unity Gain Bandwidth, Phase Margin, Slew Rate, DC transfer characteristics, Gain Margin, Rise Time, CMRR, Settling Time, Output Swing, Gain etc are computed and response curves are plotted. The Operational Amplifiers are designed to exhibit properties with unity gain frequency of 25 MHz, gain of 77.25dB and a phase margin of 60 o or more. The design and simulations are carried out to achieve these values approximately. Two stage and three stage configurations are suitable choices for low voltage and high performance application.
Image compression is the method to decrease insignificance and redundancy of image data in order ... more Image compression is the method to decrease insignificance and redundancy of image data in order to store or transmit image in a competent form. The essential information is extracted by using different transform techniques such that it can be reconstructed without ruining quality and information of the image. The paper presents a peculiar Hybrid Wavelet Transform genesis technique for Image compression using two orthogonal transforms. The concept of hybrid wavelet transform is to combine the attributes of two or more different orthogonal transform wavelet to attain the vitality of multiple transform wavelet. Here approach is to generate hybrid wavelet transform using three orthogonal transform using together Discrete Cosine transform, Discrete Wavelet transform and Discrete Kekre Transform which all are lossy compression techniques. On several image simulation has been carried out. The result has shown that hybrid transform wavelet performance is best as compared to transform wavel...
This paper suggests a spatially adaptive image denoising scheme, which is comprised of two stages... more This paper suggests a spatially adaptive image denoising scheme, which is comprised of two stages. In the first stage, image is denoised by using Principal Component Analysis (PCA) with Local Pixel Grouping (LPG). LPG-PCA can effectively preserve the image fine structures while denoising. In the second stage, we use Steerable Pyramid Transform (SPT) to decompose images into frequency sub-bands. The noise level is updated adaptively before second stage denoising. Steerable Pyramid Transform in the second stage further improves the denoising performance. This paper also reviews on the present denoising processes and performs their comparative study. Experimental results demonstrate that the proposed PCA-SPT algorithm achieve competitive outcomes. PCA-SPT works well in image fine structure preservation, compared with state-of-the-art denoising algorithms.
High quality color image obliged expansive measure of space to store and extensive data transmiss... more High quality color image obliged expansive measure of space to store and extensive data transmission t transmit it. Because of impediments in data transfer capacity and away space, it is primary prerequisite to layers compute riz d color image. To meet this, various picture pressure proce dures are created in last a few years. This research paper pre sents a peculiar Hybrid Wavelet Transform technique for Ima ge compression using three orthogonal transforms. The concept of hybrid wavelet transform is to combine the attribut es of two or more different orthogonal transform wavelet to attai n the vitality of multiple transform wavelet. Proposed approach is to generate hybrid wavelet transform with three orthogonal trans form using together which are Discrete Cosine transform, Discret e Wavelet transform and Discrete Kekre Transform. These all ar e lossy compression techniques. On several image simulation has been carried out. The experimental result has shown that hybrid transform wav...
2016 IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS), 2016
This paper presents a design and detailed FFT analysis for CMOS sense amplifiers. Sense amplifier... more This paper presents a design and detailed FFT analysis for CMOS sense amplifiers. Sense amplifiers in association with semiconductor memories are the key elements in defining the overall performance of CMOS memories. The presented design is implemented using C5 process technology using BSIM-4 Spice models. The design includes circuit and operation descriptions, transient signal analysis, FFT analysis, also evaluation of magnitude, phase, and group delay is done at range frequency range from 100 MHz to 10 THz. The paper also presents a physical design and interfacing logic for interfacing CMOS Memory arrays to Sense amplifiers and related control circuits.
Open cores soc design methodology utilize wishbone bus interface. Main aim of the wishbone bus is... more Open cores soc design methodology utilize wishbone bus interface. Main aim of the wishbone bus is to provide bus interface using reusable IP block. IP cores allow designing of huge chips at acceptable cost and quality, utilize wishbone as portable interface alleviation system on chip integration problem. To have implementation skill and optimization close to efficient SOC integration this paper present soc design level based on intellectual property blocks and IP core interface in context to wishbone is discuss. Better exploring the soc design, Wishbone master and slave IP cores generation is done utilizing DMA as master and memory as slave. The functionality of cores are verified in questasim.
Memory design is one of the interesting subjects in semiconductor technology. They have fascinate... more Memory design is one of the interesting subjects in semiconductor technology. They have fascinated world through storage of data values and program instructions. Cell structure and topology is governed by the technology. The proposed memory design takes into account the type of memory unit that is preferable for a given technology and application and is a function of the required memory size, the time it takes to access the memory data, other access patterns and configuration to optimize the memory architecture for low power design and more importantly over all system requirements. The project is dealt with basic memory architecture and their essential peripheral blocks. The peripheral blocks include the address decoders, sense amplifiers, voltage references, drivers, buffers, timing and control. In this design we will be defining our memory size in bits. The proposed size of the array is 4 - 64 bits i.e. 2x2 to 8 x 8 arrays. Moreover this CMOS memory design will also be including s...
Embedded system requires a design which combines hardware and software. The key of embedded syste... more Embedded system requires a design which combines hardware and software. The key of embedded system is embedded microcontroller. Embedded computing both hardware and software occupy an important place in India’s economy by providing more than billions jobs in this sector. Embedded system is trend for engineers. Real world problem importantly in embedded system is hardware and software design and utilization. The concept underlying theory in embedded hardware i.e. microcontroller and microprocessor platform and embedded software ie. Programming in c, c++, java etc requires challenging task, integration and testing to students both graduate and post graduate. To have implementation skill and optimization close to ‘embedded microcontroller’ platform this paper address basic skill in hardware, software design and development to understand the theory and is very important in context to products development approach. The purpose of this paper is to present our approach in learning software...
Imperial journal of interdisciplinary research, 2016
This paper presents the SQNR and sampling frequency analysis of 4 th order VCO based ADC. The 4 t... more This paper presents the SQNR and sampling frequency analysis of 4 th order VCO based ADC. The 4 th order VCO-ADC has been explored on 50 nm MOCMOS technology which measures SQNR of 76.8 dB over 127 GHz frequency and 304.8 GHz sampling frequency using 5V supply. The quantization error has been fed in the feedback loop to perform the noise shaping.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
This paper presents incorporates reference designs of Sense amplifiers and detailed FFT output pl... more This paper presents incorporates reference designs of Sense amplifiers and detailed FFT output plots in terms of amplitude or magnitude, phase and delay for scalable CMOS sense amplifiers using 300nm VLSI technology for scalable MOSFET transistor. Sensing defined as determination and detection of data contents in a particular or directed memory cell or binary bit. Sense amplifier circuits are used parallely with semiconductor memories namely DRAM SRAM and are main elements in defining the price, power and most importantly evaluation or appraisal of scalable CMOS semiconductor circuits or memories. The presented circuit topologies in this paper are made by using 0.3μm library model process technology using BSIM4 SPICE models. The presented paper also incorporates circuits operational descriptions, timing analysis, plots of FFT, also tabulation of amplitude, phase, and delay is done at range frequency range from few MHz to 10 THz. Here a layout view or backend design and connection logic for DRAM arrays to SCMOS Sense circuits amplifiers. DRC and NCC checks are also performed on the same.
2nd International Conference on Data, Engineering and Applications (IDEA), 2020
Computer vision is a field of computer systems that can comprehend images and scenes and also ide... more Computer vision is a field of computer systems that can comprehend images and scenes and also identify them. Computer vision technology is very popular in recent times and it has numerous applications namely smart monitoring and surveillance, drones, medicine, sports, entertainment, industrial robotics and self driving cars. Image localization, classification and detection are the basis of the above technology applications. Current improvements in Convolutional Neural Networks i.e. CNNs also lead to exceptional feat in tasks related to visual identification. CNNs are largely applicable for image classification tasks, particularly, looking at an image and classifying various features in it. In this paper study is carried out on various computer vision algorithms and deep learning techniques and corresponding tools for object detection in autonomous self driving cars. Deep learning has revolutionized computer vision techniques namely for object detection. CNN for object detection include three main deep learning techniques; SSD (Single shot multibox detector), R-CNN i.e. Region based CNN, R-FCN i.e. Region based fully convolutional networks. In this paper, an effort is made to show how above deep learning techniques are effective in ameliorating pre-trained networks' performance using existing datasets under different weather and terrestrial conditions. A brief comparison is also done for human centered autonomy and full autonomy for self driving cars.
2016 IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS), 2016
In this paper the design of multipliers which is less complex and power consuming is made of basi... more In this paper the design of multipliers which is less complex and power consuming is made of basic electronic components such as gates and adders. This design lowers the complexity of the circuit and works on the basic principle of multiplication and less number of transistors. The results show the multiplier is less complex and works effectively in large multiplications.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
Ring Oscillators are basic blocks of key digital modules like PLL, microprocessor or any other ti... more Ring Oscillators are basic blocks of key digital modules like PLL, microprocessor or any other time related and memory driven circuits. The purpose of this paper is to compare transients and analyze FFT of multistage ring oscillators and physical design of the same. Additional DRC and NCC checks are applied on the design using 300 nm process technologies. Ring oscillator design presented is driven and controlled by a voltage bias that can be varied by SPICE code. Here a VCO based design is presented that had less floor plan area, lesser power dissipation and consumption and also providing better noise profile which is helpful and applicable for wideband analog mixed signal circuits. Ring Oscillators in this paper, 11 stages, 21 stages and 51 stages are presented. and suitable transients and FFT is done on the design. The paper will also consider a variety of design considerations which are SCMOS cell designs, supply or biasing circuitries and tool based implementation and SPICE based simulations of the multistage oscillator design.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT)
A Women safety band (WSB) is a technology used to protect women from various and unnecessary dang... more A Women safety band (WSB) is a technology used to protect women from various and unnecessary dangerous situation. This paper presents switch-over text messaging and also describes various uses advantages of women protection band and also compares the technologies developed in the field of women security. The device mainly works on the principle of global positioning system, Bluetooth, multiple functioning microcontroller and switch over methodology. Meanwhile, the device can be easily made compatible with the smartphone having an app named “ALERT” which can be downloaded from google play store.
— Voltage controlled Oscillators or Ring Oscillators are crucial components in any timing and mem... more — Voltage controlled Oscillators or Ring Oscillators are crucial components in any timing and memory circuits. The goal of this paper is to do physical design for a high speed, low power consumption multistage high performance ring oscillator circuit based on 300 nm CMOS technology which provides frequency of high order (KHz). This oscillator is used for high speed wireless communication applications and in control circuitries of numerous analog and digital integrated circuits. This ring oscillator is designed to be controlled in a oscillation frequency by a voltage input. The physical design will include C5 process, simultaneously various design rule check and network consistency checks were performed to improve performance characteristics of the oscillator. The Complementary-Metal-Oxide-Semiconductor (CMOS) is the most popular technology for the modern integrated circuit design and fabrication. Based on this technology, a VCO can be implemented by the LC resonant or Ring structure...
2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), 2017
The differential amplifier is mostly used as an input to allow supply voltages to propagate so th... more The differential amplifier is mostly used as an input to allow supply voltages to propagate so that further gain stages in operational amplifier which are also function of input biasing voltages didn't get affected. The differential amplifiers are also fundamental building block of advanced analog integrated circuits in our presented design multistage operational amplifier design. Design presented in this paper is a multistage CMOS differential amplifiers and time and frequency analysis of the same is also carried out and evaluated the effect of various parameters on the characteristics of differential amplifier, which operates at suitable biasing sources using C5 process for scalable CMOS technology. Differential amplifier design presented here in this paper will be implemented using Electric VLSI 9.06. Simulation outcomes and further analysis is tabulated using LTSpiceXVII. There are numerous number of configurations for operational amplifier exists in literature. The presented designs will also define the operating characteristics of differential amplifiers; a brief comparison is also presented for operating point analysis for multiple stage operational amplifiers. FFT analysis is also done for better noise index results. Here parameters are computed and response curves are computed.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
Noise behavior in microelectronic devices is mainly contributed by shot noise, thermal noise and ... more Noise behavior in microelectronic devices is mainly contributed by shot noise, thermal noise and flicker noises, avalanche noise and burst noises etc. Other factors that constitute to noise are various generation and recombination procedures, power lines and scaling technology associated in CMOS designs. Thermal noise or noise due to thermal agitations with flicker noise are the primary noise sources in scalable MOSFET circuit designs however there are many more sources of noise. This paper analyzes how input referred noise sources are summed up to a CMOS design model to calculate output noise. The noise temperature and its impact on performance of a CMOS design will also be in consideration along with characterization of input and output noises.
International journal of advanced research in electrical, electronics and instrumentation engineering, 2015
System on chip is integration of multimillion transistors in single chip for reducing the cost of... more System on chip is integration of multimillion transistors in single chip for reducing the cost of design. With the new level of integration the System on Chip design is methodology where intellectual property blocks combined on single chip and allow huge chips to be design at acceptable cost and quality. Hence a standard interface bus protocol is required to increase the productivity with design time reduction. Wishbone is flexible System on Chip bus architecture, connecting IP cores together and alleviating System on Chip integration problems. Wishbone can communicate over variety of devices. Motivated by this, this paper presents different feature of wishbone bus interface. TheSoC design with DMA master cores and memory slave cores using wishbone point to point interconnection and shared bus interconnection scheme has been designed in Xilinx 12.3. This paper investigates and compare wishbone interconnection point to point and shared scheme.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
MIPS abbreviation for Microprocessor without Interlocked Pipeline Stages it is an efficient versi... more MIPS abbreviation for Microprocessor without Interlocked Pipeline Stages it is an efficient version of RISC reduced instruction set computer. The MIPS processor is practiced and used often in because it has moderate level of complexity to comprise of features of futurist computational units, but isn’t highly complex. The latest version of MIPS processor is MIPS32/64 Release 6.In the previous to previous decade it is the most widely used processing unit that the predictions were made that it will be used each and every electronic designs and systems in the future and the area of application it will cover will be very vast like in Gaming Consoles to advance defense technologies. In this paper a brief study of 8-bit MIPS processor is carried out with few basic simulations. The design software used for implementation is Electric CAD and simulations are carried out using LTSpice.
International Journal for Scientific Research and Development, 2013
the design of VLSI circuits can be achieved at many different refinement levels from the most det... more the design of VLSI circuits can be achieved at many different refinement levels from the most detailed layout to the most abstract architectures. VLSI design has been the study of electronic design automation and related semiconductor science, and many software tools have been written to solve one or more problems associated with the VLSI design flow. VLSI CAD tools have emerged as a boon in assisting VLSI Design engineers to choose and optimize various design models and technology. The importance of CAD tool can be understood by seeing its complex algorithms, data structures and modeling assumptions used in each of the following steps namely logic synthesis, logic verification, layout synthesis, timing verification and many others. Thus a number of standard tools have emerged to design and analyze VLSI chip from one step of the flow to another. Computer-aided design (CAD) is the use of computer systems to assist in the creation, modification, analysis, or optimization of a design. ...
This paper deals with the design, implementation and analysis of multistage CMOS operational ampl... more This paper deals with the design, implementation and analysis of multistage CMOS operational amplifier. The technology employed for designing is 300nm C5 process CMOS technology. The CAD tool used for designing and simulation are Electric CAD and LTspice respectively. DC, AC and Transient analysis are carried out to study the response. Under this analysis various parameters of Op-amp such as Unity Gain Bandwidth, Phase Margin, Slew Rate, DC transfer characteristics, Gain Margin, Rise Time, CMRR, Settling Time, Output Swing, Gain etc are computed and response curves are plotted. The Operational Amplifiers are designed to exhibit properties with unity gain frequency of 25 MHz, gain of 77.25dB and a phase margin of 60 o or more. The design and simulations are carried out to achieve these values approximately. Two stage and three stage configurations are suitable choices for low voltage and high performance application.
Image compression is the method to decrease insignificance and redundancy of image data in order ... more Image compression is the method to decrease insignificance and redundancy of image data in order to store or transmit image in a competent form. The essential information is extracted by using different transform techniques such that it can be reconstructed without ruining quality and information of the image. The paper presents a peculiar Hybrid Wavelet Transform genesis technique for Image compression using two orthogonal transforms. The concept of hybrid wavelet transform is to combine the attributes of two or more different orthogonal transform wavelet to attain the vitality of multiple transform wavelet. Here approach is to generate hybrid wavelet transform using three orthogonal transform using together Discrete Cosine transform, Discrete Wavelet transform and Discrete Kekre Transform which all are lossy compression techniques. On several image simulation has been carried out. The result has shown that hybrid transform wavelet performance is best as compared to transform wavel...
This paper suggests a spatially adaptive image denoising scheme, which is comprised of two stages... more This paper suggests a spatially adaptive image denoising scheme, which is comprised of two stages. In the first stage, image is denoised by using Principal Component Analysis (PCA) with Local Pixel Grouping (LPG). LPG-PCA can effectively preserve the image fine structures while denoising. In the second stage, we use Steerable Pyramid Transform (SPT) to decompose images into frequency sub-bands. The noise level is updated adaptively before second stage denoising. Steerable Pyramid Transform in the second stage further improves the denoising performance. This paper also reviews on the present denoising processes and performs their comparative study. Experimental results demonstrate that the proposed PCA-SPT algorithm achieve competitive outcomes. PCA-SPT works well in image fine structure preservation, compared with state-of-the-art denoising algorithms.
High quality color image obliged expansive measure of space to store and extensive data transmiss... more High quality color image obliged expansive measure of space to store and extensive data transmission t transmit it. Because of impediments in data transfer capacity and away space, it is primary prerequisite to layers compute riz d color image. To meet this, various picture pressure proce dures are created in last a few years. This research paper pre sents a peculiar Hybrid Wavelet Transform technique for Ima ge compression using three orthogonal transforms. The concept of hybrid wavelet transform is to combine the attribut es of two or more different orthogonal transform wavelet to attai n the vitality of multiple transform wavelet. Proposed approach is to generate hybrid wavelet transform with three orthogonal trans form using together which are Discrete Cosine transform, Discret e Wavelet transform and Discrete Kekre Transform. These all ar e lossy compression techniques. On several image simulation has been carried out. The experimental result has shown that hybrid transform wav...
2016 IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS), 2016
This paper presents a design and detailed FFT analysis for CMOS sense amplifiers. Sense amplifier... more This paper presents a design and detailed FFT analysis for CMOS sense amplifiers. Sense amplifiers in association with semiconductor memories are the key elements in defining the overall performance of CMOS memories. The presented design is implemented using C5 process technology using BSIM-4 Spice models. The design includes circuit and operation descriptions, transient signal analysis, FFT analysis, also evaluation of magnitude, phase, and group delay is done at range frequency range from 100 MHz to 10 THz. The paper also presents a physical design and interfacing logic for interfacing CMOS Memory arrays to Sense amplifiers and related control circuits.
Open cores soc design methodology utilize wishbone bus interface. Main aim of the wishbone bus is... more Open cores soc design methodology utilize wishbone bus interface. Main aim of the wishbone bus is to provide bus interface using reusable IP block. IP cores allow designing of huge chips at acceptable cost and quality, utilize wishbone as portable interface alleviation system on chip integration problem. To have implementation skill and optimization close to efficient SOC integration this paper present soc design level based on intellectual property blocks and IP core interface in context to wishbone is discuss. Better exploring the soc design, Wishbone master and slave IP cores generation is done utilizing DMA as master and memory as slave. The functionality of cores are verified in questasim.
Memory design is one of the interesting subjects in semiconductor technology. They have fascinate... more Memory design is one of the interesting subjects in semiconductor technology. They have fascinated world through storage of data values and program instructions. Cell structure and topology is governed by the technology. The proposed memory design takes into account the type of memory unit that is preferable for a given technology and application and is a function of the required memory size, the time it takes to access the memory data, other access patterns and configuration to optimize the memory architecture for low power design and more importantly over all system requirements. The project is dealt with basic memory architecture and their essential peripheral blocks. The peripheral blocks include the address decoders, sense amplifiers, voltage references, drivers, buffers, timing and control. In this design we will be defining our memory size in bits. The proposed size of the array is 4 - 64 bits i.e. 2x2 to 8 x 8 arrays. Moreover this CMOS memory design will also be including s...
Embedded system requires a design which combines hardware and software. The key of embedded syste... more Embedded system requires a design which combines hardware and software. The key of embedded system is embedded microcontroller. Embedded computing both hardware and software occupy an important place in India’s economy by providing more than billions jobs in this sector. Embedded system is trend for engineers. Real world problem importantly in embedded system is hardware and software design and utilization. The concept underlying theory in embedded hardware i.e. microcontroller and microprocessor platform and embedded software ie. Programming in c, c++, java etc requires challenging task, integration and testing to students both graduate and post graduate. To have implementation skill and optimization close to ‘embedded microcontroller’ platform this paper address basic skill in hardware, software design and development to understand the theory and is very important in context to products development approach. The purpose of this paper is to present our approach in learning software...
Imperial journal of interdisciplinary research, 2016
This paper presents the SQNR and sampling frequency analysis of 4 th order VCO based ADC. The 4 t... more This paper presents the SQNR and sampling frequency analysis of 4 th order VCO based ADC. The 4 th order VCO-ADC has been explored on 50 nm MOCMOS technology which measures SQNR of 76.8 dB over 127 GHz frequency and 304.8 GHz sampling frequency using 5V supply. The quantization error has been fed in the feedback loop to perform the noise shaping.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
This paper presents incorporates reference designs of Sense amplifiers and detailed FFT output pl... more This paper presents incorporates reference designs of Sense amplifiers and detailed FFT output plots in terms of amplitude or magnitude, phase and delay for scalable CMOS sense amplifiers using 300nm VLSI technology for scalable MOSFET transistor. Sensing defined as determination and detection of data contents in a particular or directed memory cell or binary bit. Sense amplifier circuits are used parallely with semiconductor memories namely DRAM SRAM and are main elements in defining the price, power and most importantly evaluation or appraisal of scalable CMOS semiconductor circuits or memories. The presented circuit topologies in this paper are made by using 0.3μm library model process technology using BSIM4 SPICE models. The presented paper also incorporates circuits operational descriptions, timing analysis, plots of FFT, also tabulation of amplitude, phase, and delay is done at range frequency range from few MHz to 10 THz. Here a layout view or backend design and connection logic for DRAM arrays to SCMOS Sense circuits amplifiers. DRC and NCC checks are also performed on the same.
2nd International Conference on Data, Engineering and Applications (IDEA), 2020
Computer vision is a field of computer systems that can comprehend images and scenes and also ide... more Computer vision is a field of computer systems that can comprehend images and scenes and also identify them. Computer vision technology is very popular in recent times and it has numerous applications namely smart monitoring and surveillance, drones, medicine, sports, entertainment, industrial robotics and self driving cars. Image localization, classification and detection are the basis of the above technology applications. Current improvements in Convolutional Neural Networks i.e. CNNs also lead to exceptional feat in tasks related to visual identification. CNNs are largely applicable for image classification tasks, particularly, looking at an image and classifying various features in it. In this paper study is carried out on various computer vision algorithms and deep learning techniques and corresponding tools for object detection in autonomous self driving cars. Deep learning has revolutionized computer vision techniques namely for object detection. CNN for object detection include three main deep learning techniques; SSD (Single shot multibox detector), R-CNN i.e. Region based CNN, R-FCN i.e. Region based fully convolutional networks. In this paper, an effort is made to show how above deep learning techniques are effective in ameliorating pre-trained networks' performance using existing datasets under different weather and terrestrial conditions. A brief comparison is also done for human centered autonomy and full autonomy for self driving cars.
2016 IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS), 2016
In this paper the design of multipliers which is less complex and power consuming is made of basi... more In this paper the design of multipliers which is less complex and power consuming is made of basic electronic components such as gates and adders. This design lowers the complexity of the circuit and works on the basic principle of multiplication and less number of transistors. The results show the multiplier is less complex and works effectively in large multiplications.
2018 International Conference on Advanced Computation and Telecommunication (ICACAT), 2018
Ring Oscillators are basic blocks of key digital modules like PLL, microprocessor or any other ti... more Ring Oscillators are basic blocks of key digital modules like PLL, microprocessor or any other time related and memory driven circuits. The purpose of this paper is to compare transients and analyze FFT of multistage ring oscillators and physical design of the same. Additional DRC and NCC checks are applied on the design using 300 nm process technologies. Ring oscillator design presented is driven and controlled by a voltage bias that can be varied by SPICE code. Here a VCO based design is presented that had less floor plan area, lesser power dissipation and consumption and also providing better noise profile which is helpful and applicable for wideband analog mixed signal circuits. Ring Oscillators in this paper, 11 stages, 21 stages and 51 stages are presented. and suitable transients and FFT is done on the design. The paper will also consider a variety of design considerations which are SCMOS cell designs, supply or biasing circuitries and tool based implementation and SPICE based simulations of the multistage oscillator design.
International Conference on Recent innovations in Signal Processing and Embedded Systems RISE 2... more International Conference on Recent innovations in Signal Processing and Embedded Systems RISE 2017 Physical Design, Implementatation and FFT analysis of multistage Differential Amplifiers Circuits using C5 Process for deep submicron CMOS
Tutorial presents a basic approach to microprocessor design.
A MIPS 8 bit design will be further ... more Tutorial presents a basic approach to microprocessor design. A MIPS 8 bit design will be further studied and implemented.
Electronics Design – complexities increases as the time progresses .
Design Methodologies and C... more Electronics Design – complexities increases as the time progresses . Design Methodologies and CAD tools (Design as well as Simulation)are integral parts in Electronics Design and go hand in hand and they evolve based on designer’s needs. CAD Tools allows the freedom to Electronics Designers to focus on creativity with respect to process technology. The development in the design tools, collaborative design methods, the role of human factors and integration factors in the design technology marks the outline of various design methodologies.
VLSI Design – complexities increases as the time progresses . Design Methodologies and CAD tools... more VLSI Design – complexities increases as the time progresses . Design Methodologies and CAD tools are integral parts in VLSI Design and go hand in hand and they evolve based on designer’s needs. CAD Tools allows the freedom to VLSI Designers to focus on creativity with respect to process technology. The development in the design tools, collaborative design methods, the role of human factors and integration factors in the design technology marks the outline of various design methodologies.
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Papers by Ayoush Johari
Physical Design, Implementatation and FFT analysis
of multistage Differential Amplifiers Circuits using
C5 Process for deep submicron CMOS
A MIPS 8 bit design will be further studied and implemented.
Design Methodologies and CAD tools (Design as well as Simulation)are integral parts in Electronics Design and go hand in hand and they evolve based on designer’s needs. CAD Tools allows the freedom to Electronics Designers to focus on creativity with respect to process technology. The development in the design tools, collaborative design methods, the role of human factors and integration factors in the design technology marks the outline of various design methodologies.