2017 International Conference on Computing Methodologies and Communication (ICCMC)
This paper emphasizes on the criticality of characterization and validation of compact models in ... more This paper emphasizes on the criticality of characterization and validation of compact models in RF Analog & Mixed Signal PDK development to ensure first pass silicon. The importance of predictive modeling comprising TCAD analysis, process and device simulations is emphasized in the context of emerging high frequency, technological advancements. An exhaustive study of the intricacies involved in the model development process, comprising model characterization, model qualification and model release flow to aid successful silicon implementation for RF applications has been presented in this paper. Compact models for active devices like NPNs and MOSFETs that are part of RF AMS PDK library are dealt in detail while touching passive device models at a high level. The importance of quality RF device models in the design environment has been discussed. The role of quality models in the RF design space to aid the designer to realize first pass silicon, contributing to the long term success of design houses, has been presented towards the end of the paper.
As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches... more As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this work are: 1) to theoretically explore the essential physics of SNWTs (e.g., electrostatics, transport and band structure) by performing computer-based simulations, and 2) to assess the performance limits and scaling potentials of SNWTs and to address the SNWT design issues. The computer based simulations carried out are essentially based on DFT using NEGF formalism. A silicon nanowire has been modeled as PN diode (Zener Diode), PIN diode, PIP & NIN diode configurations by selectively doping the nanowire and simulated by biasing one end of the nanowire to ground and sweeping ...
Fe/MgO/Fe magnetic tunnel junctions (MTJs) have been reported to have very high tunnel magnetores... more Fe/MgO/Fe magnetic tunnel junctions (MTJs) have been reported to have very high tunnel magnetoresistance (TMR) ratios. In this work, we present the results of First Principle simulations of Fe/ MgO/Fe MTJs with LSDA as the exchange correlation. The I-V characteristics in the antiparallel magnetization state exhibit strong features. The bias dependence of the TMR ratio shows nearly 100% TMR ratios for bias voltages up to 1.5 Volts. The MgO thickness dependence of the tunnel resistance shows the expected exponential increase in the tunnel resistance. The write energy per bit and power consumption have been computed for a bias voltage of 0.5 Volts. The Fe/MgO/Fe MTJs are the most widely used MTJs, integrated with NMOS transistors, in the form of MTJ based Magnetoresistive Random Access Memory (MRAM) which is an advanced memory technology operating at the nano scale. MRAMs are spintronic devices.
2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS), 2016
The paper reports the effect of scaling of device parameters like gate work function, nanowire di... more The paper reports the effect of scaling of device parameters like gate work function, nanowire diameter, gate oxide thickness and gate length on the electrical behavior of silicon nanowire field effect transistor based on uncoupled mode space NEGF transport model. The underlying physics behind the uncoupled mode space approach has been touched upon in this paper. By way of simulating several configurations of the nanowire transistor and observing the corresponding variations in the device behavior, the dependence of drain current on the scaled device parameters has been observed to arrive at optimum values of gate work function, diameter, gate oxide thickness and gate length out of all the configurations simulated that would enable the nanowire transistor to demonstrate higher drive current, lower subthreshold current thereby leading to lower power dissipation with minimal area and enhanced circuit speed owing to ballistic electron transport.
2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS), 2016
The effect of process and temperature variations are becoming more dominant with technology scali... more The effect of process and temperature variations are becoming more dominant with technology scaling, especially for RF circuits, wherein even the minute variability in FETs and passive devices have a significant impact on the overall circuit behavior. Due to stringent power and performance specification requirements in the latest Wireless/RF applications, reasonable compensation for the process, voltage and temperature variations, is even more critical. In this paper, the design of a 2.4GHz operated, ultra-low power CMOS down-converting active mixer fabricated in standard 180 nm RF CMOS technology has been presented. The mixer is based on double balanced Gilbert-cell resistor-loaded topology. The effects of process and temperature variations on the designed mixer have been investigated and various compensation techniques relevant to the current design have been analyzed.
This work aims to exploit the potential of nano scale memories like MTJ based Magnetoresistive RA... more This work aims to exploit the potential of nano scale memories like MTJ based Magnetoresistive RAM for use in cell phone architectures by replacing age old flash memories through a series of simulations performed using various tools. Magnetoresistive memory (MRAM) is one of the forerunners of the nanotechnology enabled memories lined to replace the traditional memories like Flash, DRAM and SRAM. MRAMs are based on the phenomenon of spin dependent tunneling in magnetic tunnel junctions (MTJs). It stores data in the magnetization of a magnetic layer as opposed to electrical charge in conventional RAMs. Yet the read-out of the MRAM is electrical. It is claimed to offer something close to the speed of SRAM, with a density approaching that of single-transistor DRAM and the ability to store information when power is removed, like flash memory or EEPROM.
There are various commercially available Analog/RF simulator tools currently in the market, which... more There are various commercially available Analog/RF simulator tools currently in the market, which have their distinctive applications and advantages. In this paper, some of the most widely used Analog/RF simulators (Cadence Spectre/APS, Keysight ADS and GoldenGate, and Mentor Graphics AFS) have been reviewed with respect to their performance and unique features. An LC-VCO and a CMOS Ring Oscillator are designed using GLOBALFOUNDRIES 45 nm RFSOI technology PDK. They are simulated using all the four listed simulators and their results have been analyzed with respect to performance and circuit design aspects.
Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law int... more Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. This paper reviews the process, application, device physics and compact modeling of Gate All around (GAA) nanowire MOSFETs. The most widely used methods of nanowire synthesis have been discussed. The paper presents the various device optimization techniques and scaling potential of nanowire transistors. A process sensitivity study of silicon nanowire transistors at the end of the paper justifies the theory of nanowire FETs to carry forward the downscaling of MOSFETs in the sub-10 nm regime. Keywords: Nanowire, scaling, MOSFET, VLS, nanoelectronics, short channel effects (SCEs), density of states, SiNWFET Cite this Article Chakraverty Mayank, Gupta Kinshuk, Babu Vinay G. et al. A Technological Review on Quantum Ballistic Transport Model Based Silicon Nanowire Field Effect Transistors for Circuit Simulation and Design. Journal of Nanoscience, Nanoengineering and Appl...
This paper reports the bias dependence of tunneling magnetoresistance in Co-MgO-Co magnetic tunne... more This paper reports the bias dependence of tunneling magnetoresistance in Co-MgO-Co magnetic tunnel junctions (MTJs) using first principles SGGA band structure calculations at four different temperatures. The Co-MgO-Co tunnel junction has been simulated at four different temperatures to obtain the I-V and dI/dV-V characteristics with parallel and anti-parallel magnetization states, respectively. The TMR ratios have been computed at all four different temperatures. It is seen that temperature doesn't seem to greatly fluctuate the TMR ratios of this magnetic tunnel junction, thereby making it suitable for applications over a wide range of temperatures. For the same four temperatures, the tunnel junction has been simulated for increasing insulator thicknesses. The exponential increase in resistance in both parallel and antiparallel magnetization states has been observed with an increase in the insulating layer thickness. The effect of increasing insulator thicknesses on the TMR rati...
With rapid advancements in the technology arena, novel design methodologies have been embraced an... more With rapid advancements in the technology arena, novel design methodologies have been embraced and to support these requirements, semiconductor process technology is also rapidly evolving. There is a need for efficient handshake between the foundry and design houses. PDKs play an important role in inheriting the foundry offering to aid in successful silicon realization. This paper presents an overview of process design kits and the importance of well-crafted kits in niche RF IC designs. The chip design ecosystem has been pictorially explained while emphasizing on the role of a foundry in the ecosystem. The different components of the process design kit have been discussed in brief. The method of qualification of process design kits and the various quality enhancement approaches to enable first pass silicon success have been presented in this paper. Towards the end of the paper, different substrate methodologies adopted by foundries for RF designs have been presented at a high level.
High gate leakage current, as a central problem, has decelerated the downscaling of minimum featu... more High gate leakage current, as a central problem, has decelerated the downscaling of minimum feature size of the field effect transistors In this paper, a combination of density functional theory and non equilibrium Green’s function formalism has been applied to the atomic scale calculation of the tunnel currents through CeO2, Y2O3, TiO2 and Al2O3 dielectrics in MOSFETs. The tunnel currents for different bias voltages applied to Si/Insulator/Si systems have been obtained along with tunnel conductance v/s bias voltage plots for each system. The results are in agreement to the use of high dielectric constant materials as gate dielectric so as to enable further downscaling of MOSFETs with reduced gate leakage currents thereby enabling ultra large scale integration. When used as dielectric, TiO2 exhibits extremely low tunnel currents followed by Y2O3 while CeO2 and Al2O3 exhibit high tunnel currents through them at certain bias voltages.
The effect of incorporating pairs of dopant atoms of opposite polarities into the nanowire lattic... more The effect of incorporating pairs of dopant atoms of opposite polarities into the nanowire lattice on the electrical behavior of nanowires has been presented in this paper. The dopants used are boron and phosphorus atoms. Intrinsic silicon nanowire is incapacitated with boron-phosphorus dopant atom pairs in a progressive manner, starting from one pair to nine dopant-atom pairs. The nanowire is simulated each time an additional dopant pair is introduced in the nanowire lattice to obtain current-voltage characteristics. These characteristics have been compared with that obtained by introducing similar dopants in an intrinsic germanium nanowire lattice. The power efficiencies of both intrinsic and doped silicon and germanium nanowires have been discussed towards the end of the paper.
This paper discusses the design of a 2.4 GHz operated, ultra-low power CMOS down-converting activ... more This paper discusses the design of a 2.4 GHz operated, ultra-low power CMOS down-converting active mixer based on double balanced Gilbert-cell resistor-loaded topology fabricated in standard 180 nm RF CMOS low-power technology. All the MOS transistors of the mixer core have ideally been biased to sub-threshold region. Consuming only 500 μW of DC power using 1.0 V supply and minimal LO power of −16 dBm, this mixer demonstrates a simulated power conversion gain of 17.2 dB with Double Side Band (DSB) noise figure of 13.3 dB. With the same DC power dissipation and LO power, −11.7 dBm IIP3 and −20.1 dBm 1-dB point have been obtained as discussed in the paper. Pre-layout and post layout simulation results match very well. The ultra-low power consumption of the proposed mixer due to subthreshold region of operation and lower local oscillator power are the advantages of this subthreshold mixer.
2017 International Conference on Computing Methodologies and Communication (ICCMC)
This paper emphasizes on the criticality of characterization and validation of compact models in ... more This paper emphasizes on the criticality of characterization and validation of compact models in RF Analog & Mixed Signal PDK development to ensure first pass silicon. The importance of predictive modeling comprising TCAD analysis, process and device simulations is emphasized in the context of emerging high frequency, technological advancements. An exhaustive study of the intricacies involved in the model development process, comprising model characterization, model qualification and model release flow to aid successful silicon implementation for RF applications has been presented in this paper. Compact models for active devices like NPNs and MOSFETs that are part of RF AMS PDK library are dealt in detail while touching passive device models at a high level. The importance of quality RF device models in the design environment has been discussed. The role of quality models in the RF design space to aid the designer to realize first pass silicon, contributing to the long term success of design houses, has been presented towards the end of the paper.
As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches... more As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this work are: 1) to theoretically explore the essential physics of SNWTs (e.g., electrostatics, transport and band structure) by performing computer-based simulations, and 2) to assess the performance limits and scaling potentials of SNWTs and to address the SNWT design issues. The computer based simulations carried out are essentially based on DFT using NEGF formalism. A silicon nanowire has been modeled as PN diode (Zener Diode), PIN diode, PIP & NIN diode configurations by selectively doping the nanowire and simulated by biasing one end of the nanowire to ground and sweeping ...
Fe/MgO/Fe magnetic tunnel junctions (MTJs) have been reported to have very high tunnel magnetores... more Fe/MgO/Fe magnetic tunnel junctions (MTJs) have been reported to have very high tunnel magnetoresistance (TMR) ratios. In this work, we present the results of First Principle simulations of Fe/ MgO/Fe MTJs with LSDA as the exchange correlation. The I-V characteristics in the antiparallel magnetization state exhibit strong features. The bias dependence of the TMR ratio shows nearly 100% TMR ratios for bias voltages up to 1.5 Volts. The MgO thickness dependence of the tunnel resistance shows the expected exponential increase in the tunnel resistance. The write energy per bit and power consumption have been computed for a bias voltage of 0.5 Volts. The Fe/MgO/Fe MTJs are the most widely used MTJs, integrated with NMOS transistors, in the form of MTJ based Magnetoresistive Random Access Memory (MRAM) which is an advanced memory technology operating at the nano scale. MRAMs are spintronic devices.
2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS), 2016
The paper reports the effect of scaling of device parameters like gate work function, nanowire di... more The paper reports the effect of scaling of device parameters like gate work function, nanowire diameter, gate oxide thickness and gate length on the electrical behavior of silicon nanowire field effect transistor based on uncoupled mode space NEGF transport model. The underlying physics behind the uncoupled mode space approach has been touched upon in this paper. By way of simulating several configurations of the nanowire transistor and observing the corresponding variations in the device behavior, the dependence of drain current on the scaled device parameters has been observed to arrive at optimum values of gate work function, diameter, gate oxide thickness and gate length out of all the configurations simulated that would enable the nanowire transistor to demonstrate higher drive current, lower subthreshold current thereby leading to lower power dissipation with minimal area and enhanced circuit speed owing to ballistic electron transport.
2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS), 2016
The effect of process and temperature variations are becoming more dominant with technology scali... more The effect of process and temperature variations are becoming more dominant with technology scaling, especially for RF circuits, wherein even the minute variability in FETs and passive devices have a significant impact on the overall circuit behavior. Due to stringent power and performance specification requirements in the latest Wireless/RF applications, reasonable compensation for the process, voltage and temperature variations, is even more critical. In this paper, the design of a 2.4GHz operated, ultra-low power CMOS down-converting active mixer fabricated in standard 180 nm RF CMOS technology has been presented. The mixer is based on double balanced Gilbert-cell resistor-loaded topology. The effects of process and temperature variations on the designed mixer have been investigated and various compensation techniques relevant to the current design have been analyzed.
This work aims to exploit the potential of nano scale memories like MTJ based Magnetoresistive RA... more This work aims to exploit the potential of nano scale memories like MTJ based Magnetoresistive RAM for use in cell phone architectures by replacing age old flash memories through a series of simulations performed using various tools. Magnetoresistive memory (MRAM) is one of the forerunners of the nanotechnology enabled memories lined to replace the traditional memories like Flash, DRAM and SRAM. MRAMs are based on the phenomenon of spin dependent tunneling in magnetic tunnel junctions (MTJs). It stores data in the magnetization of a magnetic layer as opposed to electrical charge in conventional RAMs. Yet the read-out of the MRAM is electrical. It is claimed to offer something close to the speed of SRAM, with a density approaching that of single-transistor DRAM and the ability to store information when power is removed, like flash memory or EEPROM.
There are various commercially available Analog/RF simulator tools currently in the market, which... more There are various commercially available Analog/RF simulator tools currently in the market, which have their distinctive applications and advantages. In this paper, some of the most widely used Analog/RF simulators (Cadence Spectre/APS, Keysight ADS and GoldenGate, and Mentor Graphics AFS) have been reviewed with respect to their performance and unique features. An LC-VCO and a CMOS Ring Oscillator are designed using GLOBALFOUNDRIES 45 nm RFSOI technology PDK. They are simulated using all the four listed simulators and their results have been analyzed with respect to performance and circuit design aspects.
Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law int... more Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. This paper reviews the process, application, device physics and compact modeling of Gate All around (GAA) nanowire MOSFETs. The most widely used methods of nanowire synthesis have been discussed. The paper presents the various device optimization techniques and scaling potential of nanowire transistors. A process sensitivity study of silicon nanowire transistors at the end of the paper justifies the theory of nanowire FETs to carry forward the downscaling of MOSFETs in the sub-10 nm regime. Keywords: Nanowire, scaling, MOSFET, VLS, nanoelectronics, short channel effects (SCEs), density of states, SiNWFET Cite this Article Chakraverty Mayank, Gupta Kinshuk, Babu Vinay G. et al. A Technological Review on Quantum Ballistic Transport Model Based Silicon Nanowire Field Effect Transistors for Circuit Simulation and Design. Journal of Nanoscience, Nanoengineering and Appl...
This paper reports the bias dependence of tunneling magnetoresistance in Co-MgO-Co magnetic tunne... more This paper reports the bias dependence of tunneling magnetoresistance in Co-MgO-Co magnetic tunnel junctions (MTJs) using first principles SGGA band structure calculations at four different temperatures. The Co-MgO-Co tunnel junction has been simulated at four different temperatures to obtain the I-V and dI/dV-V characteristics with parallel and anti-parallel magnetization states, respectively. The TMR ratios have been computed at all four different temperatures. It is seen that temperature doesn't seem to greatly fluctuate the TMR ratios of this magnetic tunnel junction, thereby making it suitable for applications over a wide range of temperatures. For the same four temperatures, the tunnel junction has been simulated for increasing insulator thicknesses. The exponential increase in resistance in both parallel and antiparallel magnetization states has been observed with an increase in the insulating layer thickness. The effect of increasing insulator thicknesses on the TMR rati...
With rapid advancements in the technology arena, novel design methodologies have been embraced an... more With rapid advancements in the technology arena, novel design methodologies have been embraced and to support these requirements, semiconductor process technology is also rapidly evolving. There is a need for efficient handshake between the foundry and design houses. PDKs play an important role in inheriting the foundry offering to aid in successful silicon realization. This paper presents an overview of process design kits and the importance of well-crafted kits in niche RF IC designs. The chip design ecosystem has been pictorially explained while emphasizing on the role of a foundry in the ecosystem. The different components of the process design kit have been discussed in brief. The method of qualification of process design kits and the various quality enhancement approaches to enable first pass silicon success have been presented in this paper. Towards the end of the paper, different substrate methodologies adopted by foundries for RF designs have been presented at a high level.
High gate leakage current, as a central problem, has decelerated the downscaling of minimum featu... more High gate leakage current, as a central problem, has decelerated the downscaling of minimum feature size of the field effect transistors In this paper, a combination of density functional theory and non equilibrium Green’s function formalism has been applied to the atomic scale calculation of the tunnel currents through CeO2, Y2O3, TiO2 and Al2O3 dielectrics in MOSFETs. The tunnel currents for different bias voltages applied to Si/Insulator/Si systems have been obtained along with tunnel conductance v/s bias voltage plots for each system. The results are in agreement to the use of high dielectric constant materials as gate dielectric so as to enable further downscaling of MOSFETs with reduced gate leakage currents thereby enabling ultra large scale integration. When used as dielectric, TiO2 exhibits extremely low tunnel currents followed by Y2O3 while CeO2 and Al2O3 exhibit high tunnel currents through them at certain bias voltages.
The effect of incorporating pairs of dopant atoms of opposite polarities into the nanowire lattic... more The effect of incorporating pairs of dopant atoms of opposite polarities into the nanowire lattice on the electrical behavior of nanowires has been presented in this paper. The dopants used are boron and phosphorus atoms. Intrinsic silicon nanowire is incapacitated with boron-phosphorus dopant atom pairs in a progressive manner, starting from one pair to nine dopant-atom pairs. The nanowire is simulated each time an additional dopant pair is introduced in the nanowire lattice to obtain current-voltage characteristics. These characteristics have been compared with that obtained by introducing similar dopants in an intrinsic germanium nanowire lattice. The power efficiencies of both intrinsic and doped silicon and germanium nanowires have been discussed towards the end of the paper.
This paper discusses the design of a 2.4 GHz operated, ultra-low power CMOS down-converting activ... more This paper discusses the design of a 2.4 GHz operated, ultra-low power CMOS down-converting active mixer based on double balanced Gilbert-cell resistor-loaded topology fabricated in standard 180 nm RF CMOS low-power technology. All the MOS transistors of the mixer core have ideally been biased to sub-threshold region. Consuming only 500 μW of DC power using 1.0 V supply and minimal LO power of −16 dBm, this mixer demonstrates a simulated power conversion gain of 17.2 dB with Double Side Band (DSB) noise figure of 13.3 dB. With the same DC power dissipation and LO power, −11.7 dBm IIP3 and −20.1 dBm 1-dB point have been obtained as discussed in the paper. Pre-layout and post layout simulation results match very well. The ultra-low power consumption of the proposed mixer due to subthreshold region of operation and lower local oscillator power are the advantages of this subthreshold mixer.
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Papers by Mayank Chakraverty