low power VLSI design

System on programmable chip for the performance estimation of loom machine, which calculates the efficiency and meter count for weaved cloth automatically. Also it calculates the efficiency of loom machine. Previously the same was done using manual process which was not efficient. This article is intended for loom machines which are not modern.

An extensive analysis of sub-10 nm logic building blocks utilizing ultra-compact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the workfunction in the contacts as well as two independent gates of an ambipolar Schottky-Barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to ×10) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop and 4T and-or-invert (AOI) gates are developed. Besides the logic verification using 7 nm devices, dynamic performance of the proposed logic circuits are also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.

Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.

According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of chip area will be occupied by the memory. Aggressive scaling in memory can occur in two manners. One is the cell miniaturization, which can be achieved by device modeling. Other being the peripherals and interconnect scaling. Device scaling to nanoscale regime brings many problems which are sensitive to process variation. To enable the advancement of Silicon based technology, necessary to increase computing power and the manufacture of more compact circuits, significant changes to the current planar transistor are a necessity. Novel transistor architectures and materials are currently being researched vigorously. The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. In VLSI technology conventional CMOS transistors are continuously scaling down to obtain faster speed of devices and very large scale integrated circuits. However the main drawbacks of CMOS scaling are high leakage current and heavy channel doping. So that using CMOS beyond 45 nm cell stability and controlled leakage current are becoming difficult in today's fast low power applications. Double gate FinFET may be an alternative of conventional CMOS transistor. DG FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology, because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabrication process. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous works have studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. In principal, FinFETs with tall fins (large Hfin) can provide higher drive currents and smaller Vth variations than those with short fins (small Hfin) because of their increased channel width. This paper elucidates the dependability analysis of Average power, Leakage power, Leakage current and Delay of double gate FinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence, showing that DG FinFET circuits have better dependability and scalability.

Emerging semiconductor VLSI requires improved device density on a single chip solution that many parameters are becoming vital concern for cost reduction by lowering the chip area, lowering power dissipation, reducing operating voltage, increasing speed etc. A previously designed precision sensor application mirror-amplifier was considered for optimizing in chip area consumption and improves sensing to make it ultra-precise, also this work has reduced the IC to a subcompact die sizes. MAGIC is used as two-dimensional CAD layout tool. Also PSPICE is used for electrical simulation purposes employed by extraction tool. Feature size is taken from mSCN3M_SUBM.30 process for 0.6µm layout and 0.5µm enhanced fabrication process. The improved design has area of 101λX48λ (minimized from 126λX59λ) or 30.3µmX15µm (minimized from 37.8µmX17.7µm) in 0.6µm CMOS design process. For multi-die placement, two sets of chip are designed those are placed on the four sub-dies in a single MOSIS tinychip die. For one set of chip coincidence detector is designed to make the mirror-amplifier ultra precise, buffer stage is designed for another set of chip to drive large load. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

— Fast low power SRAMs have become a critical component of many VLSI chips. This is especially true for microprocessors, where the on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and the main memory. Simultaneously, power dissipation has become an important consideration both due to the increased integration and operating speeds. Thus, a significant effort has been invested in reducing the power of CMOS RAM chips using circuit and architectural techniques. This paper presents a design using hierarchical divided bit-line approach for reducing active power in SRAMs by 40-50% and access time at the expense of 5-10% increase in the number of transistors when compared to Conventional SRAM. A Hierarchical divided bit line approach is chosen to implement a 1Kb SRAM memory on 0.18 micron CMOS technology using CADENCE design tool. Keywords— SRAM Cell, Power, Hierarchical divided bit line approach, bit-line capacitance.

As in today's date fuel consumption is important in everything from scooters to oil tankers, power consumption is a key parameter in most electronics applications. The most obvious applications for which power consumption is critical are battery-powered applications, such as home thermostats and security systems, in which the battery must last for years. Low power also leads to smaller power supplies, less expensive batteries, and enables products to be powered by signal lines (such as fire alarm wires) lowering the cost of the end-product. As a result, low power consumption has become a key parameter of microcontroller designs. The purpose of this paper is to summarize, mainly by way of examples,what in our experience are the most trustful approaches to lowpower design. In other words, our contribution should not be intended as an exhaustive survey of the existing literature on low-power esign; rather, we would like to provide insights a designer can rely upon when power consumption is a critical constraint.We will focus on the reduction of power consumption on different technologies for different values of oicapacitance and also compare power saving in technologies.

Minimization of power consumed by digital circuits is important for a wide variety of applications, both because of increasing levels of integration and the desire for portability. Standard cell based design approach is preferred over full custom design to achieve the short design time. One of the ways to minimize power consumed by a digital circuit is to organize sequence of its input vectors so that during transitions of input vectors, switching activity at the nodes of the circuit is minimized. We show that the problem of search of minimum power sequence of input vectors is equivalent to search for minimum weight Hamiltonian circuit in a completely connected graph, and is NP-complete. Hence, this power minimization approach is feasible for small circuits only, like standard cell based circuits. This paper proposes a heuristic to find the sequence of input vectors for standard cell based circuits such that the power dissipation is minimum. We consider layouts of small digital circuits with n inputs where 2 ? n ? 4. We use TSPICE simulations to measure switching power and total average power consumed in a circuit under consideration.

A common trend in digital communications has been
the increasing use of digital signal processing especially with
CMOS technology. The realization of multi-GSample/s (GS/s)
analog-to-digital converters (ADCs) draws a growing interest in
incorporating CMOS ADCs as the frontend of high-speed
serializers/deserializers (SerDes). Digital receiver frontends have
emerged as a possible solution for the next-generation serial I/O
receiver design in advanced CMOS technologies. Power
dissipation has become an important consideration both due to
the increased integration and operating speeds, as well as due to
the explosive growth of battery operated applications like mobile,
PDA’s and laptops etc. Today’s technology has been changing
rapidly to meet these requirements. This paper outlooks the
different design architectures used to address the above issues to
meet the wide spread requirements of high speed and low power
ADC based serial I/O receivers.

With the aggressive downscaling of process technologies and the importance of battery-powered systems, reducing leakage power consumption has become a crucial design challenge for IC designers. In addition, the traditional bulk CMOS technologies face significant challenges related to short-channel effects and process variations. FinFET devices have attracted a lot of attention as an alternative to bulk CMOS in sub-32nm technology nodes. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in near-and super-threshold (VT) operation regimes. The impacts of cell-level and transistor-level Gate-Length Biasing (GLB) on circuit speed and leakage power are studied using a 7nm FinFET technology.

This paper puts forward the design of a low power, high speed and energy efficient XOR gate comprising only 3 transistors in 45nm technology using the conception of Mixed Threshold Voltage (MVT) methodology. On comparison with the conventional CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL), the proposed design showed a substantial amount of depreciation in Average Power consumption (Pavg), Peak Power consumption (Ppeak), delay time, Power Delay Product (PDP) and Energy Delay Product (EDP), respectively. It has been found that Pavg is as small as 6.72×10−11 W while Ppeak is as small as 1.11×10−6 W. On further computation, it has been found that delay time is as low as 1.05pico second and hence PDP is as small as 7.07×10−23 Joule whereas EDP is as less as 7.45×10−35 Js for 0.9 volt power supply. In addition to this, due to reduced transistor count, surface area is also remarkably reduced. The simulation for the proposed design has been carried out in Tanner S PICE and the layout has been concocted in Microwind.

The diagnosis of lung cancer at an early stage is
important to cure and save lives. Prediction of lung
cancer is most challenging problem due to structure
of cancer cell.
Edge detection techniques are commonly used to
detect the affected cell region and make the
investigation easy. In this paper, the different edge
detecting techniques like sobel, Robert, prewitt, and
canny are used to detect the lung cancer affected
cells along with morphological operators. The
performance of the proposed method is analyzed and
the results are tabulated.

In the proposed system, 8 bit SAR ADC with input voltage of 0.9V has been designed. The schematic diagram of different sub blocks has been implemented in Tanner tools V16.0 using 180nm technology, also an improved low power Operational amplifier is proposed in design which utilizes 180nm technology with low voltage supply.

Satellite images are more frequently used nowadays and the resolution with which it is available to the user is limited. Hence it necessitates the need for robust resolution enhancement algorithm which works well for satellite images. The interpolation algorithms like nearest neighborhood, bilinear and bicubic algorithm works considerably well for natural images. But, there is a need for high level image enhancement algorithms which can work well for satellite images with more edges.
In this research work, an image resolution enhancement algorithm
based on evolved wavelet-filter coefficients is proposed for both satellite and medical images. The main focus of this research work lies in the optimization of wavelet filters based on parameters related to edges in the image. Initially all the input images are classified into various bins based on the edges present in the image and each bin of images will be enhanced by applying unique wavelet filters. These libraries of wavelet filters are evolved using bioinspired algorithm like genetic algorithm considering individual image bins. The individual image groups of satellite images are created based on the Spatial Frequency Mean (SFM) and wavelet filters are evolved for each group for both near edge and far edge image namely local and global DWT (CDF 9/7 type) filters. Two enhancement algorithms namely SDWT (Standard DWT) and EDWT (Evolved DWT) based on existing DWT-based methods are proposed to improve the resolution of the low-resolution satellite and medical images. The proposed algorithm enhances the resolution of the satellite image and it shows a significant improvement in the PSNR value of 0.5 dB compared with the existing techniques. The proposed algorithm is validated using 100 test satellite images. Also, the same hybrid algorithms are validated for medical images where it shows a significant improvement in PSNR and SSIM. The proposed algorithms for medical images show a maximum PSNR improvement of 4dB. Also, the proposed hybrid algorithm.

Power dissipation is one of the most important design objectives in integrated circuits, after speed. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers. This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. We present a modified carry select adder designed in different stages. Results obtained from modified carry select adders are better in area and power consumption.

Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different novel reversible circuit design style is compared with the existing ones. The relative results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present style in terms of number of gates, garbage outputs and constant input.

Basic concept of an Amplifier An amplifier is an electronics circuit that produces an output maybe current or voltage which is the magnified version of the input (current or voltage). A function, essentially a signal maybe too small to drive any load, overcome the noise levels and provide a well-defined logical level to a digital circuit or good strong power, current, or voltage value to an analog circuit. The input and output characteristics of an amplifier is generally a non-linear function that is approximated as,

Binary 128 arithmetic finds a hard in floating point
application of Quadruple Precision. The major component of 128 bit Fused Multiply Add (FMA) unit with multimode operations are Alignment Shifter, Normalization shifter, Dual Adder by CLA. The main contribution of this paper is to reduce the
latency. The technical challenges in existing FMA architectures
are latency and higher precision. The precision gets affected by
the repeated occurrence of fractional part. In order to reduce the latency the dual adder is designed by using compound Adder and
the latency of overall architecture gets reduced up to 30-40%. In
this paper the total delay of dual adder designed using compound adder is found to be 5.776 ns. Simultaneously to get higher precision we design namely Alignment Shifter and Normalization
Shifter in the FMA unit by using Barrel Shifter as this
Alignment Shifter and Normalization Shifter will have less
precision, but since replacement of these blocks by Barrel Shifter will result into higher precision.

Students play a very important role in the growth of any institute. Students and institutions have a tight relationship. Basically the rating or ranking of any institute fully depends upon the performance of its students.
Fostering conceptual and cognitive change in learners can be difficult. Students expect the things more and more in their favour or support from the institution and vice versa. Reputed institutions focus on the performance of students and try to do it better, so that they could stand in rank position as compared to the other institutions. Uncertain or soft knowledge domains can be represented with fuzzy logic. The dynamic nature of the FCM makes it a useful tool for discovering hidden relationships between concepts. Fuzzy cognitive maps (FCMs) and concept maps have similar applications in education. Variable input values can be entered into the nodes of the map and analysed via computer. Helping learners create metaknowledge may free paths to conceptual change. This paper proposes the use of fuzzy cognitive maps FCMs as a tool for creating metaknowledge and exploring hidden implications of a learner’s understanding.

This paper presents an efficient architecture for various image filtering algorithms and tumor characterization using Xilinx System Generator (XSG). This architecture offers an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explores important aspects concerned to hardware implementation. Performance of this architecture implemented in SPARTAN-3E Starter kit (XC3S500E-FG320

In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives-To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM)a parameter which gives detailed information about the cell stabilityin contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.

An Analog to Digital converter (ADC) is crucial component in video, radar, communications, high-speed data acquisition and measurement systems. ADC decides the overall accuracy of such systems. Many times the input to ADC in an application is different than standard signals such as sine wave or triangular wave. As ADC parameters are dependent on input frequency and other test conditions so parameters determined using standard signals are not useful. Therefore dynamic testing of ADC under application conditions is needed. This paper discuses methodology to test ADC using application input.

The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including ALU, microprocessors and DSP. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead scheme (CLA) to derive fast results but they lead to increase in area. Carry Select Adder is a compromise between RCA and CLA in term of area and delay. This paper focuses on the design analysis of carry select adder based on Multiplexer using Verilog. The delay (9.970ns) and power (34mW) is minimized. The proposed architecture of carry select adder is simulated in ModelSim6.5b and synthesized in Xilinx ISE14.7.

In this paper, we present analytical compact modelling approaches for the simulation of nanoscale MOSFETs in which transport is dominated by ballistic high electron mobility transistors. A numerical method for the resolution of the two and three dimensional Poisson-Schrödinger equation is proposed and applied to the simulation of double gate n-MOSFET. We have also evaluated the mobility versus drain current relation for linear and saturated nanoscale MOSFET to the near-equilibrium mobility of carriers in long-channel MOSFET. Here transistor implementation of double gate n-MOSFET is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm and 180 nm technology, some of the trade-offs are made in the design to improve the efficiency.

Electrical Engineering: An International Journal (EEIJ) is a Quarterly peer-reviewed and refered open access journal that publishes articles which contribute new results in all areas of Electrical Engineering. The journal is devoted to the publication of high quality papers on theoretical and practical aspects of Electrical Engineering.

— Today, all gadget and smart machine are become smaller and smarter because of it's an era of device miniaturization and smart performance. The only way to give a smart performance is to perform a two or more individual operations are done by one circuit. This document tells about an overview of the addition and subtraction operations can be combined into one circuit with one common binary adder by including a discrete gate with each full-adder and circuit can be performing. Index Terms—adder & full adder, subtractor and full subtractor, combine adder cum subtractor, result and discussion, conclusion, references.

The circuit topology we used for this project is a  cascode LNA with inductive  source degeneration by using 130nm CMOS technology. Specifications:
The designated Operating Frequency  : 0.8-1.0 GHz
GT:  > 15 dB
S11:  Less than -10 dB
S22:  Less than -10 dB
VDD:  1.1 ~ 1.3 V
IIP3 (input)  :  > -10 dBm
Noise Figure (50 ohms)  :  < 1.5 dB

The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for high-performance buses to communicate with low-power devices. In the AMBA Advanced High Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable RTL code of a complex interface bridge between AHB and APB is developed and known as AHB2APB Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality by writing a verification program using UVM in future.

In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”( Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows less computation and less complexity since it reduces the total number of partial products to half of it. This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design with new MGDI technique gives far better result in terms of area, switching delay and power dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result shows great improvement in terms of area, switching delay and power dissipation.

This paper is to design bandpass filter suitable with center at 2.5 GHz. This application is in the S band range at 2.5 GHz center frequency currently being used for Indian Regional Navigation Satellite System (IRNSS) receiver. The filter covers the centre frequency 2.5 GHz and the bandwidth is 80 MHz. This project was initiated with theoretical understanding of various types of filter and their applications. And suitable type was selected. It functions to pass through the desired frequencies within the range and block unwanted frequencies. In addition, filters are also needed to remove out harmonics that are present in the communication system. It was design and simulated using ADS (Advanced Design System) software Keywords-Bandpass Filter, Chebyshev, Fractional Bandwidth, Advanced Design System (ADS) ________________________________________________________________________________________________________ I. INRODUCTION Filter design depended on application requirnment. Application play very important role for filter design like which type of bandwidth require, ripple in passband, attenuation in stopband and center frequency. In this paper Filter is design for IRNSS application at 2.5GHz center frequency with 80MHz bandwidth with 0.1dB ripple level. Chebychev filter design type is used because it provide shaper cutoff in passbad.

In this era of nanometer semiconductor nodes, the transistor scaling and voltage scaling are not any longer in line with each other, leading to the failure of the Dennard scaling. Thus, it poses a severe design challenge. Reversible computing plays a vital role in applications like low power CMOS, nanotechnology, quantum computing, optical computing, digital signal processing, cryptography, computer graphics andmany more. The primary reasons for designing reversible logic are diminishing the quantum cost, profundity of the circuits and the garbage outputs. It is impossible to determine the quantum computing without implementing the reversible computation. This paper will represent the literature survey based on several papers on combinational circuits using reversible computing and also the future scope is to be discussed.

In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives-To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.

A CMOS Tapered buffer is used to increase the driving abillity of the logic circuitry whenever it is connected with large capacitive load.The increasing width of each inverter in the chain of CMOS inverters is based on tapering factor.The scaling or tapering factor of each stage is dependant on technology used, driving load and the number of stages used.

International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

In this paper, An ALU design and implementing using different foundries like 50nm, 70nm, 90nm and 120nm. The performance of developed ALU analyzing and comparing in terms of area and power. The schematic of ALU circuit designing using DSCH 3.5 and its equivalent layout creating using Microwind tool.

In many applications there is a growing demand for the development of low voltage and low power
circuits and systems. Low power consumption is of great interest because it increases the battery
lifetime. One of the main building blocks in many applications is the analogue-to-digital converter
(ADC) which serves as an interface between the analogue world and the digital processing unit. In all
these designs the comparator of the ADC, which is one the most power hungry blocks, is always on.
In order to reduce the power consumption of the ADC it is possible to turn the comparator off when
the decision is made and the comparator is not needed until the next clock cycle.
Especially, this work focuses on the reduction of the power dissipation, which is showing an everincreasing
growth with the scaling down of the technologies. Various techniques at the different
levels of the design process have been implemented to reduce the power dissipation at the circuit,
architectural and system level. Conventional Dynamic Comparator are designed and then compared
with the stack Dynamic Comparator using 180nm technology on workstation installed with Mentor
Graphics and pyxis software.