Low Power VLSI Design and Testing

System on programmable chip for the performance estimation of loom machine, which calculates the efficiency and meter count for weaved cloth automatically. Also it calculates the efficiency of loom machine. Previously the same was done using manual process which was not efficient. This article is intended for loom machines which are not modern.

According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of chip area will be occupied by the memory. Aggressive scaling in memory can occur in two manners. One is the cell miniaturization, which can be achieved by device modeling. Other being the peripherals and interconnect scaling. Device scaling to nanoscale regime brings many problems which are sensitive to process variation. To enable the advancement of Silicon based technology, necessary to increase computing power and the manufacture of more compact circuits, significant changes to the current planar transistor are a necessity. Novel transistor architectures and materials are currently being researched vigorously. The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. In VLSI technology conventional CMOS transistors are continuously scaling down to obtain faster speed of devices and very large scale integrated circuits. However the main drawbacks of CMOS scaling are high leakage current and heavy channel doping. So that using CMOS beyond 45 nm cell stability and controlled leakage current are becoming difficult in today's fast low power applications. Double gate FinFET may be an alternative of conventional CMOS transistor. DG FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology, because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabrication process. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous works have studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. In principal, FinFETs with tall fins (large Hfin) can provide higher drive currents and smaller Vth variations than those with short fins (small Hfin) because of their increased channel width. This paper elucidates the dependability analysis of Average power, Leakage power, Leakage current and Delay of double gate FinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence, showing that DG FinFET circuits have better dependability and scalability.
Hence due to the above factors, FinFET technology has proposed as an alternative to deep submicron bulk CMOS. FinFET is likely to meet the performance requirements in the sub-45 nm gate length regime. FinFET will replace the traditional MOSFET due to its better performance in sub 45 nm regime and also it has excellent control over the problems faced by the Traditional CMOS. FinFET is also suitable for future nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current.

This paper presents an efficient architecture for various image filtering algorithms and tumor characterization using Xilinx System Generator (XSG). This architecture offers an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explores important aspects concerned to hardware implementation. Performance of this architecture implemented in SPARTAN-3E Starter kit (XC3S500E-FG320

The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for high-performance buses to communicate with low-power devices. In the AMBA Advanced High Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable RTL code of a complex interface bridge between AHB and APB is developed and known as AHB2APB Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality by writing a verification program using UVM in future.

In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives-To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.

This paper presents a new power-efficient electrocardiogram acquisition system that uses a fully digital architecture to reduce the power consumption and chip area. The proposed architecture is compatible with digital CMOS technology and is capable of operating with a low supply voltage of 0.5 V. In this architecture, no analog block, e.g., low-noise amplifier (LNA), and filters, and no passive elements, such as ac coupling capacitors, are used. A moving average voltage-to time converter is used, which behaves instead of the LNA and Anti-aliasing filter. A digital feedback loop is employed to cancel the impact of the dc offset on the circuit, which eliminates the need for coupling capacitors. The circuit is implemented in 0.18-um CMOS process. The simulation results show that the front-end circuit consumes 274 nW of power. VLSI07_LP2 Title: Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Abstract: This paper proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be

2nd International Conference on VLSI & Embedded Systems (VLSIE 2021) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of VLSI and Embedded Systems. Original, unpublished papers, describing research in the general area of VLSI and Embedded Systems are solicited. Both theoretical and experimental research results are welcome in the following areas, but are not limited to.

In today’s VLSI field the exponentially increasing factor of integration takes the techniques of chip designing to be more cared about both switch level (eg. device, logic gate design, etc.) and chip level (eg. pad design, floorplanning, routing, etc.) as size of chip is continually decreasing and power consumption challenge is getting tougher. To design a complete & successful functional chip, pad frame design and floorplanning are also challenging. This study is an attempt to present a VLSI design of pad frame with less power consuming I/O architecture with an efficient way of floorplanning which includes block placement, global routing, detail routing. MAGIC is used as layout designing CAD tool to design the pad frame as it is the easiest and worldwide CAD tool for VLSI layout design, and for simulation purpose PSpice is used. This study presents details of the key research work, results, techniques and efficient way of pad frame design as well as floorplanning.

A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC) using a novel mirror telescopic operational amplifiers (opamp) with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved.

Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal's bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC) and Digital Down Conversion (DDC) are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock frequency. Both the designs have passed postroute delay based simulations, static performance checks, power domain checks and TSMC's 65nm design rule checks.

A significant portion of the total power consumption in high performance digital circuits in deep sub-micron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates.. All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

This paper presents the architecture and VHDL design of a Two Dimensional Discrete Cosine Transform (2D-DCT) with Quantization and zigzag arrangement. This architecture is used as the core and path in JPEG image compression hardware. The 2D-DCT calculation is made using the 2D-DCT Separability property, such that the whole architecture is divided into two 1D-DCT calculations by using a transpose buffer. Architecture for Quantization and zigzag process is also described in this paper. The quantization process is done using division operation. This design aimed to be implemented in Spartan-3E XC3S500 FPGA. The 2D-DCT architecture uses 1891 Slices, 51I/O pins, and 8 multipliers of one Xilinx Spartan-3E XC3S500E FPGA reaches an operating frequency of 101.35 MHz One input block with 8 x 8 elements of 8 bits each is processed in 6604 ns and pipeline latency is 140 clock cycles .

The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.

This paper determines the propagation delay and on chip power consumed by each basic and universal gates and basic arithmetic functions designed using existing reversible gates through VHDL. Hence a designer can choose the best reversible gates to use for any logic circuit design. The paper does a look up table analysis of truth tables of the reversible gates to find the occurrence of the AND OR, NAND, NOR and basic arithmetic functions, useful to build complex combinational digital logic circuits.

This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.

In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.

In today's advance electronic and communication systems the role of high accuracy analog to digital converters are of great importance. Nowadays, a larger percentage of mixed-signal applications requires for health care systems. Also the speed of the chosen ADC design matters a lot as we are connected with the real world signals. SAR based ADC will provides us a better solution for various analog to digital systems. It is an essential device whenever data from the analogue world, through sensors or transducers, should be digitally processed or when transmitting data between chips through either long-range wireless links or high-speed transmission between chips on the same printed circuit board. The paper projects up down and ring counter as a logic for Successive Approximation Register (SAR logic for a ADC that is one of the best suited for low power. Here the resolution is of 4-bit and a power consumption of few milli watts. SAR ADC is implemented in 45 nm nano-meter scaling technology CMOS technology with a power supply of 0.5V by maintaining 4:1 W/L ratio.

This paper describes the design of FPGA based signal processing card. An on board real time digital signal processing system is designed using FPGA. The platform can decode process of various kinds of digital and analog signals simultaneously. The design trend in this card is towards small size, high integration and fast real time processing. For the optimum performance a 16 bit 1 MSPS ADC is used which is interfaced with FPGA to make all the data processing onboard in real time. This card can be used in many signal processing based applications like audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications by interfacing several separate board using inbuilt I/O's, each with a number of input channels that will communicate with each other in real time over a high speed communication link. The resulting images can be displayed directly on LCD or OLED panel displays using I/O's peripherals. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing algorithms and high speed interconnection between the boards.

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix-2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC. KEYWORDS Radix-2 modified booth algorithm, Digital signal processing, spurious power suppression Technique, Verilog.

Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an optimized and dedicated hardware. The real time implementation places several constraints such as area occupied, power consumption , etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression sequence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.

A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a total power 1.96mW.

This paper determines the propagation delay and on chip power consumed by each basic and universal gates and basic arithmetic functions designed using existing reversible gates through VHDL. Hence a designer can choose the best reversible gates to use for any logic circuit design. The paper does a look up table analysis of truth tables of the reversible gates to find the occurrence of the AND OR, NAND, NOR and basic arithmetic functions, useful to build complex combinational digital logic circuits.

This paper presents a low hardware overhead test pattern generator (TPG) for scan-based
built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs)
during BIST. BIST is a device, here part of the functional device is self dedicated to selftesting
the correctness of the device. In general BIST is comprised of two TPGs: LT-RTPG
(Low Transition-Random Test Pattern Generator) and 3-Weight WRBIST (Weighted Random
Built In Self-Test). Minimization of hardware overhead is a major concern of BIST
implementation. In test-per-scan BIST, a new test pattern is applied to the inputs of the CUT
every m+1clock cycles, where m is the number of scan elements in the longest scan chain. By
using two proposed TPG increasing fault coverage is achieved through the reduction of
switching activity, thereby dissipation of power is minimized. Experimental results for
ISCAS’89 (International Symposium for Circuits and Systems) benchmark circuits show that
the proposed BIST can significantly reduce switching activity during BIST while achieving
maximum fault coverage for all ISCAS’89 benchmark circuits. In large circuit, greater
reduction in switching activity is achieved. The proposed BIST can be implemented with low
area overhead; as seen through experimental results.

Internet-of-things enabled applications are increasingly popular and are expected to spread even more in the next few years. Energy efficiency is fundamental to support the widespread use of such systems. This paper presents a practical framework for the development and the evaluation of low-power Wireless Sensor Networks equipped with energy harvesting, aiming at energy-autonomous applications. An experimental case study demonstrates the capabilities of the solution.

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272µW in 0.35µm technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542µW. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35µm CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit's shows better performance in terms of power consumption and transistor count.

Addition is a fundamental arithmetic operation and is the base for arithmetic operations such as multiplication and the basic adder cell can be modified to function as sub-tractor by adding another EX-OR gate and can be used for division. Each and every logic has its own advantages and disadvantages. If we combine all these logics than (Hybrid) then, how the circuit will work, then how much amount of PDP will be reducible is observed. Here The Analysis of 1-bit full adder using Hybrid design and with GDI technology using Tanner EDA tools , simulation of output Waveforms comparison of power, delay, Power Delay Product(PDP) are observed both theoretically and practically.

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272µW in 0.35µm technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542µW. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35µm CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit's shows better performance in terms of power consumption and transistor count.

Page 1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011 DOI : 10.5121/vlsic.2011.2405 47 Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate ...

This paper presents a flexible standalone, low cost smart home system, which is based on the Android app communicating with the micro-web server providing more than the switching functionalities. The Arduino Ethernet is used to eliminate the use of a personal computer (PC) keeping the cost of the overall system to a minimum while voice activation is incorporated for switching functionalities. Devices such as light switches, power plugs, temperature sensors, humidity sensors, current sensors, intrusion detection sensors, smoke/gas sensors and sirens have been integrated in the system to demonstrate the feasibility and effectiveness of the proposed smart home system. The smart home app is tested and it is able successfully perform the smart home operations such as switching functionalities, automatic environmental control and intrusion detection, in the later case where an email is generated and the siren goes on.

A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre KEYWORDS Phase locked loop (PLL), Delayed flip-flop (D-ff), Phase frequency detector (PFD),True signal phase clock (TSPC), Voltage controlled oscillator (VCO), Charge pump (CP), Divider (Div), Low pass filter (LPF).

Resonant tunneling diodes (RTDs) have functional versatility and high speed switching capability. The integration of resonant tunneling diodes and MOS transistor makes threshold gates and logics. The design and fabrication of linear threshold gates will be presented based on a monostable bistable transition logic element. Each of its input terminals consist out of a resonant tunnelling diode merged with a transistor device. The circuit models of RTD and MOSFET are simulated in HSPICE. Two input XOR gate is designed and tested.

Code division multiple access (CDMA) is used in various radio communication techniques due to its advantages. In CDMA one of the most important processes is multi user detection (MUD). There are numerous methods for MUD in CDMA, but in most of the methods, they identify the exact user but the interference signal is high. One of the methods used for MUD in CDM A is elliptic curve cryptography (ECC). Normally, the multi user detector in CDMA using elliptic curve cryptography is performed by using one prime field. In ECC method the exact user is identified and also interference signal reduces comparing with other techniques. To reduce the interference signal to very low, here propose a new technique for MUD in CDMA using ECC. The proposed technique uses multiple prime numbers for key generation. By generating key using different prime numbers using ECC, the bit error rate was very low. The results shows the performance of the proposed for reduce in bit error rate for MUD in CDMA.

Device density in VLSI today enforces the process of chip designing much more complex; whereas MAGIC CAD tools made the IC design in this work, comparatively easier. Study on various amplifiers for sensor applications showed that their powers ranged from a few milliamperes to a few hundred milliamperes at the submicron fabrication processes by MOSIS, but within the affordable cost. Objectives of lowering the power at least by 1000 times in those fabrication processes engaged this research towards completing a new design, called the mirror-amplifier. This design is verified for precise functional behavior for the sensor and total power consumption, using MAGIC extractor and PSPICE electrical simulation tools. A compact model chip layout made silicon area more efficient for MOSIS tiny-chip fabrication in 0.6µm processes. To make even more economical, a multi-die placement technique was applied to the chip layout for this tiny-chip in silicon area of 1500µmX1500µm. MOSIS design rules for multi-die fabrication was verified for process scribe-lines and die packaging. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.

This paper puts forward different low power adder cells using different XOR gate architectures. Adder plays an important role in arithmetic operation such as addition, subtraction, multiplication, division etc. The optimization and characterization of such low power adder designs will aid in comparison and choice of adder modules in system design. A comparative analysis is performed for the power, delay, and power delay product (PDP) optimization characteristic& deals with the design of five adder cells using transistors and schematic structure using CADENCE tool. 10 transistor adder circuits shows the least power consumption with others. Simulations are performed by using Cadence Design tools using 45nm CMOS technology. The four adder cell module proposed here demonstrates their advantages in comparison with Static Energy Recovery Full (SERF), including lower power consumption, smaller area, and higher speed at different frequencies. Keywords Low power, Static Energy Recovery Full Adder (SERF), 45 nm technology, power delay product (PDP).

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the downscaling of the gate oxide thickness due to higher gate leakage current and gate capacitance.