Digital Circuit Synthesis

Digital synthesis tools such as logic synthesis and semicustom layout have dramatically changed both the frontend (specification to netlist) and backend (netlist to mask) steps of the digital IC de- sign process. In this tutorial, we look at the last decade's worth of progress on analog circuit synthesis and layout tools. We focus on the frontend and backend of analog

Independent control of front and back gate in double gate (DG) devices can be used to merge parallel transistors in noncritical paths. This reduces the effective switching capacitance and, hence, the dynamic power dissipation of a circuit. However, efficient design of large-scale circuits with DG devices is not well explored due to lack of proper modeling and large-scale design simulation tools. In this paper, we propose several low-power circuit options using independent gate FinFETs. We developed semianalytical models for different FinFET logic gates to predict their performance. An efficient circuit synthesis methodology comprised of proposed low-power logic options in FinFET design library has been developed. Results show about 8.5% area savings and 18% power savings over conventional FinFET technology for ISCAS85 benchmark circuits in 45-nm technology with no performance penalty.

In this paper we present a new hybrid transform based on the Kronecker product of Reed-Muller and Reed-Muller Haar transforms. The proposed transform shares attractive properties of both Reed-Muller transform and Reed-Muller Haar transform. An example of application of ...

We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis problem. We have implemented this strategy in a pair of tools called ASTRX and OBLX. To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTRX/OBLX has resynthesized circuits in an afternoon that, for some prior approaches, had required months. To show the viability of the approach on difficult circuits, we have resynthesized a recently published (and patented), high-performance operational amplifier; ASTRX/OBLX achieved performance comparable to the expert manual design. And finally, to test the limits of the approach on industrial-sized problems, we have synthesized the component cells of a pipelined A/D converter; ASTRX/OBLX successfully generated cells 2-3× more complex than those published previously

The task of this report is to present the proposed re- search program, and to review the literature describing the main characteristics of quantum computing, genetic algorithms and cir- cuit synthesis. We also present selected parts from a submitted ar- ticle, which proposes a solution for quantum circuit synthesis using genetic algorithms. Our goal is to perform automatic quantum cir- cuit synthesis for a given functional description using rippled steps. We propose and will pursue the usage of a parser which will create an internal data structure for the provided description. Also, we employ simulation in order to determine the flnal quantum state, and we encourage the usage of an optimizer that will allow a better handling of data, and in the last step foster the usage of genetic algorithms in order to perform the synthesis tasks.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 ... Application to the ARM 1136JF-S Microprocessor ... Aurangzeb Khan, Senior Member, IEEE, Philip Watson, George Kuo, Due Le, Trung Nguyen, Steven Yang, Peter Bennett, Pokai Huang, ...

Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few years has slowed considerably (with some notable exceptions). It seems natural to then question whether the current logic-synthesis and technology-mapping algorithms for FPGA designs are producing near-optimal solutions. Although there are many empirical studies that compare different FPGA synthesis/mapping algorithms, little is known about how far these algorithms are from the optimal (recall that both logic-optimization and technology-mapping problems are NP-hard, if we consider area optimization in addition to delay/depth optimization). In this paper, we present a novel method for constructing arbitrarily large circuits that have known optimal solutions after technology mapping. Using these circuits and their derivatives (called Logic synthesis Examples with Known Optimal (LEKO) and Logic synthesis Examples with Known Upper bounds (LEKU), respectively), we show that although leading FPGA technology-mapping algorithms can produce close to optimal solutions, the results from the entire logic-synthesis flow (logicoptimization+mapping) are far from optimal. The LEKU circuits were constructed to show where the logic synthesis flow can be improved, while the LEKO circuits specifically deal with the performance of the technology mapping. The best industrial and academic FPGA synthesis flows are around 70 times larger in terms of area on average and, in some cases, as much as 500 times larger on LEKU examples. These results clearly indicate that there is much room for further research and improvement in FPGA synthesis

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 ... Application to the ARM 1136JF-S Microprocessor ... Aurangzeb Khan, Senior Member, IEEE, Philip Watson, George Kuo, Due Le, Trung Nguyen, Steven Yang, Peter Bennett, Pokai Huang, ...

This paper presents an extension of the AAA rapid prototyping methodology for the optimized implementation of real-time applications onto reconfigurable circuits. This extension is based on an unified model of factorized data dependence graphs as well to specify the application algorihtm, as to deduce the possible implementations onto reconfigurable hardware. This is formalized in terms of graphs transformations. This seamless transformation flow has been implemented in a CAD software tool called SynDEx-IC.