IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 1, FEBRUARY 1999 3 Design Methodologies Based on Hardware Description Languages Teresa Riesgo, Member, IEEE, Yago Torroja, and Eduardo de la Torre Abstract—In this paper, we are presenting the basic methodology to be used in the design of a digital system, based on the use of hardware description languages. The most important stages of the design flow and the computer-aided design tools involved are presented, from the initial specification to the final implementation. The design flow described in the paper is based on a top-down approach, as this is the methodology currently used for most of the digital systems to face the current system complexity. Although all the concepts and methods are feasible for any kind of digital electronic system, application-specific integrated circuits are, in particular, considered as an application example in the paper. Most of the examples shown are written in VHSIC HDL, as it is an IEEE Standard and is one of the most commonly used. Index Terms—Circuit simulation, circuit synthesis, design automation, design methodology, digital systems, hardware design languages. I. INTRODUCTION T HE complexity of electronic systems is constantly growing. This is well known by both designers and users. Some facts have been of great importance in allowing this growth: the improvement of the manufacturing processes, the diversity of applications, and the quantity of elements in the market being some of the crucial points. However, this development could not have been possible if the design processes and computer-aided design (CAD) tools had not developed, as well. Besides the systems’ complexity, the market has evolved with very rapid changes, where quality and cost are as important as the time to market of the electronic equipment. The result is that development times and costs are decreasing, while design complexities are increasing. With these factors in mind, a lot of effort has been and is being made to improve what are usually called design methodologies. A design methodology defines a set of procedures, rules, and tools to optimize the electronic system’s design. The optimization criteria could come from different sources, depending on the system nature, application, and complexity. The following are some of the most important factors: • development time and effort; • final product cost; • reusability of the design; Manuscript received January 10, 1997; revised October 1, 1998. Abstract published on the Internet October 26, 1998. The authors are with the División de Ingenierá Electrónica, E.T.S. Ingenieros Industriales, Universidad Politécnica de Madrid, 28006 Madrid, Spain. Publisher Item Identifier S 0278-0046(99)00479-7. • customer and quality control during the whole design cycle; • first-attempt success guarantee. To make the design of complex systems manageable, the design team has to be coordinated throughout the whole development period. This is not an easy task, when arranging different departments and people with diverse skills (from the systems engineer, through the components designer, to the test team). Communication among them should be made using a common format or language, which makes possible understanding. Hardware description languages (HDL’s) have come to solve some of the problems previously posed. Some of the previewed advantages are as follows. • HDL’s allow shorter development phases in the projects. • HDL’s provide continuous checking and verification of the system performance and behavior. • HDL’s make the system independent of the target technology and the final implementation details, in the early stages of the project. • HDL’s are a common language throughout most design phases, so CAD tools and users benefit from it. • HDL’s supply a common interface between different people involved in the project and between designers and CAD tools. Some other advantages of using HDL’s will be pointed out later in this paper and will be summarized in the conclusions. An important step ahead in the design methodologies based on HDL’s is the acceptance of a standard language by the IEEE. This language is VHSIC HDL (VHDL), balloted as standard for the first time in 1987 [1], and reballoted in 1993. The existence of a standard has spread the use of the language because its use is accepted by different designers (systems, application-specific integrated circuits (ASIC’s), test, etc.) and several CAD tools from different vendors. Other languages, such as Verilog, are also widely used for hardware design [2]. In the case of ASIC’s, HDL’s have been widely used in recent years (actually, from the moment VHDL was standardized), and the growth of ASIC’s designers using HDL’s is foreseen to be constant [3]. With everything expressed above, this paper will go into detail in some special stages of the design process, taking into account the needs of the electronic designers and the availability of tools that permit the automation of some designrelated tasks. In the next section, the abstraction levels in the different design phases and the use of HDL’s are explained. In 0278–0046/99$10.00  1999 IEEE 4 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 1, FEBRUARY 1999 Fig. 2. Different domain representations of the same component. Fig. 1. Graphical representation of the abstraction levels and description styles. the following sections, the main tools and related advantages are shown, detailing some crucial aspects, such as specification, documentation, simulation, synthesis, and test, and how they are accomplished when using HDL’s. Finally, some conclusions and a preview of the future trends are presented. II. ABSTRACTION LEVELS AND HDL’S The first approach in reducing the number of objects or components to deal with for a given electronic system is considering it from a higher level of abstraction. For example, digital circuits have been typically considered at the logic gate level and not at the electrical level. This reduces the amount of data the designer has to deal with, by a factor of about four, in terms of number of elements, number of connections, etc. When the electronic system has a large number of gates, it should be considered at an abstraction level higher than logic gates. Fig. 1 shows a graphical representation of the different levels of abstraction [4]. The diagram (usually called the Ychart) grows in abstraction level with the distance to the center and shows different representations for each domain at each abstraction level. In this diagram, four levels are considered, although a mixed approach could also be possible. The lowest level (circuit level) considers electrical information of the system, having the maximum accuracy in the model. The next level is the logic level, which considers logic states as possible values in the signals, and some timing information (delays, setup times, etc.) is also present. At the register transfer level (RTL), data transfers and control cycles are identified in the description, working with primitive elements like adders, multiplexers, etc. At the system level, no schedule is defined for the operations and no clocking scheme is specified either. Apart from the abstraction levels, three domains can be identified to represent electronic systems, that are represented in the axes of the Y-graph: behavioral domain, where the design functionality is defined (what the system does); structural domain, where designs are defined as a set of components and interconnections (what components the system has); and physical domain, where size, technologies and implementations are considered (how the system is made). Fig. 2 shows three different representations for an inverter, as an example. The main advantage of working at higher levels of abstraction is the reduction of the number of elements the designer has to consider. Moreover, high-level descriptions in the behavioral domain imply the possibility of modeling the system behavior, regardless of the final structure, target technology, and implementation details. HDL’s, and VHDL, in particular, make it possible to describe the digital systems at any abstraction level, using behavioral or structural information. An example for a multiplexer block is shown in the VHDL code of Table I. As shown in the code, the structural description is defined as an interconnection (netlist) of previously defined components stored in a library, while the behavioral description does not give information about the system structure, and only describes its behavior. For this simple example, it can be noticed that behavioral descriptions are closer to the function of the system, while the structural one considers implementation details. It is also important to notice that the complexity associated with the behavioral description is much lower than the structural one, both describing the same element. The transformation of a high abstraction level description into another with lower abstraction level is called synthesis. The transformation from a behavioral description into another in the structural domain within the same abstraction level is sometimes called synthesis, although, if a particular library or technology is considered in this step, it can be called mapping. The transformations made within a domain and an abstraction level to improve the system performances can be called optimization or refinement [5], [6]. III. DESIGN FLOW IN TOP-DOWN METHODOLOGIES Design methodologies can be classified in two groups. • Bottom-up is when the designer builds the system from elementary components, such as logic gates or transistors. This approach needs a previous phase in which the system has to be partitioned into smaller blocks. • Top-down is when the designer builds the system from its functional specification through a synthesis process to the final implementation details. The first approach may be considered as the traditional design method, and it is mainly based on schematic capture and simulation. The top-down approach is the method used in conjunction with HDL’s, and it is based on code generation, simulation, and synthesis. RIESGO et al.: DESIGN METHODOLOGIES BASED ON HDL’S 5 TABLE I VHDL CODE OF A MULTIPLEXER ‘ ’ Fig. 3. Bottom-up versus top-down methodologies. Fig. 3 shows both flow diagrams of the design processes, detailing the steps to be taken and the CAD tools to be used. Top-down approaches are best suited for the use of HDLbased design methodologies, and their widespread use has been possible because of the use of CAD tools related to synthesis and simulation, which will be detailed later on this paper. The design methodology described in this paper is based on a topdown approach, where different abstraction levels are implied along the design process [7]–[9]. One of the main advantages of using top-down methodologies in conjunction with HDL’s is the fact that the whole design process can be made within a common format. On one hand, the HDL description can be simulated using a set of input stimuli described by the designer. This can be considered as an abstract model of the electronic system. On the other hand, this HDL description can also be synthesised to a particular technology, obtaining the electronic system after a set of steps (physical design, manufacturing, etc.). This will be the hardware model and the stimuli used to verify the functionality of the abstract model can be reused here to check the system functionality for the final implementation. The great advantage of the method is that there exists the possibility of dealing with abstract and hardware models within the same design environment, as shown in Fig. 4. 6 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 1, FEBRUARY 1999 be the case of a system implemented in a printed circuit board (PCB) that can be integrated using an ASIC or a programmable device, like a field-programmable gate array (FPGA). The reusability issues will be detailed in Section VIII. All these features are key points for the success of a project and the price to pay in terms of human effort in writing the specification and the documentation using the HDL can be easily amortized, particularly for developments implying different institutions. V. SIMULATION Fig. 4. A common environment for abstract and hardware models. In the following three sections, the key topics mentioned in the top-down methodology are explained in detail: specification through HDL coding, simulation, and synthesis. Later on, two more topics will be discussed: test and design with macrocell blocks. IV. SPECIFICATION AND DOCUMENTATION The first stage of a project is the specification phase. In this phase, all functional features of the system have to be clearly defined before the design starts. Practice shows that most of the problems during the design phase come from inconsistencies and vagueness in the specification. This problem is even worse when the system definition and the design are made by different departments or different centers. In this case, an additional problem is the interchange format and the different points of view of the people involved in the project. HDl’s provide solutions for these problems. • Specifications can be written at a system level, using the HDL, with the advantage that this description can be simulated to check its correctness and completeness. In this way, the functional test vectors used for checking the specifications may be used along the whole process at all abstraction levels. This continuous checking can detect design failures and errors in the early stages of the design, where the correction and remaking is not yet an “expensive” task. • HDL’s provide a common interface between system developers and designers which allows a formal way of interchanging information at all levels. In this way, the step from the specification phase to the design is made using a description which is easily and precisely understood by all members of the design team. • Besides the specification phase, the use of the HDL may help in the final documentation of the system. The specification and the final simulation results may help a lot when writing the documentation of the system. Moreover, if the system is intended to be implemented in another technology or reused in another system, the starting HDL description may be used as input for the new system design. This is quite important, for example, in long-life systems that have to be updated periodically, for performance improvements. Another example could Using a simulation tool, it is possible to know the response of a system, given a set of input stimuli. In this way, it is possible to preview the system performance before it is manufactured. Simulators are very useful in the design of systems based on components, when previous prototypes can be built to estimate the system performance and to debug the design. However, simulators are essential in the design of integrated circuits (ASIC’s, mainly) because it is not possible to manufacture a prototype to check its performance. In this case, the circuit has to be simulated with a large set of sequences to check its functionality before the first prototypes are manufactured. The prototype fabrication implies mask fabrication and a complex manufacturing process, and the “trial-and-error” method cannot be used. HDL’s and, in particular, VHDL, were initially made for simulation purposes. A key advantage of HDL use is that it can be simulated with the same tool at any abstraction level and with any description style. Of course, a mixed description, with some parts defined by its behavior and others by its structure, can also be simulated. The main differences in the simulation, regarding the abstraction level of the input description, are the following. • One is simulator performance, or the time required for simulating a given model. The higher abstraction level considered, the better performance is obtained. The main reason is that the number of objects the simulator has to consider is lower as the abstraction level is increased. Besides, higher abstraction levels imply the use of algorithms in the description which are easier to simulate in computers. There are some VHDL simulators that can run in hardware accelerators to improve the simulator performance. • Another is result accuracy, or the resemblance between the simulated results and the real response. This is also directly related to the abstraction level of the input description. The higher the abstraction level considered, the lower accuracy in the results. For example, if a logic level is used, the results will contain information about the signal timings and delays, while, if an algorithmic level is considered, no timing information will be available in the results and even the system clock may not be included in the design. Fig. 5 shows these concepts in a graphical way, for different abstraction levels. RIESGO et al.: DESIGN METHODOLOGIES BASED ON HDL’S 7 Fig. 5. Simulator performance versus results accuracy. Fig. 6. Simulation of a VHDL description. The input stimuli to the HDL description may be written in the same language, which makes the simulation file independent of the tool that is being used. Besides, the language has capabilities to describe high-level functions and algorithms, which allow an easy way to specify the input waveforms. This input file is usually called testbench and can be used for all the descriptions (architectures) of the same device. HDL simulation has to be clearly defined to ensure the correct semantics of the model, as well as the treatment of time, that is one of the most important differentiating features among different simulators. Electrical or analog simulators usually have a continuous-time model, while digital simulators use a discrete-timing model, which assumes that time advances in discrete units. Among the digital simulators there may be two approaches, time-driven simulators which calculate the state of the circuit at every time step and event-driven simulators which only calculate the state of the circuit when any change occurs. This last approach seems to be more efficient when dealing with large digital systems, as only a few time units are considered and a large amount of CPU time may be saved. A VHDL simulator is a discrete event-driven simulator based on concurrent execution of sequential processes. The detailed description of the simulation cycle may be found in [10]. VHDL is not well suited for modeling or describing analog functions, where continuous time is required. An extension to VHDL language has been developed to support mixed analog–digital modeling and simulation (VHDL-AMS) [11], [12]. Before the VHDL description is simulated, it has to be processed by a sequence of steps, as shown in Fig. 6; these steps are not usually seen by the user. The VHDL analyzer checks the source code syntax and generates a design library, establishing the links between signals, components, and all the required functions through the circuit hierarchy. The second step elaborates this library data base, generating a set of sequential processes interconnected by signals that can be translated by the simulator to an executable code in the processor. This scheme allows that concurrent models can be executed in sequential processors. The communication among processes is managed by a kernel process that calculates the events and the time advance. The simulator is the most important tool through all of the design process. It is used in all the design stages, at different abstraction levels. To sum up, the VHDL simulator will be used in the following stages of the design. 1) The specifications may be simulated using the language at the system level, in conjunction with the input stimuli to check the system function. When this starting description agrees with the system requirements, the specification description and the simulation results will be used as input for the next stage. The input stimuli that prove the functionality of the system may be used for the following stages. 2) The total system has to be partitioned for the next step. For each block, the description will be refined into a lower abstraction level, converting data types and control structures to something closer to hardware structures. The goal will be to obtain a model at the RTL that has to be checked against the input stimuli used for the specification files. Therefore, this RTL model will be simulated to check the correctness of its functionality, including additional information such as synchronization schemes and length of the operations in terms of number of clock cycles. 3) The RTL model is very close to hardware structures and can be easily translated to a logic gate structure based on a particular module library. This step will be explained in the next section. The resulting description will be a netlist (connection of logic gates and modules) and its simulation results will contain technology-dependent information like signal propagation delays, critical paths, etc. After this step, the system may be built as a set of discrete components of a PCB, an ASIC, a combination of both, etc. The method changes depending on the final implementation. 4) If the system will be an ASIC, the physical design will be performed at this moment. From the final layout of the circuit, the parasitic capacitances and resistances will be extracted. The computed parasitic effects will determine the real delays of the final chip. These delays should be back annotated to the structural description and the resulting model simulated with the physical 8 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 1, FEBRUARY 1999 VHDL CODE TABLE II MULTIPLIER EXAMPLE FOR THE ‘ ’ ‘ ’ “ ” ‘ ’ ‘ ’ ‘ ’ ‘ ’ ‘ ’ ‘ ’ ‘ ’ ’ ‘ ’ ‘ ’ ‘ ’ ‘ ’ ‘ ’ ‘ ’ ‘ ’ ‘ ’ information. This will be the final check before the prototype manufacturing. For these purposes, VHDL Initiative Toward ASIC Libraries (VITAL ) is a VHDLrelated standard which supports the delay modeling for back-annotated simulations. It also defines a way to accelerate logic level simulations, which are very slow in a standard VHDL simulator [13]. After describing the simulator functions, let us introduce another important tool of the design process, which is synthesis. VI. SYNTHESIS As it has been already explained, synthesis is the transformation of a description of a high abstraction level into another with lower abstraction level. Depending on the level of the starting description, two different kinds of synthesis can be considered. • One is behavioral synthesis, which translates an algorithmic description into a RTL model. • The other is RTL synthesis, which translates a register transfer description into a logic level model. The main differences between algorithmic and register transfer descriptions will be explained using an example. The VHDL codes in Table II show the entity of a multiplier that will be first described by terms of an algorithm (see architecture ALGORITHM) and by a high-level synthesis transformation, will be translated into an RTL description (see architecture RTL). The main difference between both descriptions is the specification of the clocking scheme, which is not RIESGO et al.: DESIGN METHODOLOGIES BASED ON HDL’S 9 Fig. 7. Schematic of the multiplier example. determined in the algorithmic description. Besides, in the RTL architecture, the registers are identified. In the second refinement process, called RTL synthesis, the RTL description is translated into a set of interconnected logic gates. This description contains information about the signal delays and the particular timing problems that may appear in the circuit. RTL synthesis usually works in two steps. In the first one, the synthesizer translates the register transfer description to a set of generic modules, like multiplexers, adders, comparators, etc. This step is called synthesis itself. The second step is more related to technology mapping and Boolean optimization. In this step, the circuit logic is mapped to a particular set of logic gates included in a library (discrete component library, such as 74XX or an ASIC library), and a further optimization is applied. The user has some control in the synthesis to choose the optimization preferences in terms of signal propagation time or hardware requirements. For the example shown above, after synthesis and optimization, the schematic obtained with a synthesizer is shown in Fig. 7. The propagation time from input to output is 11 ns and the total area is 323 equivalent gates (the circuit has been mapped in gate array library of MHS). The schematic description may also be expressed using the same HDL (VHDL, in this case) and simulated in the same tool and with the same stimuli used in previous design stages. RTL synthesis tools have been available for some years, and several CAD vendors offer these products for synthesizing from different HDL’s, like VHDL or Verilog. From the practical point of view, in most of the cases, the specification description is directly refined to a register transfer description and the RTL synthesis tool is used for generating the schematic. Synthesis tools have some limitations in the kind of HDL code they accept, derived from the abstraction level they consider. For example, in RTL synthesis tools, the clock and reset signals must be clearly identified in the description. In the same way, data types are constrained and real types are not allowed. Combinational and sequential parts have to be clearly identified in the code. A performance comparison among different RTL synthesis tools can be found in [14]. Another important issue is the dependency of the code style with the results. If the HDL code is not written according to the “synthesizer point of view,” the results in terms of hardware resources and timing of the final circuit may not be very good. The synthesizer, for example, expects the designer to take care of the possibility of inferring latches in combinational designs, as shown in the example of Fig. 8. This example corresponds to an AND2 gate description or to a latch, if the second part of the if statement is missed. Some drawbacks of automatic synthesis methods should be detailed at this point to evaluate when we should use automatic synthesis tools and when manual synthesis is preferred. • The designer loses the knowledge of the particular structure that is being implemented in the circuit. If some structural changes are required in the synthesis output (schematic) they are very difficult to include and the resulting schematics are very difficult to debug, as can be seen in Fig. 7. In most cases, at regular operation frequencies and with normal hardware constraints, this is not required. Another problem is posed in the case of ASIC’s when the test has to be generated for an automatically synthesized structure. This point will be explained in more detail in the next section. • The quality of the final design may be poorer, as a result of the automatic synthesis. This is paid off by the design time that is saved by using the tool. Besides, the changes in the behavioral descriptions to improve the results are easier to introduce than in a structural model, even if it has been manually synthesized. When designs are very critical in area or time, some blocks should be manually synthesized. 10 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 1, FEBRUARY 1999 Fig. 8. Latch inference in VHDL synthesis. • Sometimes, hardware designers are not as comfortable when writing software code as when drawing schematics. This will imply some changes in the hardware engineer’s mentality. Practical experience shows that deep knowledge of HDL’s is not required to design circuits with this methodology. Moreover, when some trials are made using the automatic synthesis tool, most designers move to it. VII. TEST The next step after the system design is the specification of the test procedures which will be used to verify its performance and functionality, once the system is manufactured. The more complex the system is, the more difficult the generation of the test procedures is. For most electronic systems, when complexity grows, the observability and controllability of signals decreases, because, generally speaking, internal complexity is increased but the number of access points (primary inputs and outputs) is not increased by the same factor. The testability problem is even greater when talking about integrated circuits (where no internal net can be directly accessed), but is also important for multilayer PCB’s, surface mounted boards, or multichip modules (MCM’s). The result is that some special strategies have to be applied to increase the testability of the internal signals [15]. These strategies are based on adding extra hardware, inputs, and outputs to give access to the internal system. These techniques are usually called design for testability (DFT) [16]. Some other approaches to help in the test-generation task are based on test synthesis. These tools work in parallel with RTL synthesis tools and generate the required logic for making an easily testable circuit. In summary, they include scan logic to break the sequential paths in test mode of operation and generate the test vectors for the synthesized circuit. Among DFT techniques, boundary scan is specially important for testing complex PCB’s or chips in the final system. boundary scan test, also called JTAG, uses a serial path to interconnect all the inputs and outputs of a given PCB. In this way, test vectors are applied from a serial input and the results read from a serial output. Test procedures are internally controlled by a finite-state machine (test access port controller) and externally by a set of additional control inputs (test mode Fig. 9. Boundary scan interconnections. select, test clock, and test reset). All of these protocols and procedures are defined and accepted as standard by the IEEE [17]. Some commercial devices have a JTAG option that may be optionally included in the circuit. Fig. 9 shows the schematic diagram of a PCB with boundary scan test. Another important application of boundary scan test is its use as a mechanism to integrate test vectors in those circuits based on macrocells or existing components [18]. At this level, each macrocell should have the corresponding logic and the scan chain would be internal to the circuit. Testing is one of the bottlenecks in the design flow presented in this paper. The main problem is derived from the fact that current test tools work at the structural level and the designer, when automatic synthesis is used, has partially lost the final structure of the circuit. Therefore, a new test strategy has to be defined to accomplish the design flow based in HDL’s. Some work has been developed to take advantage of the presynthesis descriptions, in order to have additional information of the system behavior to make the test generation easier and closer to the design methodology [19]. These techniques are usually called high-level testing techniques, as they consider high-level descriptions for performing test generation. Some results show that it is possible to estimate the fault coverage achieved with a set of test vectors before the synthesis is made [20]. In this way, the designer may have information on the test quality at the early stages of the design process. Of course, this is an emerging technique that needs more development to have new test tools as VHDL fault simulators. VIII. DESIGN BASED ON MACROCELLS REUSABLE DESIGN Another important issue in reducing the design time in integrated systems is the reusability of already existing cells. The method is based on the use of cells designed for other applications or with a more general scope. This philosophy is very well suited for current complexities that do not permit the design “from scratch.” Two different perspectives can be viewed from this approach: • the design of reusable modules, that can fit different applications; RIESGO et al.: DESIGN METHODOLOGIES BASED ON HDL’S 11 TABLE III ADVANTAGES AND DISADVANTAGES OF THE PROPOSED METHODOLOGY Fig. 10. System on chip. macrocell based design. • the design of systems on chip, by including modules designed in a reusable way. In both cases, the use of an HDL is a must. In the first case, there is a need of having a description that can be targeted to different technologies and that can be easily adapted to different architectures (FPGA’s, ASIC’s, etc.). The module supplier should provide the potential users with the information to complete the design and to check the final system performance. In the second case, the model supplier must provide the required information to complete the design, including a simulation model to check the whole system, the test vectors, a data sheet, etc. This design method based on macrocells [also called intellectual properties (IP’s)], allows greater complexities than traditional methods. The concept system on chip as a system that contains a CPU, memory, and periphery is affordable by reusing others’ designs [21]. From the design point of view, it is required to have appropriate tools to simulate the whole design (an HDL simulator, for example) and even to run software programs in the HDL model. These “virtual” systems require that the hardware–software interaction is well defined and new CAD tools are needed. Fig. 10 shows an example of the blocks that can be included in a chip, based on macrocells. IX. CONCLUSIONS The design process based on HDL’s has been presented in this paper. The main steps in the design process have been pointed out, as well as the tools involved in each stage. In the paper, some of the advantages and disadvantages of the process have been pointed out, which are summarized in Table III. In spite of the drawbacks that are found in the method, the HDL-based design is a good solution to deal with the complexity of current electronic systems. So far, it is restricted to digital systems, but some effort is being made to extend some of these concepts to analog electronics. Besides, some of the problems related to testing are being studied to obtain a test methodology similar to the design method. The forecast for the use of this process is very promising. A large group of designers is moving from old methodologies to those based on HDL’s. Some companies and institutions are starting to demand HDL documentation for all their designed systems. The method, that was only used by ASIC designers, is beginning to get into the systems, and this implies that new design tools for system design will appear in the near future. Among these tools, there is a very important issue, which is the possibility of hardware–software codesign based on HDL’s. REFERENCES [1] IEEE Standard VHDL Language Reference Manual, IEEE Std 10761987, Mar. 1988. [2] D. Thomas and P. Moorby, The Verilog Hardware Description Language. Norwell, MA: Kluwer, 1991. [3] M. Carroll, “VHDL-panacea or hype?,” IEEE Spectrum, vol. 30, pp. 34–37, June 1993. [4] D. D. Gajski and R. Kuhn, “Guest editors’ introduction: New VLSI tools,” IEEE Computer, vol. 16, pp. 11–14, Dec. 1983. [5] P. Michel, U. Lauther, and P. Duzy, The Synthesis Approach to Digital Systems Design. Norwell, MA: Kluwer, 1992. [6] R. Waxman, J. M. Berge, O. Levia, and J. Rouillard, High-Level System Modeling. Specification and Design Methodologies. Norwell, MA: Kluwer, 1996. [7] “PRENDA: ASIC design methodology,” Div. Ing. Electrón., Univ. Politécnica Madrid, Madrid Spain, Rep., Nov. 1996. [8] “ASIC design and manufacturing requirements (issue 2),” ESA/ESTEC, Rep., Paris, France, Oct. 1994. [9] T. Riesgo, Y. Torroja, and J. Uceda, “Design process based on hardware description languages,” in Proc. IEEE Int. Symp. Industrial Electronics (ISIE’94), Santiago, Chile, May 1994, pp. 59–65. [10] S. Olcoz and J. M. Colom, “VHDL through the looking glass,” in Proc. VHDL-FORUM for CAD in Europe, Innsbruck, Austria, Mar. 1993, pp. 13–22. [11] J. M. Berge, O. Levia, and J. Rouillard, Modeling in Analog Design. Norwell, MA: Kluwer, 1995. [12] H. A. Mantooth and M. Fiegenbaum, Modeling with an Analog Description Language. Norwell, MA: Kluwer, 1995. [13] IEEE Standard VITAL ASIC Modeling Specification, IEEE Draft Std. 1076.4, July 1995. [14] L. Lindqvist, “Evaluating the applicability of current VHDL synthesis tools to an industrial top-down development procedure,” in Proc. VHDL Int. Users’ Forum, San Jose, CA, Oct. 1993, pp. 1–7. [15] C. F. Hawkins, H. T. Nagle, R. R. Fritzemeier, and J. R. Guth, “The VLSI circuit test problem—A tutorial,” IEEE Trans. Ind. Electron., vol. 36, May 1989. [16] T. W. Williams and K. P. Parker, “Design for testability—A survey,” Proc. IEEE, vol. 71, pp. 98–112, Jan. 1983. 12 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 46, NO. 1, FEBRUARY 1999 [17] ,IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990, 1990. [18] E. de la Torre, J. Calvo, and J. Uceda, “Model generation of test logic for macrocell based design,” in Proc. EURO-DAC with EURO-VHDL’96, Geneva, Switzerland, Sept. 1996, pp. 456–461. [19] T. Riesgo, J. Uceda, and F. Aldana, “High level testing for digital VLSI—A survey,” in Proc. IECON’93, Maui, HI, Nov. 1993, pp. 402–407. [20] T. Riesgo and J. Uceda, “A fault model for VHDL descriptions at the register transfer level,” in Proc. EURO-DAC with EURO-VHDL’96, Geneva, Switzerland, Sept. 1996, pp. 462–467. [21] C. Liem, F. Naçabal, C. Valderrama, P. Paulin, and A. Jerraya, “Systemon-a-chip cosimulation and compilation,” IEEE Design & Test, vol. 14, pp. 16–25, Apr./June, 1997. Yago Torroja received the Electrical Engineering degree from the Universidad Politécnica de Madrid, Madrid, Spain, in 1990. Since 1990, he has been an Assistant Professor in the Electronic Engineering Division, Universidad Politécnica de Madrid. His main research interests are ASIC design and methodologies, VLSI tools, and embedded systems. Teresa Riesgo (M’96) received the Electrical Engineering and Ph.D. degrees from the Universidad Politécnica de Madrid, Madrid, Spain, in 1989 and 1996, respectively. In 1990, she joined the Electronic Engineering Division, Universidad Politécnica de Madrid, as an Assistant Professor. She is currently an Associate Professor. Her main research interests are ASIC design, VLSI test techniques, and embedded systems. Eduardo de la Torre received the Electrical Engineering degree from the Universidad Politécnica de Madrid, Madrid, Spain, in 1989. Since 1990, he has been an Assistant Professor in the Electronic Engineering Division, Universidad Politécnica de Madrid. His main research interests are ASIC design and testing, VLSI tools, and embedded systems.