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Obtaining a well distributed non-dominated Pareto front is one of the key issues in multi-objective optimization algorithms. This paper proposes an algorithm which promotes well distributed non-dominated fronts in the parameters space... more
Obtaining a well distributed non-dominated Pareto front is one of the key issues in multi-objective optimization algorithms. This paper proposes an algorithm which promotes well distributed non-dominated fronts in the parameters space when a single-objective function is optimized. The proposed technique is described and tested in an automated synthesis circuit design problem. The project consists in designing CMOS radio-frequency and microwave binaryweighted differential switched capacitor arrays (RFDSCAs) from user top-level specification to component size. The genetic synthesis tool optimizes a fitness function based on the performance parameter of the RFDSCAs. To validate the proposed design methodology, a CMOS RFDSCA is synthesized, using a 0.25 μm BiCMOS technology, and verified by the SpectreRF simulator of the Cadence design environment. The results show that the synthesis and simulation outcomes are in very good agreement.N/
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This paper presents a digital low-IF Gaussian frequency-shift keying (GFSK) demodulator. The demodulator is based on a phase-shift quadrature discriminator. A preamble detector controls the sequencing of the blocks operation to minimize... more
This paper presents a digital low-IF Gaussian frequency-shift keying (GFSK) demodulator. The demodulator is based on a phase-shift quadrature discriminator. A preamble detector controls the sequencing of the blocks operation to minimize power consumption. An IF input signal of 1 MHz is used, the same of the data rate, hence, allowing a low-power receiver implementation. The implementation is fully digital with a silicon area of 0.06 mm2 in 130 nm process. Simulations show a state-of-art current consumption of about 143 μA from a single 1.2 V supply voltage. The proposed demodulator requires a SNR of 15 dB for a BER of 0.1 % for up to ± 200 kHz frequency offset variation.
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This paper presents the design and simulation of a 5GHz monolithic low-noise amplifier integrated with an active Balun. Intended to WLAN applications, the fully integrated circuit was implemented in a 0.18 μm CMOS technology. The... more
This paper presents the design and simulation of a 5GHz monolithic low-noise amplifier integrated with an active Balun. Intended to WLAN applications, the fully integrated circuit was implemented in a 0.18 μm CMOS technology. The simulations, optimized to noise performance, gain and minimum differential phase and magnitude error, were performed with BSIM3 model. Circuit simulations present 23dB differential power gain at 5GHz, a phase and a transducer gain magnitude errors less than 1o and 0.2dB, respectively, in a 100MHz span around 5GHz, NF =3.6dB, 1dB CP = -22dBm, IIP3 = -8dBm, 50 Ω input and output match, while drawing 8mA from a 1.8V power supply.
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Current-mode class-D (CMCD) power amplifiers (PAs) may not achieve a switching efficiency as good as class-E PAs, but they require fewer inductances and deliver almost five times more power for the same load and supply voltage when... more
Current-mode class-D (CMCD) power amplifiers (PAs) may not achieve a switching efficiency as good as class-E PAs, but they require fewer inductances and deliver almost five times more power for the same load and supply voltage when compared with the ideal push–pull class-E PA. Furthermore, CMCD PAs can easily use bondwires as the only circuit inductors, a precious feature that Internet-of-Things (IoT) wireless interfaces can exploit. For this reason, we analyze the voltage and current waveforms in CMCD PAs without assuming infinite value feeding inductors (i.e., without choke inductors). It is shown that the current stress on the switching device is significantly higher than in the conventional topology, especially in bondwire-based designs where relatively small feeding inductances are presented. Finally, we propose a design procedure for a given feeding inductance that maximizes energy efficiency while delivering a compact-size solution. A 2.4-GHz PA capable of delivering 19.8 dBm to a 100-<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> differential load with a power-added-efficiency (PAE) of 58% is presented. Three-dimensional electromagnetic (3-D EM) simulations combined with postlayout simulations were used to evaluate the PA performance in a quad-flat nonlead (QFN)-type package. The circuit is designed in a 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu \text {m}$ </tex-math></inline-formula> process and only occupies a silicon area of 0.025 mm<sup>2</sup>.
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The limitations on the implementation of BiCMOS activeinductors at 2GHz are described. The circuit is based on atwo BJT feedback configuration. Two types of biasingcircuits were used: active bias and resistive bias. With 0.8mBiCMOS... more
The limitations on the implementation of BiCMOS activeinductors at 2GHz are described. The circuit is based on atwo BJT feedback configuration. Two types of biasingcircuits were used: active bias and resistive bias. With 0.8mBiCMOS standard technology is possible to obtain up to afew nanohenry inductance with a Q close to 3 at 2GHz. TwoMMIC were studied.I.
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Research Interests: Analog Circuits, Soft Computing, Particle Swarm Optimization, Genetic Algorithm, Design method, and 10 moreQuality Factor, Radio Frequency, Digital Circuit Synthesis, Fitness Function, Switched Capacitor Filters, Particle Swarm Optimizer, Objective function, parameter space, Particle Swarm Optimization Algorithm, and Circuit synthesis
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Research Interests: Asia Pacific, Q factor, Mmic, Mosfet Model, Spirals, and 4 moreInductance, L BAND, Dynamic Range, and Gyrators
Research Interests: APMC, Si, Frequency, Mmic, Active Filters, and 6 moreBand Pass, Active Filter, Bandwidth, L BAND, Selectivity, and Band pass filters
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It is noted that series feedback oscillators stabilized with dielectric resonators (DRs) usually have the two resistive elements of the feedback network (DR and load) in different branches. A design technique for these oscillators is... more
It is noted that series feedback oscillators stabilized with dielectric resonators (DRs) usually have the two resistive elements of the feedback network (DR and load) in different branches. A design technique for these oscillators is presented which leads to the maximum added power condition and optimization of frequency stability and noise immunity. The nonlinear characterization of the active device is obtained assuming an empirical relation to the power-gain saturation characteristics. The oscillator stability is verified by means of graphical methods based on the network determinant or and on the negative resistance oscillator theory of Kurokawa (1969). The six possible topologies are analyzed for a typical X-band GaAs MESFET using the proposed method. A comparison is made, taking into account the circuit implementation in microstrip, stability, AM and FM noise, spurious oscillations, transient response, and loaded Q-factor
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Abstract: This paper presents the design and simulation of a CMOS fully integrated 5GHz low-noise (LNA) amplifier for WLAN applications. The circuit was implemented in a 0.18 μm CMOS standard CMOS process. The simulations, optimized to... more
Abstract: This paper presents the design and simulation of a CMOS fully integrated 5GHz low-noise (LNA) amplifier for WLAN applications. The circuit was implemented in a 0.18 μm CMOS standard CMOS process. The simulations, optimized to noise performance, gain ...