Phase Locked Loop

In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current,
and no jump output voltage. In order to verify such operation, circuit
simulation is performed using 0.18 μm CMOS process parameters.

This paper proposes a simple and effective control technique for interconnection of DG resources to the power grid via interfacing converters based on Phase locked loop (PLL) and Droop control. The behaviour of a Microgrid (MG) system during the transition from islanded mode to grid-connected mode of operation has been studied. A dynamic phase shifted PLL technique is locally designed for generating phase reference of each inverter. The phase angle between filter capacitor voltage vector and d-axis is dynamically adjusted with the change in q-axis inverter current to generate the phase reference of each inverter. During fluctuations in load capacity, the grid-connected system must be able to supply balanced power from the utility grid side and micro-grid side. Therefore, droop control is implemented to maintain a balanced power sharing. The inverter operates in voltage control mode in order to control the filter capacitor voltage. An adjusted droop control method for equivalent load sharing of parallel connected Inverters, without any communication between individual inverters has been proposed. The control loops are tested with aid of MATLAB Simulink tool during several operating conditions.

This paper presents an improved design of voltage
controlled oscillator (VCO)  utilizing the three differential cell
CMOS inverters for forming the ring oscillator. The differential
cell reduces the power supply fluctuations impact on the
oscillator jitter while the negative feedback from frequency to
voltage converter reduces the jitter at high frequencies. Finally
the proposed model is designed using CMOS 0.18um foundry
technology and simulated using P-Spice software. The result
shows that the proposed design improves the jitter attenuation at
different offset frequencies up to 40dB.

This paper presents the design of a two-stage CMOS differential voltage-controlled ring oscillator (VCO). The VCO is designed to operate as a module of the frequency synthesizer in a PLL to generate the local oscillator (LO) of a multi-band acquisition system, providing quadrature output. The goal is a wide operating frequency tuning range of 440 MHz-1.4 GHz in the VCO with low power consumption, 90 dBc/Hz @ 600 KHz phase-noise performance and good linearity between the frequency and control voltage. Simulation results verify the theoretical development as well as the final layout design. The symmetric load transistor operation region controls the frequency behavior achieved by the ring VCO, which shows a monotonic relation with the control voltage when the loads are operated in saturation. The circuit was designed, implemented and simulated in a 0.18 mum IBM CMOS technology.

Basic methods of frequency control voltage-source series-resonant inverter induction heating equipment were considered. A comparative analysis of a phase-locked loop (PLL) systems and approaches in design them for voltage-source series-resonant inverter were presented. Analytical expressions for determining an optimal current switching transistor of voltage-source series-resonant inverter, time of transistor's recharge parasitic capacitances with snubber's capacitance, as well as the delay time between the control signals of the transistor, and time which corresponds to the phase shift between the input signals of the phase detector PLL are established.

A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DLL phase filtering to achieve sub-ps resolution independent of the operating frequency. Test chip fabricated in a 0.13mum CMOS process achieves a DNL below plusmn100fs and plusmn12ps INL and consumes 15mW while operating at 1GHz

The realization of power electronic applications on hardware is a challenging task. The digital control circuit strategies are used to overcome the analog control strategies by providing great flexibility with simple equipment and higher switching frequencies. In this manuscript, an area optimized, modified digital space vector (DSV) pulse width modulation is designed and realized on low-cost FPGA. The modified digital space vector pulse width modulation (DSVPWM) uses a phase-locked loop (PLL) to generate clocks using the digital clock manager (DCM). These DCM clocks are used in the DSVPWM module to synchronize the other sub-modules. The voltage generation unit generates the three-phase (3-Ф) voltages and is used in the alpha-beta generation and sector determination unit. The reference active vectors are made by the reference generation unit and used in switching time calculation. The PWM pulses are generated using switching time generation, and lastly, the dead time occurrence unit generates the final SVPWM gate pulses. The modified DSVPWM is synthesized and implemented on Spartan3E FPGA. The modified DSVPWM utilizes 17% slices, works at 102.45 MHz, and consumes 0.070 W total power. The simulation results and the resource utilization of modified DSVPWM are represented in detail. The modified DSVPWM is compared with existing PWM approaches on different Spartan-series FPGAs with better chip area improvement.

In this paper the Synchronous Reference frame PI-based control method for generating the reference signals for the Voltage Source Converter of Shunt Active Power Filter (SAPF) is presented. The method relies on the performance of the Proportional-Integral (PI) controller for achieving the best control performance of the SAPF. To improve the performance of the PI controller, the feedback path to the integral term is introduced to compensate the winding up phenomenon due to the integrator. Using Reference Frame Transformation, reference signals were transformed from c b a   stationery frame to q d   0 rotating frame. Using the PI controller, reference signals in q d   0 rotating frame were controlled to get the desired reference signals for the Pulse Width Modulation. Using MATLAB/SIMULINK, the 5 th , 7 th , and 11 th harmonics were used to test the proposed Active Power Filter with improved PI controller resulting in harmonic content down to 3.87%.

A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.

The analog front end of an echo cancellation burst mode (ECBM) transceiver operating from a single 5-V supply is described. The chip performs pulse shaping and line driving in the transmit section and hybrid function, equalization, A/D and D/A conversion, automatic gain control, threshold detection for a phase-locked loop (PLL), and wake-up in the receive section. The partitioning between analog and digital functions is explained. The analog portion of the chip is described for both the receive and transmit portions, and design considerations for the various building blocks are outlined. The chip contains 45 amplifiers of seven different types and three different types of comparators and dissipates about 160 mW in the normal operation mode and 5 mW in the power-down mode. The die area is 50000 mil2 in a 2-μm, double-poly, single-metal CMOS technology

This paper presents a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed analog-to-digital converters (ADCs) with moderate resolutions. The proposed system is suited to be fully integrated with the ADC and, besides a low jitter clock reference, no other external high quality generators are required. The complete system comprises two synchronized phase-locked loops (PLLs), one based on a two-integrator oscillator capable of providing low distortion outputs and another based on a relaxation oscillator providing low jitter squared output, to allow coherent sampling. A detailed description of the building blocks of both PLLs is given as well as the techniques used to minimize area of the loop filters (LFs), to stabilize the output amplitude of the two-integrator oscillator to a known value, and to improve the total harmonic distortion (THD) of this oscillator. Post-layout simulations, in a 0.13 μm CMOS technology, of the proposed BIST scheme applied to a case-study 6-bit 1 GS/s ADC are shown and validate the proposed test methodology.

In conventional receivers, carrier recovery and timing recovery are performed in the analog domain by controlling the frequency and phase of voltage controlled oscillators (VCO) in their respective phase locked loop (PLL). When the control signal for these loops are generated in the sampled data domain by DSP techniques the digital samples must be brought to the analog domain by a pair of digital-to-analog converters (DAC). It is more cost effective to perform the entire signal processing function of the PLL in the digital domain and avoid the cost of the DAC and analog smoothing filter in the processing loops. In the full DSP implementation the receiver performs an initial complex down conversion with an asynchronous local oscillator set to the nominal final conversion frequency and then absorbs the residual carrier and phase uncertainty by data dependent control of a digital complex rotator. In a similar fashion sample timing is performed by the sampling the input signal with an asynchronous sampling clock operating at nominally twice the symbol rate and then absorbs residual frequency and phase of the sampling clock by resampling the data with a polyphase filter bank

An integrated heterodyne optical phase-locked loop was designed and demonstrated with an indium phosphide based photonic integrated circuit and commercial off-the-shelf electronic components. As an input reference, a stable microresonator-based optical frequency comb with a 50-dB span of 25 nm (~3 THz) around 1550 nm, having a spacing of ~26 GHz, was used. A widely-tunable on-chip sampled-grating distributed-Bragg-reflector laser is offset locked across multiple comb lines. An arbitrary frequency synthesis between the comb lines is demonstrated by tuning the RF offset source, and better than 100Hz tuning resolution with ± 5 Hz accuracy is obtained. Frequency switching of the on-chip laser to a point more than two dozen comb lines away (~5.6 nm) and simultaneous locking to the corresponding nearest comb line is also achieved in a time ~200 ns. A low residual phase noise of the optical phase-locking system is successfully achieved, as experimentally verified by the value of 80 dBc/Hz at an offset of as low as 200 Hz. Hall, and S. T. Cundiff, " Carrier-envelope phase control of femtosecond mode-locked lasers and direct optical frequency synthesis, " Science 288(5466), 635–639 (2000). 2. J. Castillega, D. Livingston, A. Sanders, and D. Shiner, " Precise measurement of the J = 1 to J = 2 fine structure interval in the 2(3)P state of helium, " Phys.