A HIGH SWING LOW POWER CMOS DIFFERENTIAL VOLTAGECONTROLLED RING OSCILLATOR Luciano Severino de Paula, Eric Fabris, Sergio Bampi, Altamiro Amadeu Susin Federal University of Rio Grande do Sul - DELET Av. Osvaldo Aranha, 103 – Zip 90035-190 – Porto Alegre – RS - Brazil {lspaula, fabris, bampi }@inf.ufrgs.br, susin@eletro.ufrgs.br ABSTRACT This paper presents a two-stage CMOS differential voltage-controlled ring oscillator (VCO). The VCO is intended to operate as a frequency synthesizer in a PLL to generate local oscillator frequency (LO) for an acquisition system, providing quadrature output. The proposal is to design a differential VCO that has a wide operating frequency tuning range with low power consumption, better phase-noise performance and good linearity between the frequency and control voltage. Simulation results verify the theoretical development and address the layout design. The circuit was designed and simulated in 0.18µm IBM CMOS technology. than the threshold voltage Vtn and the oscillation frequency is directly proportional to control voltage Vc . 1. INTRODUCTION Figure 1 – Proposed VCO circuit This paper describes a monolithic ring VCO based on the differential ring oscillator structure. The VCO is intended to be fabricated in an IBM 0.18µm CMOS standard process, and it oscillates from 186 MHz to 1.576 GHz with a single 1.8V supply. Section 2 presents the detailed circuit of the proposed delay cell. In Section 3, the simulation results of the VCO are described and concluding remarks follow in Section 4. The polarization scheme composed by transistors M8 to M13 provides a controlled bias current and a controlled voltage Vc ' in such a way that the transistors M4 and M5 stay in the saturation region in the whole control voltage range. Also this arrangement avoids the cells to lose gain maintaining a lineal relation between the control voltage Vc and the tail current provided to the cells by M7. Transistor M10 allows establishing a minimum current for the delay cells even if the control voltage leaves its nominal values. 2. CIRCUIT DESCRIPTION In the delay cells proposed in this work, we provide the necessary bias condition for the circuit to oscillate by means of using the positive partial feedback [6] generated by M1f and M2f, as depicted in figure 1. In the upper portion of the circuit, we have M3 and M4 or M5 and M6, that implements a voltage controlled symmetrical load [7] modifying the delay when the control voltage Vc’ is changed, together with the oscillation frequency. The use of this type of load allows diminishing the sensibility to variations in common mode and also the phase-noise of the circuit [7]. To observe the behavior of the circuit, let’s consider the case in that transistors M4 and M5 are in the saturation region, where the output swing must be less Table 1 – Sizes of the devices W/L Device 40 M1, M2 M3 – M6, M13 55.56 555.6 M7 27.78 M8,M10 83.33 M9 444.44 M11 138.89 M12 38.89 M1f, M2f The final sizes of the devices for the delay cells and the bias circuit are shown in table 1. 3. SIMULATION RESULTS The circuit was simulated using IBM 0.18µm technology, providing preliminary results for a future prototipation. The results are stated in table 2 together with other high performance ring VCOs. the tuning range showed good linearity. The characteristics of this VCO are highly attractive for use in PLL systems. Table 2 – Results of the proposed ring VCO Parameter Supply Voltage (V) Power consumption (mW) Tunning Range (MHz) Phase-noise (dBc/Hz) @offset(KHz) Central frequency (MHz) Area (µm2) Gate length (µm) # of delay cells [1] [2] [3] [4] [5] This work 2.5 2.0 3.3 1.8 3.3 1.8 15.4 18.95 7.01 26 24.5 11.38 6611270 650– 1040 2002100 4401595 450– 1150 1861576 -105 @600 -116 @600 -90 -73.3 -106 @100 @100 @500 -113.5 @600 900 913 1200 12750 6750 0.5 0.18 2 2 900 866 850 5231 - 4035 - 0.35 0.18 0.35 0.18 2 2 2 2 Figure 3 – Frequency of VCO vs. control voltage Vc As future work, the circuit will be implemented in silicon to evaluate its real performance. To measure the characteristics of the circuit, a buffer stage will be designed to make possible driving external charges as pad and instrument capacitances. 5. REFERENCES [1] W. Yan, H. C. Luong, “A 900-MHz CMOS Low-Phasenoise Voltage-Controlled Ring Oscillator”, IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 48, No. 2, pp. 216-221, February 2001. [2] D. A. Badillo and S. Kiaei, “A low phase-noise 2.0 V 900 MHz CMOS voltage controlled ring oscillator”, Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 international Symposium on Volume 4, 23-26 May 2004 Page(s):IV - 533-6. Figure 2 – Phase noise and time domain behavior The phase noise and the time domain behavior of the VCO are shown in figure 2, where the VCO is operating in a frequency of 881.5MHz. Figure 3 shows the relationship of the operation frequency of the VCO and the control voltage Vc . The simulation results shows that if the transistors M4 and M5 are equal in size to M3 and M6, the whole voltage control range is restricted to operate in the saturation region as stated previously because of the provided bias scheme. 4. CONCLUSION The design of a wide range, low power consumption VCO was detailed in this work. The structure showed that the relation between the oscillation frequency and the control voltage behaves according the operation region of the symmetric load transistors. The maximum power consumption of the circuit is only 11.38mW and [3] D. P. Bautista and M.L. Aranda, “A low power and high speed CMOS Voltage-Controlled Ring Oscillator”, Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on Volume 4, 23-26 May 2004 Page(s):IV - 752-5 Vol.4. [4] Y. Chuang and S.L. Jang, ”A low voltage 900MHz Voltage Controled Ring Oscillator with wide tunning range”, Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on, pages 301 – 304, vol.1. [5] W. Xin, Y. Dunshan and S. Sheng, ”A Full Swing And Low Power Voltage-Controlled Ring Oscillator”, Electron Devices and Solid-State Circuits, 2005 IEEE Conference on 19-21 Dec. 2005 Page(s):141 – 143 [6] E. Wang and R. Harjani, “Partial Positive Feedback for gain Enhancement of Low-Power CMOS OTAs”, Analog Integrated Circuits and Signal Processing, 8, pp21-35, 1995. [7] J. Maneatis and M. Horowitz, “Precise delay generation using coupled oscillators,” IEEE J. Solid-State Circuits, vol. 28, No. 12, pp. 1273-1282, Dec 1992.