Jubayer Jalil

T he integrated dif-ferential ring oscil-l a t o r (D RO) i n c o m p l e m e n t a r y metal oxide semi-conductor (CMOS) technol-ogy has been used in numer-ous products for a long time. Its presence has been extended to high-speed clock and data recovery (CDR) circuits for opti-cal communication, analog and digitally controlled oscillators, fre-quency dividers of high-frequency synthesizers, clock generators of digi-tal circuits, analog-to-digital convert-ers (ADCs), and many more applications [1]–[5]. Implementations of these ring oscilla-tors are seen in emerging technologies such as ultrawideband (UWB) and radio frequency iden-tification (RFID) as well as wireless sensor networks (WSNs) and short-range communication devices [6], [7]. The DRO is a good design choice for integrated circuit (IC) designers because of its continued use in different bulk CMOS tech-nologies. This article presents implementation techniques and performance comparisons of the DRO as a CMOS voltage-control...

ABSTRACT Designing a compact, power efficient voltage controlled oscillator (VCO) for high frequency phase lock loop (PLL) in modern wireless communication system is decisively a challenging task. Inappropriately designed VCOs for battery-powered radio frequency identification (RFID) transponder cause huge degradation of overall system. The proposed work presents a low power 2.45 GHz VCO developed for active readerless transponder compatible with IEEE 802.11b protocol. A 3-stage, single delay path, differential ring oscillator based architecture has been adopted for the ease of integration and implementation of the circuit in small die area. 0.18μm CMOS process is used for designing the proposed VCO. Simulated results showed that the proposed VCO would work in the tuning range of 2.4GHz-2.5GHz with 1.8V supply. Thus, the proposed VCO will be a key component for readerless RFID transponder.

ABSTRACT Radio frequency identification (RFID) is lagging behind because of vendor specific solutions and expensive implementation cost. In particular, the reader is the most expensive part. A WiFi compatible tag was proposed to use the WNIC as an RFID reader. However, no specific modulator or demodulator was suggested. This paper analyzes the various IEEE 802.11 standards and their modulation and coding techniques keeping the desired properties of an RFID system in consideration. After the analysis, a digital modulator and demodulator for RFID tag in IEEE 802.11 protocol employing Direct Sequence Spread-Spectrum (DSSS) and coding is proposed. A MOD-11 synchronous counter is designed for the 11-bit encoder which generates the desired Barker code. Data are multiplied with this Barker code to modulate the data, and the received data are multiplied with the Barker code to demodulate them. The proposed modulator and demodulator are implemented in 0.18μm CMOS technology. The simulation results show that 1 bit is spread to 11 bits by the modulator and 11-bit received data are demodulated to 1 bit correctly. The proposed design is simple, resistant to multipath fading and interference and offers the highest distance with the lowest BER for an RFID tag.

ABSTRACT Radio frequency identification (RFID) is a ubiquitous identification technology nowadays. An on-chip high-performance transmit/receive (T/R) switch is designed and simulated in 0.13-μm CMOS technology for reader-less RFID tag. The switch utilizes only the transistor width and length (W/L) optimization, proper gate bias resistor and resistive body floating technique and therefore, exhibits 1 dB insertion loss, 31.5 dB isolation and 29.2 dBm 1-dB compression point (P1dB). Moreover, the switch dissipates only 786.7 nW power for 1.8/0 V control voltages and is capable of switching in 794 fs. Above all, as there is no inductor or capacitor used in the circuit, the size of the switch is 0.00208 mm2 only. This switch will be appropriate for reader-less RFID tag transceiver front-end as well as other wireless transceivers operated at 2.4 GHz band.

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 μm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5-2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of -126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

ABSTRACT Speed is one of the basic reasons for vehicle accident. Many lives could have been saved if emergency service could get accident information and reach in time. Nowadays, GPS has become an integral part of a vehicle system. This paper proposes to utilize the capability of a GPS receiver to monitor speed of a vehicle and detect accident basing on monitored speed and send accident location to an Alert Service Center. The GPS will monitor speed of a vehicle and compare with the previous speed in every second through a Microcontroller Unit. Whenever the speed will be below the specified speed, it will assume that an accident has occurred. The system will then send the accident location acquired from the GPS along with the time and the speed by utilizing the GSM network. This will help to reach the rescue service in time and save the valuable human life.

ABSTRACT Charge pump circuit is widely used in many systems due to its low power consumption, high performance, small area and low current drivability. This paper presents a low-voltage, high performance charge pump circuit suitable for low-voltage applications such as EEPROM of Radio Frequency Identification (RFID) tag. Designed in 0.18-μm CMOS process, the proposed charge pump circuit is able to pump an input voltage of 1.8V to a measured output of 5.95V through 20MHz clock signal with each pumping capacitor of 0.1pF and smoothing capacitor of 0.1pF at the output. Simulation result shows that the proposed charged pump circuit offers higher pumping gain compared with the existing charge pump circuit. Besides the RFID tag, the charge pump circuit can also be used in other memory circuits.

ABSTRACT Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC) by process in 0.18 mu m CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ)-comparator, the encoder and the parallel input serial output (PISO) register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 mu m(2) and the power dissipation is 0.162 mu W with 1.6 V supply voltage.

Elliptic Curve Cryptography (ECC), which allows smaller key length as compared to conventional public key cryptosystems, has become a very attractive choice in wireless mobile communication technology and personal communication systems. Any ...

ABSTRACT Radio frequency identification (RFID) is the utilization of the radio frequency for the purpose of identification. RFID is lagging behind due to vendor specific solutions and excessive implementation cost. A Wireless Fidelity (WiFi) compatible IEEE 802.11 RFID tag can overcome these limitations. IEEE 802.11 utilizes Direct Sequence Spread Spectrum (DSSS) technique and a matched filter is a vital block in a DSSS system. A low-power and low-area novel adder-less Barker matched filter is proposed in this paper by eliminating the conventional multiple multiplications. The matched filter designed in 0.18 µm CMOS technology achieves average and maximum power consumption of 33.747 μW and 8.08 mW, respectively and chip area of 0.41184 mm2 only. The simulation result shows the correct matching of data against the threshold value. Compared with the conventional matched filter, the design achieves 25% power reduction (maximum power) and 51% chip area reduction. Therefore, the design will help to implement a low-power matched filter for IEEE 801.11 compatible RFID tag. Copyright © 2013 John Wiley & Sons, Ltd.

ABSTRACT The integrated differential ring oscillator (DRO) in complementary metal oxide semiconductor (CMOS) technology has been used in numerous products for a long time. Its presence has been extended to high-speed clock and data recovery (CDR) circuits for optical communication, analog and digitally controlled oscillators, frequency dividers of high-frequency synthesizers, clock generators of digital circuits, analog-to-digital converters (ADCs), and many more applications [1]-[5]. Implementations of these ring oscillators are seen in emerging technologies such as ultrawideband (UWB) and radio frequency identification (RFID) as well as wireless sensor networks (WSNs) and short-range communication devices [6], [7]. The DRO is a good design choice for integrated circuit (IC)designers because of its continued use in different bulk CMOS technologies. This article presents implementation techniques and performance comparisons of the DRO as a CMOS voltage-controlled oscillator (VCO) in low radio frequency (RF) bands, along with presentation and discussion of a number of circuit approaches.

ABSTRACT This study describes a hardware modeling environment of built-in-self-test (BIST) for System on Chip (SOC) testing to ease the description, verification, simulation and hardware realization on Altera FLEX10K FPGA device. The very high speed hardware description language (VHDL) model defines a main block, which describe the BIST for SOC through a behavioral and structural description. The three modules test vector generator, circuit under test and response analyzer is connected using its structural description. 8-bit pseudorandom test vector generator is a linear feedback shift register circuit consists of D latches and XOR gates produces 255 different patterns of test vectors for CUT which consists of a 3 to 8 line decoder and a 4 bit adder circuit. In response analyzer, the multiple-input pattern compressor circuit is used to produce signature and a comparator circuit is used for signature analysis. The design is modularized and each module is modeled individually using hardware description language VHDL. This is followed by the timing analysis and circuit synthesis for the validation, functionality and performance of the designated circuit, which supports the practicality, advantages and effectiveness of the proposed hardware realization for the applications with a maximum clock frequency of 31.4 MHz.