Design Trends in Fully Integrated 2.4 GHz CMOS SPDT Switches Abstract: Fully integrated CMOS single pole double through (SPDT) Transmit/Receive (T/R) switch is an essential component of every compact transceiver for enabling sharing of a single antenna between its transmitter and receiver. The switch is expected to encompass very low insertion loss, relatively higher isolation with high power handling capability. But there is inevitable trade-off among the parameters of the switch which makes the design even more challenging at 2.4 GHz ISM band. This paper presents a bibliographical survey of the work published on improved performance of different switch topologies for 2.4 GHz ISM band transceiver applications. Different techniques reported in literatures for further improvements in the characteristics of CMOS switches are also highlighted. This review will serve as a comparative study and reference for the researchers in designing T/R switches for future 2.4 GHz ISM band applications. Keywords: CMOS, integrated, ISM band, SPDT, T/R switch, transceiver, wireless. INTRODUCTION The level of integration of modern transceivers has augmented in the last few years, resulting in compact as well as low cost wireless communication devices [1-4]. Regardless of this advancement, the emerging short-range wireless communication applications have encouraged the need for even higher level of integration to eliminate a number of board level constituents to ensure low-cost, small area wireless systems [5,6]. Modern transceiver front-end, comprises of a single transmitter (Tx) branch and a receiver (Rx) branch, which cannot be imagined without a high performance T/R switch [7]. A fully integrated communication system at radio frequencies requires sharing a single high performance antenna for both transmitter and receiver that can be realized by implementation of a suitable switch [8]. This switch provides adequate isolation between the transmitter and receiver as well as the tractability in attaching the antenna(s) either to the transmitter or the receiver according to the needs in multi-mode communication systems. Fig. (1) shows the role of a T/R switch in a compact transceiver. In the receive mode, the T/R switch ties the antenna to the receiver offering high impedance to the transmitter, whereas in the transmit mode, the switch ties the antenna to the transmitter and imposes high impedance to the receiver. But several problems and limitations have been identified and reported on this topic, mainly transmission power loss as a result of imperfect separation of the receiver circuits and sensitivity loss because of the employment of external switches which bring in a non negligible nonlinearities and insertion loss [9,10]. Fig. (1). SPDT T/R switch and marching network at the transceiver front end. In recent transceivers, T/R switches are normally realized by using external components like MEMSs, MESFETs, PHEMTs, PIN diodes etc [11]. Conventionally, PIN diodes are given priority because of their moderate small signal performance and good linearity [12]. But power dissipation and size are the important issues to be considered for PIN diodes [13]. Besides compound semiconductor switches such as GaAs have excellent impedance characteristics due to high electron mobility and high breakdown electric field to boost the power handling capability. Nevertheless, in these structures the presence of Schottky gates confines the forward bias voltage at the gate terminal to switch on voltage of the Schottky diode which is about 0.7V for GaAs. It is, therefore, more complicated to fabricate large number of MESFETs with threshold voltage smaller than that [14]. These problems necessitate the introduction of CMOS process to fabricate RF switch. In this decade, wireless communication systems have experienced a rapid progress due to the advancement of CMOS technology. CMOS technology is capable of meeting the more stringent cost constraints inherent in these applications [15,16]. In RF regime, the benefits of silicon CMOS technology are due to its economical structure and its potentiality to integrate with RF and silicon MOS-based mixedsignal circuitry. With the advancement of CMOS technology, it offers the prospect for integration of RF/digital/analog functions on a single chip in a low-cost manner [17,18]. As a result, CMOS RF switch is a promising solution for modern wireless circuits to fulfil the demand of low-power and lowcost design, and therefore nowadays are increasingly replacing off-chip components like PIN diodes, MESFETs etc. in RF systems [19]. Utilizing the advantages of unlicensed 2.4 GHz band, the demand of wireless devices such as RFID, Bluetooth, Zigbee and Wi-Fi devices, non-contacting medical instruments, sensors etc is continuously increasing [20]. As the sizes and performances of such devices mainly depend on the sizes and performances of their transceivers, therefore, it is essential to enhance the performance enhancement of such wireless transceivers [21,22]. The aim of this article is to present various aspects of designs and performances of T/R switches in different CMOS processes for 2.4 GHz ISM band applications and review their recent advances based on key performance parameters. where,
n is the mobility of electrons and Cox represents capacitance of the gate. • Isolation: Isolation refers to the ability to prevent a signal from appearing at a node in the circuit where it is unwanted which means the magnitude of a signal that is coupled across an open circuit. It measures the performance of a T/R switch capable of preventing the outflow of signal from one node to other nodes instead of the required node i.e. the signal obtained at the on-thru port when the signal coupled to the off-thru port or vice versa is the measurement of isolation. Interference between an output port of transmitter and an input port of a receiver is inevitably introduced. Hence, the isolation during TX/RX mode selection is one of the key design specifications. Isolation provided by the switch between transmitter and receiver should be enlarged. • Power handling capacity: Power handling capacity is evaluated by the 1-dB compression point (P1dB) measured by the input power that causes a drop of 1 dB in the linear gain because of saturation of the device. P1dB is also considered as a measure of nonlinearity of the switch but sometimes it is not handy because T/R switches are usually planned to possess less than 1 dB insertion loss. Power handling capability of a device is very important specially in transmitter sections and should be maximized. • Linearity: When the output varies in a linear manner with respect to the variations at the input of a device it is called its linearity. In reality, linearity is normally determined from the value of third-order intercept point (IP3). It is directly related to nonlinear products due to the third-order nonlinear term to the linear term. The concept of intercept point is entirely mathematical and is not related to a practical/ physical power level. It is obtained from graphical method by plotting output power with respect to input power both on logarithmic scales. • Offset: When the input port of a device is grounded but there is still a nonzero voltage at the output port is called offset. Offset should be minimized for better performance. • Switching time: The time delay between the output and the input signals through a T/R switch during its operation is its switching time. The switching time is expected to be shortened as much as possible. • Reliability: It is the ability of the switch to perform and maintain its functions properly with time even during the variation of different process parameters such as temperature, supply voltage etc. SWITCH PERFORMANCE PARAMETERS The key factors for the assessment of a T/R switch’s performance are determined by the followings [13,23]: • Insertion loss: The loss incorporated into a transceiver due to the use of T/R switch is called insertion loss. This type of loss is primarily for the channel resistance i.e. the finite on state resistance of the series transistors is determined by the ratio of the power conveyed to the effective on-thru load impedance and the power obtained at the total effective impedance. Generally, the enlargement of the gate width of transistors diminishes the channel resistance hence improves insertion loss, but at the same time it enlarges the transistor capacitive coupling to the substrate. As a result, signal losses in the substrate increases and therefore, isolation degrades. This phenomenon is accentuated with the increase of frequency. An optimal value for the transistor gate width should be implemented for a given frequency band to facilitate minimizing the insertion loss. Insertion loss should be kept as low as possible. The on state resistance and insertion loss of a switch are determined by the following equations [24,25]: Ron = 1 W μ n Cox (VGS
VTH ) L IL ( dB ) =
20 log 10 (Vout ) (Vin ) (1) (2) Therefore, T/R switches should be designed in such a way having less insertion loss, better isolation, large power handling capacity, little offset, tiny switching interval along with adequate reliability [25]. But in an RF switch design, the best trade-off among insertion loss, isolation and power handling (P1dB) must be set up at a given frequency band [26]. For silicon CMOS switches (opposite of GaAs ones), this trade-off becomes vital as a result of utilization of low resistive substrate that helps increase in losses and decrease in isolation [27]. ADVANCEMENT OF CMOS T/R SWITCHES An assessment of literatures divulges that there are mainly two usual circuit configurations for CMOS T/R switches, the series- and shunt/series-type switches. Figs. (2 and 4) show the basic structures of series and shunt/series CMOS switches. Several modifications on these two topologies are provided by researchers to obtain better performance CMOS T/R switches and as a result another two circuit topologies have been introduced which are: Differential and Asymmetric T/R switches. The advancements in T/R switches are described through their circuit architecture and performance point of view. SERIES AND SERIES-SHUNT T/R SWITCHES A typical series type T/R switch is depicted in Fig. (2). It adopts a transistor (M1) for transmitter and other transistor (M2) for receiver. A proper control signal is needed to be applied at the gates of the transistors to swap their ON/OFF state. For instance, during transmission, Vc is kept high and M1 turns ON; whereas Vc´ is kept low and M2 turns OFF. In this manner, the antenna is made to establish connection with the transmitter and detached from the receiver. During the reception stage the process is quite opposite i.e., M1 is kept turned OFF and M2 is turned ON which lets the antenna to be tied with the receiver. Therefore, this switch demonstrates a single-pole double-throw (SPDT) arrangement. It should be noted that the magnitude of the control voltages (Vc and Vc´) must be below and above the threshold voltage Vth of the transistors, which normally depends on factors like gate width, oxide thickness, temperature etc. Generally, seriestype T/R switches have the advantages of less insertion loss, simple design and almost no power dissipation. Fig. (3). Schematic of series type T/R switch [28]. leads to the shunt/series-type T/R switch. A complement control signal, (Vc and Vc´), is applied at the gate of the transistors, M1 and M2, to alternate the ON/OFF states in the same way as in the series type switch. The series transistors, M1 and M2, execute the main switching task while the shunt transistors, M3 and M4, provide low-impedance paths for the unwanted signals to the RF ground. Therefore, the two shunt arms make the T/R switch having relatively better isolation between transmitter and receiver port compared to previous type switch. Although the isolation is improved in seriesshunt switch but insertion loss of the switch is also found to become deteriorated at higher frequencies. Fig. (2). Series topology of typical SPDT T/R switch. Fig. (4). Series-shunt topology of typical SPDT T/R switch. Yen and Chuang (2005) demonstrated a 2.4 GHz transceiver in 0.25-
m CMOS technology which utilizes a series type T/R switch as shown in Fig. (3) [28]. The switch utilizes two 80-
m/0.24-
m NMOS transistors with gate control voltage of 2.5/0 V. There is an extra resistor R1 which is used to ensure a DC to ground biasing path. A series-shunt T/R switch topology is illustrated in Fig. (4). Addition of two shunt arms to the series-type T/R switch Yamamoto et al. (2001) demonstrated the basic consideration for improvement of performance of both types of T/R switches, shown in Figs. (2 and 4) respectively, from microstuctural design point of view in 0.18-
m standard bulk CMOS technology [23]. In case of Si switches, fabricated on low-resistivity substrates, expanding the gate width of M1 and M2 reduces the on-state resistance and thus insertion loss is improved. Concurrently, with this enlargement there is an increase of substrate parasitics of M1 and M2, which degrades both insertion loss and isolation. This implies that an appropriate gate width will ensure the lowest insertion loss for the Si switches on the substrates with low-resistivity. It is, therefore, indispensable to evaluate the optimal gate width that will provide the least insertion loss along with satisfactory isolation. Fig. (7). Schematic of series-shunt T/R switch [29]. Fig. (5). Equivalent circuit of series topology in Fig. (2) [23]. Fig. (6). Equivalent circuit of series-shunt topology in Fig. (3) [23]. From the small-signal equivalent circuits (in transmit mode), shown in Figs. (5 and 6), for both types of switches, it is anticipated that the shunt/series-type switch fundamentally offers a large insertion loss and isolation compared to a series-type switch. In his design, a control voltage of 1.8 V is used for 200-
m transistors. The total area on the chip is 0.45 mm2. resistances due to the conductive behavior of silicon substrates are some of the significant factors for insertion loss [13] of the switch. To compensate these, only n-channel (0.18-
m length and 300-
m width) MOS transistors with low resistance substrate are used. The transistors are fully surrounded by large area substrate contacts to reduce the series resistances and maximize the Q factor of CDB and CSB. The DC bias of TX and RX nodes has been set to 3.0 V and Vc and Vc’ are 6.0 V and 2.0 V, respectively to perform proper switching operation. Two SPDT switches using P- silicon substrate in 0.18-
m bulk CMOS process for 900 MHz as well as 2.4 GHz applications were described by Huang and Kenneth (2004) [30]. Fig. (8) shows the schematic of SPDT RF switch including significant substrate resistances for 2.4 GHz transceiver. In this design only n-channel MOS transistors with optimized widths are utilized to compensate the onresistance of the transistor. The die area of the chip is (531 x 531)
m2 of which around 63% of the area is made to occupy by substrate contacts to diminish the value of substrate resistances. Impedance transformation method is adopted to meliorate its power-handling capability. A low insertion loss of only 0.8-dB has been reported by Huang and Kenneth (2001) for a series-shunt topology as shown in Fig. (7) [29]. The switch is fabricated using 0.35
m MOSs in a 0.18-
m CMOS technology, exhibiting acceptable isolation and power handling capacity with 3.3/0V control voltage. The low insertion loss is obtained by optimization of bias voltages as well as the transistor widths and by minimization of source/drain-to-body capacitances and substrate resistances. While for maintaining a high P1dB, proper DC biasing at the input and output terminals is utilized. The junction capacitances at drain-to-body and source-tobody (CDB and CSB) of transistors M1 and M2 and the CDB’s of transistors M3 and M4, and associated parasitic Fig. (8). Series-shunt SPDT design with critical substrate resistances [30]. Yeh et al. (2006) improved the overall characteristics of the 2.4 GHz series-shunt switch in a standard 0.18-μm CMOS process by employing body-floating technique [31]. The circuit schematic of the switch is shown in Fig. (9). The core die area of the switch excluding pads is only 0.03 mm2. Fig. (9). Series-shunt SPDT switch with resistive body floating [31]. In this circuit for minimizing the insertion loss maximum allowed gate to channel voltage has been used for the transistors. Besides, the gate resistances keep the gate capacitance maintained so that the gate to channel voltage be almost steady throughout the duration of the signal. Thus, the power level is kept restricted only by the maximum permissible potential across the drain/source junctions (3.6 V), resulting in a higher power handling capacity. The circuit linearity improves as a result of reduced fluctuation in the gate to channel voltage and also the channel resistance. The MOSs are biased through Rbias resistances to evade forward bias of the pn-junctions from substrate to drain/source. During the conduction period of shunt transistors, DC biasing of the transmitter and receiver ports are maintained by a couple of capacitors (C1, C2) by applying RF ground to the sources of M3 and M4. A 2.4 GHz CMOS T/R switch with acceptable characteristics for radio transceiver applications was designed by Mekanand et al. (2008) in 0.5-
m CMOS process [32]. In this design, switch is incorporated by paralleling an NMOS and a PMOS as depicted in Fig. (11). The benefit of such a switch compared to a single channel MOS switch is that the dynamic range in the conducting state is greatly enlarged, which permits a full swing of signal. To facilitate achieving low insertion loss, larger size transistors are selected for the series arms whereas smaller sizes for the shunt arm or vice versa. Besides it is well known that larger devices handle higher maximum current and thus, the power-handling capacity is better. But in the nonconducting state, smaller transistors have less negative current, which helps to achieve superior power-handling capability. Considering all these factors, 180-
m MOSs for series transistors (M1 and M2) while 60-
m MOSs for shunt transistors (M3 and M4) are used. Four 5 k resistors are used for biasing the transistors to improve the linearity. The design of a very small series-shunt type T/R switch in 0.35-
m bulk CMOS technology has been described by Hove et al. (2004) [1]. The switch occupies only 0.025 mm2 of space without pads. A parasitic MOSFET model together with appropriate bulk resistance is used to optimize the sizes of the MOSs pertaining to insertion loss and isolation. The schematic of the proposed T/R switch is given in Fig. (10). Fig. (11). T/R switch using parallel NMOS and PMOS [32]. With the aim of increased linearity of the switch, the gates are biased through large resistors. DC biasing at drain and source trims down the insertion loss by decreasing the junction capacitance between source/drain to body and signal coupled to the substrate which in turn improves the power handling capacity of the switch. A control voltage of only 1.2 V is selected for both modes of operation. DIFFERENTIAL SWITCHES Fig. (10). A very small series-shunt type T/R switch schematic [1]. AND ASYMMETRIC T/R Fig. (12) presents a typical differential T/R switch, which is nothing but a combination of both series SPDT T/R switch topology illustrated in Fig. (2) and its mirror. The switch consists of a pair of transistors M1 and M3 for the transmitter and another couple of transistors M2 and M4 for the receiver. A complement control signal is needed to be applied at the gate of transistor pairs to interchange its ON/OFF position in a similar way described before. Theoretically, this type of topology exhibits 3-dB higher power-handling capability compared to its single-ended counter-part. Therefore, this topology is considered to have great advantage in contemporary micrometer CMOS technology in perspective of power-handling capability [33]. Furthermore, such a structure allows better linearity and smaller offset which makes it quite resistant to variations in supply voltage and substrate noise. Therefore, differential topology is generally favored where better signal quality is necessary [34]. Transistors M1, M2, M3, and M4 carry out the key switching job. A high control voltage Vc turns on the transistors M1 and M3, allowing the differential path in between antenna and receiver. In the same way, the differential transmit path remains ON as long as the control voltage remains low. The control voltage is applied through resistances (RG1 - RG4) to trim down the effect of capacitive coupling around the gate of the non-conducting transistors [36]. In this design, 100-
m/0.18-
m transistors and 3.9 k resistors are used to obtain best performances at 2.4 GHz. Fig. (14). Typical asymmetric SPDT T/R switch topology. Fig. (12). Typical differential SPDT T/R switch. A tiny differential T/R switch integrated in a 0.18-
m CMOS technology has been presented by Zhang et al. (2006) [35]. It occupies only 0.0024 μm2 chip area with reasonable performances. A high P1dB is attained without adopting additional techniques to increase the linearity because of the topology. This switch is suitable for moderate power level front-ends of differential transceiver. The architecture of this differential switch is shown in Fig. (13). Fig. (13). A tiny differential T/R switch [35]. Fig. (14) demonstrates a T/R switch in asymmetric topology. It is obtained as a result of alteration to the usual structure of series-shunt T/R switch, given in Fig. (4), by substituting transistor M2 with stepped impedance in the receiver path and removing transistor M3 in the transmitter section. The stepped impedance section, consisting of resonant LC network, offers high impedance during transmit mode but very little impedance at receive mode. The asymmetric topology can fulfil different asymmetric requirements of T/R switch satisfactorily [37]. For example, larger powerhandling capacity is desirable for the transmission purpose rather than for reception because the signal strength from the transmitter can be more than 30 dBm whereas the received signal strength from the antenna is, in general, less than -30 dBm [38,39]. Talwalkar et al. (2004) designed low loss and highly linear integrated CMOS T/R switches of 1 mm2 in a 0.18-
m standard CMOS process for 2.4 and 5.2 GHz wireless applications [40]. In these designs, low insertion loss and high linearity are achieved due to the increment of the substrate resistance of a MOSFET at the operating frequency using an accurately tuned LC tank circuit. In the schematic for 2.4 GHz band, shown in Fig. (15), M1 and M2 are multifinger NMOS devices with 13-
m finger width. L1 and L2 are spiral inductors with patterned ground shield (PGS) [41]. The capacitors C1, C2a and C2b are realized by metal–oxide–metal sandwiched capacitors, whereas biasing resistances (Rb1– Rb4) are fabricated by nonsilicided n+ poly. The parasitic capacitance caused by the probing pad of the antenna is soaked up into C2a whilst the drain capacitance of M2 is absorbed into C2b. Therefore, designing T/R switches with adequate performance becomes more challenging in bulk CMOS technology [42,43]. Fig. (15). Asymmetric T/R switch [40]. In the transmit mode, the application of control voltage Vc causes the transistors M1 and M2 to operate in the linear region with low on state resistance. The drain of M2 pulled to GND and the LNA is properly protected. Besides L2 and C2a form a parallel tank that resonates at the operating frequency providing a high impedance path to the receiver path. Similarly the L1, C1 pair resonates at the operating frequency to make the substrate node of M1 high impedance thus for reducing the substrate loss. This pair along with the large bias resistor Rb1 permits a large ac voltage to be applied at the transmitter but keeps the potential difference between any two terminals of M1 less than VDD. On the other hand, in the receive mode, the Vc is set to ground which cut off M1 and M2. As a result M1 isolates the PA from antenna whereas the
network (C2a, L2 and C2b) match the LNA to antenna. Resistors Rb3 and Rb4 DC bias the drain terminals of M1 and M2 to VDD to curtail the parasitic drain capacitances of the corresponding transistors. Table 1 illustrates the performances of recently reported CMOS switches for 2.4 GHz applications. DISCUSSIONS A T/R-switch (SW) is one of the essential RF front-end blocks to realize a compact wireless transceiver. In modern transceivers, despite of bigger sizes and high power consumptions, T/R switches are normally employed using board level external devices such as MEMSs, MESFETs, PHEMTs, PIN diodes etc. for their excellent small signal performance and linearity. Even though silicon technology has ameliorated the switching characteristics of MOSFETs, CMOS T/R switches which are still incapable of meeting requirements satisfactorily for most wireless applications [13]. For instance, a report on T/R switches in CMOS technology with tolerable linearity is yet to be published to deal approximately 1 W transmitter power. In CMOS T/R switch fabrication, the critical design considerations include mainly low insertion loss, high isolation and high power-handling capability. But regrettably, these performances commonly are trade-offs with each other. On-resistance of the MOS transistor is one of the leading issues for the determination of insertion loss [44]. Huang and O evaluated the value of substrate resistance and parasitic capacitance for which insertion loss is at minimum [13] and they suggested increasing or decreasing the substrate resistance [39,45] to achieve low insertion loss. It is also studied that the ratio of the size for the series to shunt transistor significantly influences the insertion loss of the switch. The low insertion loss is attained by proper transistor width optimization and bias voltages. Reduced source/drain-to-body capacitances as well as substrate resistances also help to lessen the insertion loss [31]. Besides increased DC biasing of transistor source/drain terminals causes an increase in channel resistance and decrease in junction capacitances. The use of high resistivity substrate, thick metallization, thick interconnects on a thick, low dielectric constant passivated film such as polyimide etc. help reducing insertion loss [23]. Isolation of a T/R switch rigorously counts on technology [36]. In CMOS processes, it is completely dependent on the drain and source parasitics [23]; an increase in gate width results in a degradation of isolation performance. Besides in series-shunt topology, shunt MOSs are used to improve the isolation by providing a low-impedance route for the unwanted signals to the RF ground [46]. However, the use of more transistors may cause accidental turn-on and therefore, degrades the linearity [47]. The use of parallel resonance using appropriate valued inductors can also improve the isolation. The power handling capacity (P1dB) of a switch is directly associated with the bias condition as well as sizes of the MOS transistors. The unintended turn-on of the OFF MOSs also deforms the signal which implies that the DC bias of the transmitter/receiver terminals has significant effect on the linearity [34]. Therefore, to achieve better linearity, high DC bias and high control voltage are frequently used [48,49]. Besides in conduction state, transistors with large widths exhibit higher maximum current and thus, their power-handling capability is better. But in non-conducting state, the smaller MOSs experience less negative current, which helps to attain a better power-handling capability. Therefore, selection of appropriate sizes of the transistors is very important in terms of power handling capabilities of T/R switches. Instead of a single channel MOS switch, parallel NMOS and PMOS can result in improvements in the linearity of the switch due to the augmentation in dynamic range [50]. The use of asymmetric MOSFEt along with conventional transistors is also found to have better power handling capability of the switch due to removal of drain extension [50]. It is also a good practice to isolate the body from the substrate using triple-well MOS devices for improvement in the power performance [48]. In order to improve the overall performance of the CMOS switch, application of body-floating in different forms such as LC tuned [40], resistive [31], double well [34], switched [45] etc., techniques is quite useful after selecting the appropriate width and length of the transistors [28]. The gate resistances, used with control voltages, are found to Table 1. Ref. Performance comparison of 2.4 GHz CMOS T/R switches. Year CMOS Technology Topology Isolation (dB) P1dB (dBm) IL (dB) Die area Comments 2 (mm ) [23] 2001 0.18-
m Series and seriesshunt -24 11 -1.5 0.45 * Optimizing gate width [29] 2001 0.18-
m Series-shunt 24.4 17 0.8 0.28 Optimizing transistor widths and DC biasing [40] 2004 0.18-
m Asymmetric 32 (Tx) and 17 (Rx) 28.5 (Tx) and 12.5 (Rx) 0.56 1.5 (Tx) and 1.6 (Rx) Increasing the substrate impedance by properly tuned LC circuit [1] 2004 0.35-
m Series-shunt 42 16 1.3 0.026 Parasitic MOSFET model [30] 2004 0.18-
m Series- shunt 20.6 20.6 1.1 0.28 Impedance transformation [28] 2005 0.25-
m Series 17.6 18.6 2 - Transistor sizing [35] 2006 0.18-
m differential 15 15 <2 0.0024 Transistor sizing and matching [31] 2006 0.18-
m Series-shunt [32] 2008 O.5-
m Series-shunt 35 21.3 0.7 25.33 1.085 (Tx) and 1.102 (Rx) - 0.03 Body-floating DC - Biasing of the switch [48] 2008 65-nm Asymmetric 28 29 0.8 (Tx) and 1.6 (Rx) 0.2 Optimizing the matching network [50] 2012 0.18-
m Series-shunt 35 (Tx) and 33 (Rx) 29.2 (Tx) and 23.2 (Rx) 0.62 (Tx) and 0.7 (Rx) 0.125 Using asymmetric MOSFETs *including pads affect the switching time which is important to keep the gate to channel voltage constant during the signal period. Impedance matching of T/R switch ports with other transceiver terminals is imperative for high performance operation. But, the integration of T/R switch with other front-end components like band pass filter, antenna etc. has already been started [51] and it is expected that the T/R switch will be merged with other front-end components in the near future. end and will contribute to realize low-cost, small-size wireless communication terminals at 2.4 GHz ISM band. CONCLUSIONS This work is supported by the research grant Arus Perdana (UKM-AP-ICT-20-2010) from Universiti Kebangsaan Malaysia and the Ministry of Science, Technology and Innovation (MOSTI), respectively. Fully integrated CMOS T/R switches have numerous advantages over conventional external switches. A detailed review on the advancement of CMOS T/R switches in different topologies for 2.4 GHz ISM band applications has been portrayed in this paper with adequate schematic diagrams and performance analyses. Several techniques have been implemented by different researchers to obtain better switch in CMOS technology. It is anticipated that the procedures of T/R switch design and the associated discussions presented in this paper will help the researchers in designing RF front- CONFLICT OF INTEREST The authors confirm that this article content has no conflicts of interest. ACKNOWLEDGEMENTS REFERENCES [1] [2] Hove, C.; Faaborg, J.L.; Jenner, M.B.; Lindfors, S. 0.35
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